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-rw-r--r--arch/arm/mach-imx/clk-imx35.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 920a8cc42726..c6422fb10bae 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -201,7 +201,6 @@ int __init mx35_clocks_init()
201 pr_err("i.MX35 clk %d: register failed with %ld\n", 201 pr_err("i.MX35 clk %d: register failed with %ld\n",
202 i, PTR_ERR(clk[i])); 202 i, PTR_ERR(clk[i]));
203 203
204
205 clk_register_clkdev(clk[pata_gate], NULL, "pata_imx"); 204 clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
206 clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0"); 205 clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
207 clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1"); 206 clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
@@ -264,6 +263,14 @@ int __init mx35_clocks_init()
264 clk_prepare_enable(clk[iim_gate]); 263 clk_prepare_enable(clk[iim_gate]);
265 clk_prepare_enable(clk[emi_gate]); 264 clk_prepare_enable(clk[emi_gate]);
266 265
266 /*
267 * SCC is needed to boot via mmc after a watchdog reset. The clock code
268 * before conversion to common clk also enabled UART1 (which isn't
269 * handled here and not needed for mmc) and IIM (which is enabled
270 * unconditionally above).
271 */
272 clk_prepare_enable(clk[scc_gate]);
273
267 imx_print_silicon_rev("i.MX35", mx35_revision()); 274 imx_print_silicon_rev("i.MX35", mx35_revision());
268 275
269#ifdef CONFIG_MXC_USE_EPIT 276#ifdef CONFIG_MXC_USE_EPIT