1 files changed, 146 insertions, 72 deletions

diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 86964d2e9e1b..0d59be3fa1fe 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/syscore_ops.h>
 
 #include <plat/cpu-freq.h>
 #include <plat/clock.h>
@@ -20,26 +21,93 @@
 #include <plat/pll.h>
 #include <plat/s5p-clock.h>
 #include <plat/clock-clksrc.h>
+#include <plat/exynos4.h>
+#include <plat/pm.h>
 
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 #include <mach/sysmmu.h>
-
-static struct clk clk_sclk_hdmi27m = {
+#include <mach/exynos4-clock.h>
+
+static struct sleep_save exynos4_clock_save[] = {
+        SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
+        SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
+        SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
+        SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
+        SAVE_ITEM(S5P_CLKSRC_TOP0),
+        SAVE_ITEM(S5P_CLKSRC_TOP1),
+        SAVE_ITEM(S5P_CLKSRC_CAM),
+        SAVE_ITEM(S5P_CLKSRC_TV),
+        SAVE_ITEM(S5P_CLKSRC_MFC),
+        SAVE_ITEM(S5P_CLKSRC_G3D),
+        SAVE_ITEM(S5P_CLKSRC_LCD0),
+        SAVE_ITEM(S5P_CLKSRC_MAUDIO),
+        SAVE_ITEM(S5P_CLKSRC_FSYS),
+        SAVE_ITEM(S5P_CLKSRC_PERIL0),
+        SAVE_ITEM(S5P_CLKSRC_PERIL1),
+        SAVE_ITEM(S5P_CLKDIV_CAM),
+        SAVE_ITEM(S5P_CLKDIV_TV),
+        SAVE_ITEM(S5P_CLKDIV_MFC),
+        SAVE_ITEM(S5P_CLKDIV_G3D),
+        SAVE_ITEM(S5P_CLKDIV_LCD0),
+        SAVE_ITEM(S5P_CLKDIV_MAUDIO),
+        SAVE_ITEM(S5P_CLKDIV_FSYS0),
+        SAVE_ITEM(S5P_CLKDIV_FSYS1),
+        SAVE_ITEM(S5P_CLKDIV_FSYS2),
+        SAVE_ITEM(S5P_CLKDIV_FSYS3),
+        SAVE_ITEM(S5P_CLKDIV_PERIL0),
+        SAVE_ITEM(S5P_CLKDIV_PERIL1),
+        SAVE_ITEM(S5P_CLKDIV_PERIL2),
+        SAVE_ITEM(S5P_CLKDIV_PERIL3),
+        SAVE_ITEM(S5P_CLKDIV_PERIL4),
+        SAVE_ITEM(S5P_CLKDIV_PERIL5),
+        SAVE_ITEM(S5P_CLKDIV_TOP),
+        SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
+        SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
+        SAVE_ITEM(S5P_CLKSRC_MASK_TV),
+        SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
+        SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
+        SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
+        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
+        SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
+        SAVE_ITEM(S5P_CLKDIV2_RATIO),
+        SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
+        SAVE_ITEM(S5P_CLKGATE_IP_CAM),
+        SAVE_ITEM(S5P_CLKGATE_IP_TV),
+        SAVE_ITEM(S5P_CLKGATE_IP_MFC),
+        SAVE_ITEM(S5P_CLKGATE_IP_G3D),
+        SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
+        SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
+        SAVE_ITEM(S5P_CLKGATE_IP_GPS),
+        SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
+        SAVE_ITEM(S5P_CLKGATE_BLOCK),
+        SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
+        SAVE_ITEM(S5P_CLKSRC_DMC),
+        SAVE_ITEM(S5P_CLKDIV_DMC0),
+        SAVE_ITEM(S5P_CLKDIV_DMC1),
+        SAVE_ITEM(S5P_CLKGATE_IP_DMC),
+        SAVE_ITEM(S5P_CLKSRC_CPU),
+        SAVE_ITEM(S5P_CLKDIV_CPU),
+        SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
+        SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
+        SAVE_ITEM(S5P_CLKGATE_IP_CPU),
+};
+
+struct clk clk_sclk_hdmi27m = {
         .name           = "sclk_hdmi27m",
         .rate           = 27000000,
 };
 
-static struct clk clk_sclk_hdmiphy = {
+struct clk clk_sclk_hdmiphy = {
         .name           = "sclk_hdmiphy",
 };
 
-static struct clk clk_sclk_usbphy0 = {
+struct clk clk_sclk_usbphy0 = {
         .name           = "sclk_usbphy0",
         .rate           = 27000000,
 };
 
-static struct clk clk_sclk_usbphy1 = {
+struct clk clk_sclk_usbphy1 = {
         .name           = "sclk_usbphy1",
 };
 
@@ -58,12 +126,7 @@ static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
 }
 
-static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
-}
-
-static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
 }
@@ -103,12 +166,12 @@ static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
 }
 
-static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
 }
 
-static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
 }
@@ -133,7 +196,7 @@ static struct clksrc_clk clk_mout_apll = {
         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
 };
 
-static struct clksrc_clk clk_sclk_apll = {
+struct clksrc_clk clk_sclk_apll = {
         .clk    = {
                 .name           = "sclk_apll",
                 .parent         = &clk_mout_apll.clk,
@@ -141,7 +204,7 @@ static struct clksrc_clk clk_sclk_apll = {
         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
 };
 
-static struct clksrc_clk clk_mout_epll = {
+struct clksrc_clk clk_mout_epll = {
         .clk    = {
                 .name           = "mout_epll",
         },
@@ -149,12 +212,13 @@ static struct clksrc_clk clk_mout_epll = {
         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
 };
 
-static struct clksrc_clk clk_mout_mpll = {
+struct clksrc_clk clk_mout_mpll = {
         .clk = {
                 .name           = "mout_mpll",
         },
         .sources        = &clk_src_mpll,
-        .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
+
+        /* reg_src will be added in each SoCs' clock */
 };
 
 static struct clk *clkset_moutcore_list[] = {
@@ -224,12 +288,12 @@ static struct clksrc_clk clk_periphclk = {
 
 /* Core list of CMU_CORE side */
 
-static struct clk *clkset_corebus_list[] = {
+struct clk *clkset_corebus_list[] = {
         [0] = &clk_mout_mpll.clk,
         [1] = &clk_sclk_apll.clk,
 };
 
-static struct clksrc_sources clkset_mout_corebus = {
+struct clksrc_sources clkset_mout_corebus = {
         .sources        = clkset_corebus_list,
         .nr_sources     = ARRAY_SIZE(clkset_corebus_list),
 };
@@ -284,12 +348,12 @@ static struct clksrc_clk clk_pclk_acp = {
 
 /* Core list of CMU_TOP side */
 
-static struct clk *clkset_aclk_top_list[] = {
+struct clk *clkset_aclk_top_list[] = {
         [0] = &clk_mout_mpll.clk,
         [1] = &clk_sclk_apll.clk,
 };
 
-static struct clksrc_sources clkset_aclk = {
+struct clksrc_sources clkset_aclk = {
         .sources        = clkset_aclk_top_list,
         .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
 };
@@ -321,7 +385,7 @@ static struct clksrc_clk clk_aclk_160 = {
         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
 };
 
-static struct clksrc_clk clk_aclk_133 = {
+struct clksrc_clk clk_aclk_133 = {
         .clk    = {
                 .name           = "aclk_133",
         },
@@ -360,7 +424,7 @@ static struct clksrc_sources clkset_sclk_vpll = {
         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 };
 
-static struct clksrc_clk clk_sclk_vpll = {
+struct clksrc_clk clk_sclk_vpll = {
         .clk    = {
                 .name           = "sclk_vpll",
         },
@@ -410,16 +474,6 @@ static struct clk init_clocks_off[] = {
                 .enable         = exynos4_clk_ip_lcd0_ctrl,
                 .ctrlbit        = (1 << 0),
         }, {
-                .name           = "fimd",
-                .devname        = "exynos4-fb.1",
-                .enable         = exynos4_clk_ip_lcd1_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "sataphy",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 3),
-        }, {
                 .name           = "hsmmc",
                 .devname        = "s3c-sdhci.0",
                 .parent         = &clk_aclk_133.clk,
@@ -449,11 +503,6 @@ static struct clk init_clocks_off[] = {
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 9),
         }, {
-                .name           = "sata",
-                .parent         = &clk_aclk_133.clk,
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 10),
-        }, {
                 .name           = "pdma",
                 .devname        = "s3c-pl330.0",
                 .enable         = exynos4_clk_ip_fsys_ctrl,
@@ -673,7 +722,7 @@ static struct clk init_clocks[] = {
         }
 };
 
-static struct clk *clkset_group_list[] = {
+struct clk *clkset_group_list[] = {
         [0] = &clk_ext_xtal_mux,
         [1] = &clk_xusbxti,
         [2] = &clk_sclk_hdmi27m,
@@ -685,7 +734,7 @@ static struct clk *clkset_group_list[] = {
         [8] = &clk_sclk_vpll.clk,
 };
 
-static struct clksrc_sources clkset_group = {
+struct clksrc_sources clkset_group = {
         .sources        = clkset_group_list,
         .nr_sources     = ARRAY_SIZE(clkset_group_list),
 };
@@ -967,25 +1016,6 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
         }, {
                 .clk            = {
-                        .name           = "sclk_fimd",
-                        .devname        = "exynos4-fb.1",
-                        .enable         = exynos4_clksrc_mask_lcd1_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_sata",
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &clkset_mout_corebus,
-                .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
-        }, {
-                .clk            = {
                         .name           = "sclk_spi",
                         .devname        = "s3c64xx-spi.0",
                         .enable         = exynos4_clksrc_mask_peril1_ctrl,
@@ -1114,7 +1144,13 @@ static int xtal_rate;
 
 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
 {
-        return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
+        if (soc_is_exynos4210())
+                return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
+                                        pll_4508);
+        else if (soc_is_exynos4212() || soc_is_exynos4412())
+                return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
+        else
+                return 0;
 }
 
 static struct clk_ops exynos4_fout_apll_ops = {
@@ -1124,10 +1160,10 @@ static struct clk_ops exynos4_fout_apll_ops = {
 void __init_or_cpufreq exynos4_setup_clocks(void)
 {
         struct clk *xtal_clk;
-        unsigned long apll;
-        unsigned long mpll;
-        unsigned long epll;
-        unsigned long vpll;
+        unsigned long apll = 0;
+        unsigned long mpll = 0;
+        unsigned long epll = 0;
+        unsigned long vpll = 0;
         unsigned long vpllsrc;
         unsigned long xtal;
         unsigned long armclk;
@@ -1151,14 +1187,29 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
 
         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 
-        apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
-        mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
-        epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
-                                __raw_readl(S5P_EPLL_CON1), pll_4600);
-
-        vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
-        vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
-                                __raw_readl(S5P_VPLL_CON1), pll_4650c);
+        if (soc_is_exynos4210()) {
+                apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
+                                        pll_4508);
+                mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
+                                        pll_4508);
+                epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
+                                        __raw_readl(S5P_EPLL_CON1), pll_4600);
+
+                vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
+                vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
+                                        __raw_readl(S5P_VPLL_CON1), pll_4650c);
+        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+                apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
+                mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
+                epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
+                                        __raw_readl(S5P_EPLL_CON1));
+
+                vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
+                vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
+                                        __raw_readl(S5P_VPLL_CON1));
+        } else {
+                /* nothing */
+        }
 
         clk_fout_apll.ops = &exynos4_fout_apll_ops;
         clk_fout_mpll.rate = mpll;
@@ -1193,6 +1244,28 @@ static struct clk *clks[] __initdata = {
         /* Nothing here yet */
 };
 
+#ifdef CONFIG_PM_SLEEP
+static int exynos4_clock_suspend(void)
+{
+        s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+        return 0;
+}
+
+static void exynos4_clock_resume(void)
+{
+        s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+}
+
+#else
+#define exynos4_clock_suspend NULL
+#define exynos4_clock_resume NULL
+#endif
+
+struct syscore_ops exynos4_clock_syscore_ops = {
+        .suspend        = exynos4_clock_suspend,
+        .resume         = exynos4_clock_resume,
+};
+
 void __init exynos4_register_clocks(void)
 {
         int ptr;
@@ -1208,5 +1281,6 @@ void __init exynos4_register_clocks(void)
         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 
+        register_syscore_ops(&exynos4_clock_syscore_ops);
         s3c_pwmclk_init();
 }