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-rw-r--r--arch/arm/configs/exynos4_defconfig1
-rw-r--r--arch/arm/configs/mxs_defconfig1
-rw-r--r--arch/arm/mach-at91/Kconfig13
-rw-r--r--arch/arm/mach-at91/Makefile6
-rw-r--r--arch/arm/mach-at91/board-rsi-ews.c233
-rw-r--r--arch/arm/mach-at91/board-usb-a9260.c230
-rw-r--r--arch/arm/mach-at91/board-usb-a926x.c (renamed from arch/arm/mach-at91/board-usb-a9263.c)181
-rw-r--r--arch/arm/mach-at91/include/mach/timex.h5
-rw-r--r--arch/arm/mach-ep93xx/Kconfig7
-rw-r--r--arch/arm/mach-ep93xx/Makefile1
-rw-r--r--arch/arm/mach-ep93xx/vision_ep9307.c364
-rw-r--r--arch/arm/mach-exynos4/Kconfig54
-rw-r--r--arch/arm/mach-exynos4/Makefile10
-rw-r--r--arch/arm/mach-exynos4/clock-exynos4210.c139
-rw-r--r--arch/arm/mach-exynos4/clock-exynos4212.c118
-rw-r--r--arch/arm/mach-exynos4/clock.c218
-rw-r--r--arch/arm/mach-exynos4/cpu.c57
-rw-r--r--arch/arm/mach-exynos4/include/mach/entry-macro.S23
-rw-r--r--arch/arm/mach-exynos4/include/mach/exynos4-clock.h43
-rw-r--r--arch/arm/mach-exynos4/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-exynos4/include/mach/map.h4
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-clock.h54
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-mct.h5
-rw-r--r--arch/arm/mach-exynos4/mach-origen.c108
-rw-r--r--arch/arm/mach-exynos4/mach-smdk4x12.c302
-rw-r--r--arch/arm/mach-exynos4/mct.c165
-rw-r--r--arch/arm/mach-exynos4/platsmp.c13
-rw-r--r--arch/arm/mach-exynos4/pm.c79
-rw-r--r--arch/arm/mach-ixp4xx/Kconfig19
-rw-r--r--arch/arm/mach-ixp4xx/Makefile4
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/uncompress.h3
-rw-r--r--arch/arm/mach-ixp4xx/miccpt-pci.c78
-rw-r--r--arch/arm/mach-ixp4xx/omixp-setup.c273
-rw-r--r--arch/arm/mach-mxs/Kconfig17
-rw-r--r--arch/arm/mach-mxs/Makefile1
-rw-r--r--arch/arm/mach-mxs/clock-mx28.c16
-rw-r--r--arch/arm/mach-mxs/include/mach/mxs.h1
-rw-r--r--arch/arm/mach-mxs/include/mach/uncompress.h1
-rw-r--r--arch/arm/mach-mxs/mach-m28evk.c366
-rw-r--r--arch/arm/mach-s3c64xx/cpu.c22
-rw-r--r--arch/arm/mach-s5p64x0/dev-spi.c8
-rw-r--r--arch/arm/mach-s5p64x0/dma.c7
-rw-r--r--arch/arm/mach-s5p64x0/gpiolib.c7
-rw-r--r--arch/arm/mach-s5p64x0/irq-eint.c3
-rw-r--r--arch/arm/mach-tegra/board-harmony.c5
-rw-r--r--arch/arm/mach-tegra/board-paz00-pinmux.c3
-rw-r--r--arch/arm/mach-tegra/board-paz00.c64
-rw-r--r--arch/arm/mach-tegra/board-paz00.h8
-rw-r--r--arch/arm/mach-tegra/board-seaboard-pinmux.c6
-rw-r--r--arch/arm/mach-tegra/board-seaboard.c81
-rw-r--r--arch/arm/mach-tegra/board-seaboard.h12
-rw-r--r--arch/arm/mach-tegra/board-trimslice.c4
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c9
-rw-r--r--arch/arm/plat-s5p/cpu.c46
-rw-r--r--arch/arm/plat-s5p/include/plat/exynos4.h5
-rw-r--r--arch/arm/plat-s5p/include/plat/pll.h55
-rw-r--r--arch/arm/plat-samsung/Makefile2
-rw-r--r--arch/arm/plat-samsung/cpu.c58
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h113
59 files changed, 3147 insertions, 586 deletions
diff --git a/arch/arm/configs/exynos4_defconfig b/arch/arm/configs/exynos4_defconfig
index da53ff3b4d70..cd40bb56e568 100644
--- a/arch/arm/configs/exynos4_defconfig
+++ b/arch/arm/configs/exynos4_defconfig
@@ -11,6 +11,7 @@ CONFIG_MACH_SMDKV310=y
11CONFIG_MACH_ARMLEX4210=y 11CONFIG_MACH_ARMLEX4210=y
12CONFIG_MACH_UNIVERSAL_C210=y 12CONFIG_MACH_UNIVERSAL_C210=y
13CONFIG_MACH_NURI=y 13CONFIG_MACH_NURI=y
14CONFIG_MACH_ORIGEN=y
14CONFIG_NO_HZ=y 15CONFIG_NO_HZ=y
15CONFIG_HIGH_RES_TIMERS=y 16CONFIG_HIGH_RES_TIMERS=y
16CONFIG_SMP=y 17CONFIG_SMP=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index db2cb7d180dc..6ee781bf6bf1 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -26,6 +26,7 @@ CONFIG_MACH_MX23EVK=y
26CONFIG_MACH_MX28EVK=y 26CONFIG_MACH_MX28EVK=y
27CONFIG_MACH_STMP378X_DEVB=y 27CONFIG_MACH_STMP378X_DEVB=y
28CONFIG_MACH_TX28=y 28CONFIG_MACH_TX28=y
29CONFIG_MACH_M28EVK=y
29# CONFIG_ARM_THUMB is not set 30# CONFIG_ARM_THUMB is not set
30CONFIG_NO_HZ=y 31CONFIG_NO_HZ=y
31CONFIG_HIGH_RES_TIMERS=y 32CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 22484670e7ba..04a85c546abc 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -182,6 +182,11 @@ config MACH_ECO920
182 help 182 help
183 Select this if you are using the eco920 board 183 Select this if you are using the eco920 board
184 184
185config MACH_RSI_EWS
186 bool "RSI Embedded Webserver"
187 depends on ARCH_AT91RM9200
188 help
189 Select this if you are using RSIs EWS board.
185endif 190endif
186 191
187# ---------------------------------------------------------- 192# ----------------------------------------------------------
@@ -381,6 +386,14 @@ config MACH_GSIA18S
381 This enables support for the GS_IA18_S board 386 This enables support for the GS_IA18_S board
382 produced by GeoSIG Ltd company. This is an internet accelerograph. 387 produced by GeoSIG Ltd company. This is an internet accelerograph.
383 <http://www.geosig.com> 388 <http://www.geosig.com>
389
390config MACH_USB_A9G20
391 bool "CALAO USB-A9G20"
392 depends on ARCH_AT91SAM9G20
393 help
394 Select this if you are using a Calao Systems USB-A9G20.
395 <http://www.calao-systems.com>
396
384endif 397endif
385 398
386if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) 399if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index bf57e8b1c9d0..d992dd5d9321 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -36,12 +36,13 @@ obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o
36obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o 36obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o
37obj-$(CONFIG_MACH_CPUAT91) += board-cpuat91.o 37obj-$(CONFIG_MACH_CPUAT91) += board-cpuat91.o
38obj-$(CONFIG_MACH_ECO920) += board-eco920.o 38obj-$(CONFIG_MACH_ECO920) += board-eco920.o
39obj-$(CONFIG_MACH_RSI_EWS) += board-rsi-ews.o
39 40
40# AT91SAM9260 board-specific support 41# AT91SAM9260 board-specific support
41obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o 42obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
42obj-$(CONFIG_MACH_CAM60) += board-cam60.o 43obj-$(CONFIG_MACH_CAM60) += board-cam60.o
43obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o 44obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o
44obj-$(CONFIG_MACH_USB_A9260) += board-usb-a9260.o 45obj-$(CONFIG_MACH_USB_A9260) += board-usb-a926x.o
45obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o 46obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o
46obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o 47obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o
47obj-$(CONFIG_MACH_CPU9260) += board-cpu9krea.o 48obj-$(CONFIG_MACH_CPU9260) += board-cpu9krea.o
@@ -53,7 +54,7 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
53 54
54# AT91SAM9263 board-specific support 55# AT91SAM9263 board-specific support
55obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o 56obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
56obj-$(CONFIG_MACH_USB_A9263) += board-usb-a9263.o 57obj-$(CONFIG_MACH_USB_A9263) += board-usb-a926x.o
57obj-$(CONFIG_MACH_NEOCORE926) += board-neocore926.o 58obj-$(CONFIG_MACH_NEOCORE926) += board-neocore926.o
58 59
59# AT91SAM9RL board-specific support 60# AT91SAM9RL board-specific support
@@ -67,6 +68,7 @@ obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o
67obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o 68obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o
68obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o 69obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
69obj-$(CONFIG_MACH_GSIA18S) += board-gsia18s.o board-stamp9g20.o 70obj-$(CONFIG_MACH_GSIA18S) += board-gsia18s.o board-stamp9g20.o
71obj-$(CONFIG_MACH_USB_A9G20) += board-usb-a926x.o
70 72
71# AT91SAM9260/AT91SAM9G20 board-specific support 73# AT91SAM9260/AT91SAM9G20 board-specific support
72obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o 74obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
new file mode 100644
index 000000000000..e927df0175df
--- /dev/null
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -0,0 +1,233 @@
1/*
2 * board-rsi-ews.c
3 *
4 * Copyright (C)
5 * 2005 SAN People,
6 * 2008-2011 R-S-I Elektrotechnik GmbH & Co. KG
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/mm.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/spi/spi.h>
17#include <linux/mtd/physmap.h>
18
19#include <asm/setup.h>
20#include <asm/mach-types.h>
21#include <asm/irq.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26
27#include <mach/hardware.h>
28#include <mach/board.h>
29
30#include <linux/gpio.h>
31
32#include "generic.h"
33
34static void __init rsi_ews_init_early(void)
35{
36 /* Initialize processor: 18.432 MHz crystal */
37 at91_initialize(18432000);
38
39 /* Setup the LEDs */
40 at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9);
41
42 /* DBGU on ttyS0. (Rx & Tx only) */
43 /* This one is for debugging */
44 at91_register_uart(0, 0, 0);
45
46 /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
47 /* Dialin/-out modem interface */
48 at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
49 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
50 | ATMEL_UART_RI);
51
52 /* USART3 on ttyS4. (Rx, Tx, RTS) */
53 /* RS485 communication */
54 at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS);
55
56 /* set serial console to ttyS0 (ie, DBGU) */
57 at91_set_serial_console(0);
58}
59
60/*
61 * Ethernet
62 */
63static struct at91_eth_data rsi_ews_eth_data __initdata = {
64 .phy_irq_pin = AT91_PIN_PC4,
65 .is_rmii = 1,
66};
67
68/*
69 * USB Host
70 */
71static struct at91_usbh_data rsi_ews_usbh_data __initdata = {
72 .ports = 1,
73};
74
75/*
76 * SD/MC
77 */
78static struct at91_mmc_data rsi_ews_mmc_data __initdata = {
79 .slot_b = 0,
80 .wire4 = 1,
81 .det_pin = AT91_PIN_PB27,
82 .wp_pin = AT91_PIN_PB29,
83};
84
85/*
86 * I2C
87 */
88static struct i2c_board_info rsi_ews_i2c_devices[] __initdata = {
89 {
90 I2C_BOARD_INFO("ds1337", 0x68),
91 },
92 {
93 I2C_BOARD_INFO("24c01", 0x50),
94 }
95};
96
97/*
98 * LEDs
99 */
100static struct gpio_led rsi_ews_leds[] = {
101 {
102 .name = "led0",
103 .gpio = AT91_PIN_PB6,
104 .active_low = 0,
105 },
106 {
107 .name = "led1",
108 .gpio = AT91_PIN_PB7,
109 .active_low = 0,
110 },
111 {
112 .name = "led2",
113 .gpio = AT91_PIN_PB8,
114 .active_low = 0,
115 },
116 {
117 .name = "led3",
118 .gpio = AT91_PIN_PB9,
119 .active_low = 0,
120 },
121};
122
123/*
124 * DataFlash
125 */
126static struct spi_board_info rsi_ews_spi_devices[] = {
127 { /* DataFlash chip 1*/
128 .modalias = "mtd_dataflash",
129 .chip_select = 0,
130 .max_speed_hz = 5 * 1000 * 1000,
131 },
132 { /* DataFlash chip 2*/
133 .modalias = "mtd_dataflash",
134 .chip_select = 1,
135 .max_speed_hz = 5 * 1000 * 1000,
136 },
137};
138
139/*
140 * NOR flash
141 */
142static struct mtd_partition rsiews_nor_partitions[] = {
143 {
144 .name = "boot",
145 .offset = 0,
146 .size = 3 * SZ_128K,
147 .mask_flags = MTD_WRITEABLE
148 },
149 {
150 .name = "kernel",
151 .offset = MTDPART_OFS_NXTBLK,
152 .size = SZ_2M - (3 * SZ_128K)
153 },
154 {
155 .name = "root",
156 .offset = MTDPART_OFS_NXTBLK,
157 .size = SZ_8M
158 },
159 {
160 .name = "kernelupd",
161 .offset = MTDPART_OFS_NXTBLK,
162 .size = 3 * SZ_512K,
163 .mask_flags = MTD_WRITEABLE
164 },
165 {
166 .name = "rootupd",
167 .offset = MTDPART_OFS_NXTBLK,
168 .size = 9 * SZ_512K,
169 .mask_flags = MTD_WRITEABLE
170 },
171};
172
173static struct physmap_flash_data rsiews_nor_data = {
174 .width = 2,
175 .parts = rsiews_nor_partitions,
176 .nr_parts = ARRAY_SIZE(rsiews_nor_partitions),
177};
178
179#define NOR_BASE AT91_CHIPSELECT_0
180#define NOR_SIZE SZ_16M
181
182static struct resource nor_flash_resources[] = {
183 {
184 .start = NOR_BASE,
185 .end = NOR_BASE + NOR_SIZE - 1,
186 .flags = IORESOURCE_MEM,
187 }
188};
189
190static struct platform_device rsiews_nor_flash = {
191 .name = "physmap-flash",
192 .id = 0,
193 .dev = {
194 .platform_data = &rsiews_nor_data,
195 },
196 .resource = nor_flash_resources,
197 .num_resources = ARRAY_SIZE(nor_flash_resources),
198};
199
200/*
201 * Init Func
202 */
203static void __init rsi_ews_board_init(void)
204{
205 /* Serial */
206 at91_add_device_serial();
207 at91_set_gpio_output(AT91_PIN_PA21, 0);
208 /* Ethernet */
209 at91_add_device_eth(&rsi_ews_eth_data);
210 /* USB Host */
211 at91_add_device_usbh(&rsi_ews_usbh_data);
212 /* I2C */
213 at91_add_device_i2c(rsi_ews_i2c_devices,
214 ARRAY_SIZE(rsi_ews_i2c_devices));
215 /* SPI */
216 at91_add_device_spi(rsi_ews_spi_devices,
217 ARRAY_SIZE(rsi_ews_spi_devices));
218 /* MMC */
219 at91_add_device_mmc(0, &rsi_ews_mmc_data);
220 /* NOR Flash */
221 platform_device_register(&rsiews_nor_flash);
222 /* LEDs */
223 at91_gpio_leds(rsi_ews_leds, ARRAY_SIZE(rsi_ews_leds));
224}
225
226MACHINE_START(RSI_EWS, "RSI EWS")
227 /* Maintainer: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> */
228 .timer = &at91rm9200_timer,
229 .map_io = at91_map_io,
230 .init_early = rsi_ews_init_early,
231 .init_irq = at91_init_irq_default,
232 .init_machine = rsi_ews_board_init,
233MACHINE_END
diff --git a/arch/arm/mach-at91/board-usb-a9260.c b/arch/arm/mach-at91/board-usb-a9260.c
deleted file mode 100644
index bac9b65cf551..000000000000
--- a/arch/arm/mach-at91/board-usb-a9260.c
+++ /dev/null
@@ -1,230 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-usb-a9260.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2006 Atmel
6 * Copyright (C) 2007 Calao-systems
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/types.h>
24#include <linux/gpio.h>
25#include <linux/init.h>
26#include <linux/mm.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/spi/spi.h>
30#include <linux/gpio_keys.h>
31#include <linux/input.h>
32#include <linux/clk.h>
33
34#include <asm/setup.h>
35#include <asm/mach-types.h>
36#include <asm/irq.h>
37
38#include <asm/mach/arch.h>
39#include <asm/mach/map.h>
40#include <asm/mach/irq.h>
41
42#include <mach/hardware.h>
43#include <mach/board.h>
44#include <mach/at91sam9_smc.h>
45#include <mach/at91_shdwc.h>
46
47#include "sam9_smc.h"
48#include "generic.h"
49
50
51static void __init ek_init_early(void)
52{
53 /* Initialize processor: 12.000 MHz crystal */
54 at91_initialize(12000000);
55
56 /* DBGU on ttyS0. (Rx & Tx only) */
57 at91_register_uart(0, 0, 0);
58
59 /* set serial console to ttyS0 (ie, DBGU) */
60 at91_set_serial_console(0);
61}
62
63/*
64 * USB Host port
65 */
66static struct at91_usbh_data __initdata ek_usbh_data = {
67 .ports = 2,
68};
69
70/*
71 * USB Device port
72 */
73static struct at91_udc_data __initdata ek_udc_data = {
74 .vbus_pin = AT91_PIN_PC5,
75 .pullup_pin = 0, /* pull-up driven by UDC */
76};
77
78/*
79 * MACB Ethernet device
80 */
81static struct at91_eth_data __initdata ek_macb_data = {
82 .phy_irq_pin = AT91_PIN_PA31,
83 .is_rmii = 1,
84};
85
86/*
87 * NAND flash
88 */
89static struct mtd_partition __initdata ek_nand_partition[] = {
90 {
91 .name = "Uboot & Kernel",
92 .offset = 0,
93 .size = SZ_16M,
94 },
95 {
96 .name = "Root FS",
97 .offset = MTDPART_OFS_NXTBLK,
98 .size = 120 * SZ_1M,
99 },
100 {
101 .name = "FS",
102 .offset = MTDPART_OFS_NXTBLK,
103 .size = 120 * SZ_1M,
104 }
105};
106
107static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
108{
109 *num_partitions = ARRAY_SIZE(ek_nand_partition);
110 return ek_nand_partition;
111}
112
113static struct atmel_nand_data __initdata ek_nand_data = {
114 .ale = 21,
115 .cle = 22,
116// .det_pin = ... not connected
117 .rdy_pin = AT91_PIN_PC13,
118 .enable_pin = AT91_PIN_PC14,
119 .partition_info = nand_partitions,
120};
121
122static struct sam9_smc_config __initdata ek_nand_smc_config = {
123 .ncs_read_setup = 0,
124 .nrd_setup = 1,
125 .ncs_write_setup = 0,
126 .nwe_setup = 1,
127
128 .ncs_read_pulse = 3,
129 .nrd_pulse = 3,
130 .ncs_write_pulse = 3,
131 .nwe_pulse = 3,
132
133 .read_cycle = 5,
134 .write_cycle = 5,
135
136 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
137 .tdf_cycles = 2,
138};
139
140static void __init ek_add_device_nand(void)
141{
142 /* configure chip-select 3 (NAND) */
143 sam9_smc_configure(3, &ek_nand_smc_config);
144
145 at91_add_device_nand(&ek_nand_data);
146}
147
148/*
149 * GPIO Buttons
150 */
151
152#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
153static struct gpio_keys_button ek_buttons[] = {
154 { /* USER PUSH BUTTON */
155 .code = KEY_ENTER,
156 .gpio = AT91_PIN_PB10,
157 .active_low = 1,
158 .desc = "user_pb",
159 .wakeup = 1,
160 }
161};
162
163static struct gpio_keys_platform_data ek_button_data = {
164 .buttons = ek_buttons,
165 .nbuttons = ARRAY_SIZE(ek_buttons),
166};
167
168static struct platform_device ek_button_device = {
169 .name = "gpio-keys",
170 .id = -1,
171 .num_resources = 0,
172 .dev = {
173 .platform_data = &ek_button_data,
174 }
175};
176
177static void __init ek_add_device_buttons(void)
178{
179 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
180 at91_set_deglitch(AT91_PIN_PB10, 1);
181
182 platform_device_register(&ek_button_device);
183}
184#else
185static void __init ek_add_device_buttons(void) {}
186#endif
187
188/*
189 * LEDs
190 */
191static struct gpio_led ek_leds[] = {
192 { /* user_led (green) */
193 .name = "user_led",
194 .gpio = AT91_PIN_PB21,
195 .active_low = 0,
196 .default_trigger = "heartbeat",
197 }
198};
199
200static void __init ek_board_init(void)
201{
202 /* Serial */
203 at91_add_device_serial();
204 /* USB Host */
205 at91_add_device_usbh(&ek_usbh_data);
206 /* USB Device */
207 at91_add_device_udc(&ek_udc_data);
208 /* NAND */
209 ek_add_device_nand();
210 /* I2C */
211 at91_add_device_i2c(NULL, 0);
212 /* Ethernet */
213 at91_add_device_eth(&ek_macb_data);
214 /* Push Buttons */
215 ek_add_device_buttons();
216 /* LEDs */
217 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
218 /* shutdown controller, wakeup button (5 msec low) */
219 at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
220 | AT91_SHDW_RTTWKEN);
221}
222
223MACHINE_START(USB_A9260, "CALAO USB_A9260")
224 /* Maintainer: calao-systems */
225 .timer = &at91sam926x_timer,
226 .map_io = at91_map_io,
227 .init_early = ek_init_early,
228 .init_irq = at91_init_irq_default,
229 .init_machine = ek_board_init,
230MACHINE_END
diff --git a/arch/arm/mach-at91/board-usb-a9263.c b/arch/arm/mach-at91/board-usb-a926x.c
index 5bd735787d6d..5852d3d9890c 100644
--- a/arch/arm/mach-at91/board-usb-a9263.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -1,9 +1,10 @@
1/* 1/*
2 * linux/arch/arm/mach-at91/board-usb-a9263.c 2 * linux/arch/arm/mach-at91/board-usb-a926x.c
3 * 3 *
4 * Copyright (C) 2005 SAN People 4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation. 5 * Copyright (C) 2007 Atmel Corporation.
6 * Copyright (C) 2007 Calao-systems 6 * Copyright (C) 2007 Calao-systems
7 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
@@ -21,14 +22,15 @@
21 */ 22 */
22 23
23#include <linux/types.h> 24#include <linux/types.h>
24#include <linux/gpio.h>
25#include <linux/init.h> 25#include <linux/init.h>
26#include <linux/mm.h> 26#include <linux/mm.h>
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/platform_device.h> 28#include <linux/platform_device.h>
29#include <linux/spi/spi.h> 29#include <linux/spi/spi.h>
30#include <linux/gpio_keys.h> 30#include <linux/gpio_keys.h>
31#include <linux/gpio.h>
31#include <linux/input.h> 32#include <linux/input.h>
33#include <linux/spi/mmc_spi.h>
32 34
33#include <asm/setup.h> 35#include <asm/setup.h>
34#include <asm/mach-types.h> 36#include <asm/mach-types.h>
@@ -74,10 +76,42 @@ static struct at91_udc_data __initdata ek_udc_data = {
74 .pullup_pin = 0, /* pull-up driven by UDC */ 76 .pullup_pin = 0, /* pull-up driven by UDC */
75}; 77};
76 78
79static void __init ek_add_device_udc(void)
80{
81 if (machine_is_usb_a9260() || machine_is_usb_a9g20())
82 ek_udc_data.vbus_pin = AT91_PIN_PC5;
83
84 at91_add_device_udc(&ek_udc_data);
85}
86
87#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
88#define MMC_SPI_CARD_DETECT_INT AT91_PIN_PC4
89static int at91_mmc_spi_init(struct device *dev,
90 irqreturn_t (*detect_int)(int, void *), void *data)
91{
92 /* Configure Interrupt pin as input, no pull-up */
93 at91_set_gpio_input(MMC_SPI_CARD_DETECT_INT, 0);
94 return request_irq(gpio_to_irq(MMC_SPI_CARD_DETECT_INT), detect_int,
95 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
96 "mmc-spi-detect", data);
97}
98
99static void at91_mmc_spi_exit(struct device *dev, void *data)
100{
101 free_irq(gpio_to_irq(MMC_SPI_CARD_DETECT_INT), data);
102}
103
104static struct mmc_spi_platform_data at91_mmc_spi_pdata = {
105 .init = at91_mmc_spi_init,
106 .exit = at91_mmc_spi_exit,
107 .detect_delay = 100, /* msecs */
108};
109#endif
110
77/* 111/*
78 * SPI devices. 112 * SPI devices.
79 */ 113 */
80static struct spi_board_info ek_spi_devices[] = { 114static struct spi_board_info usb_a9263_spi_devices[] = {
81#if !defined(CONFIG_MMC_AT91) 115#if !defined(CONFIG_MMC_AT91)
82 { /* DataFlash chip */ 116 { /* DataFlash chip */
83 .modalias = "mtd_dataflash", 117 .modalias = "mtd_dataflash",
@@ -88,6 +122,27 @@ static struct spi_board_info ek_spi_devices[] = {
88#endif 122#endif
89}; 123};
90 124
125static struct spi_board_info usb_a9g20_spi_devices[] = {
126#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
127 {
128 .modalias = "mmc_spi",
129 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
130 .bus_num = 1,
131 .chip_select = 0,
132 .platform_data = &at91_mmc_spi_pdata,
133 .mode = SPI_MODE_3,
134 },
135#endif
136};
137
138static void __init ek_add_device_spi(void)
139{
140 if (machine_is_usb_a9263())
141 at91_add_device_spi(usb_a9263_spi_devices, ARRAY_SIZE(usb_a9263_spi_devices));
142 else if (machine_is_usb_a9g20())
143 at91_add_device_spi(usb_a9g20_spi_devices, ARRAY_SIZE(usb_a9g20_spi_devices));
144}
145
91/* 146/*
92 * MACB Ethernet device 147 * MACB Ethernet device
93 */ 148 */
@@ -96,24 +151,42 @@ static struct at91_eth_data __initdata ek_macb_data = {
96 .is_rmii = 1, 151 .is_rmii = 1,
97}; 152};
98 153
154static void __init ek_add_device_eth(void)
155{
156 if (machine_is_usb_a9260() || machine_is_usb_a9g20())
157 ek_macb_data.phy_irq_pin = AT91_PIN_PA31;
158
159 at91_add_device_eth(&ek_macb_data);
160}
161
99/* 162/*
100 * NAND flash 163 * NAND flash
101 */ 164 */
102static struct mtd_partition __initdata ek_nand_partition[] = { 165static struct mtd_partition __initdata ek_nand_partition[] = {
103 { 166 {
104 .name = "Linux Kernel", 167 .name = "barebox",
105 .offset = 0, 168 .offset = 0,
106 .size = SZ_16M, 169 .size = 3 * SZ_128K,
107 }, 170 }, {
108 { 171 .name = "bareboxenv",
109 .name = "Root FS",
110 .offset = MTDPART_OFS_NXTBLK, 172 .offset = MTDPART_OFS_NXTBLK,
111 .size = 120 * SZ_1M, 173 .size = SZ_128K,
112 }, 174 }, {
113 { 175 .name = "bareboxenv2",
114 .name = "FS", 176 .offset = MTDPART_OFS_NXTBLK,
177 .size = SZ_128K,
178 }, {
179 .name = "kernel",
180 .offset = MTDPART_OFS_NXTBLK,
181 .size = 4 * SZ_1M,
182 }, {
183 .name = "rootfs",
115 .offset = MTDPART_OFS_NXTBLK, 184 .offset = MTDPART_OFS_NXTBLK,
116 .size = 120 * SZ_1M, 185 .size = 120 * SZ_1M,
186 }, {
187 .name = "data",
188 .offset = MTDPART_OFS_NXTBLK,
189 .size = MTDPART_SIZ_FULL,
117 } 190 }
118}; 191};
119 192
@@ -132,7 +205,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
132 .partition_info = nand_partitions, 205 .partition_info = nand_partitions,
133}; 206};
134 207
135static struct sam9_smc_config __initdata ek_nand_smc_config = { 208static struct sam9_smc_config __initdata usb_a9260_nand_smc_config = {
136 .ncs_read_setup = 0, 209 .ncs_read_setup = 0,
137 .nrd_setup = 1, 210 .nrd_setup = 1,
138 .ncs_write_setup = 0, 211 .ncs_write_setup = 0,
@@ -150,10 +223,36 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = {
150 .tdf_cycles = 2, 223 .tdf_cycles = 2,
151}; 224};
152 225
226static struct sam9_smc_config __initdata usb_a9g20_nand_smc_config = {
227 .ncs_read_setup = 0,
228 .nrd_setup = 2,
229 .ncs_write_setup = 0,
230 .nwe_setup = 2,
231
232 .ncs_read_pulse = 4,
233 .nrd_pulse = 4,
234 .ncs_write_pulse = 4,
235 .nwe_pulse = 4,
236
237 .read_cycle = 7,
238 .write_cycle = 7,
239
240 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
241 .tdf_cycles = 3,
242};
243
153static void __init ek_add_device_nand(void) 244static void __init ek_add_device_nand(void)
154{ 245{
246 if (machine_is_usb_a9260() || machine_is_usb_a9g20()) {
247 ek_nand_data.rdy_pin = AT91_PIN_PC13;
248 ek_nand_data.enable_pin = AT91_PIN_PC14;
249 }
250
155 /* configure chip-select 3 (NAND) */ 251 /* configure chip-select 3 (NAND) */
156 sam9_smc_configure(3, &ek_nand_smc_config); 252 if (machine_is_usb_a9g20())
253 sam9_smc_configure(3, &usb_a9g20_nand_smc_config);
254 else
255 sam9_smc_configure(3, &usb_a9260_nand_smc_config);
157 256
158 at91_add_device_nand(&ek_nand_data); 257 at91_add_device_nand(&ek_nand_data);
159} 258}
@@ -210,6 +309,19 @@ static struct gpio_led ek_leds[] = {
210 } 309 }
211}; 310};
212 311
312static struct i2c_board_info __initdata ek_i2c_devices[] = {
313 {
314 I2C_BOARD_INFO("rv3029c2", 0x56),
315 },
316};
317
318static void __init ek_add_device_leds(void)
319{
320 if (machine_is_usb_a9260() || machine_is_usb_a9g20())
321 ek_leds[0].active_low = 0;
322
323 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
324}
213 325
214static void __init ek_board_init(void) 326static void __init ek_board_init(void)
215{ 327{
@@ -218,22 +330,29 @@ static void __init ek_board_init(void)
218 /* USB Host */ 330 /* USB Host */
219 at91_add_device_usbh(&ek_usbh_data); 331 at91_add_device_usbh(&ek_usbh_data);
220 /* USB Device */ 332 /* USB Device */
221 at91_add_device_udc(&ek_udc_data); 333 ek_add_device_udc();
222 /* SPI */ 334 /* SPI */
223 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); 335 ek_add_device_spi();
224 /* Ethernet */ 336 /* Ethernet */
225 at91_add_device_eth(&ek_macb_data); 337 ek_add_device_eth();
226 /* NAND */ 338 /* NAND */
227 ek_add_device_nand(); 339 ek_add_device_nand();
228 /* I2C */
229 at91_add_device_i2c(NULL, 0);
230 /* Push Buttons */ 340 /* Push Buttons */
231 ek_add_device_buttons(); 341 ek_add_device_buttons();
232 /* LEDs */ 342 /* LEDs */
233 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); 343 ek_add_device_leds();
234 /* shutdown controller, wakeup button (5 msec low) */ 344
235 at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW 345 if (machine_is_usb_a9g20()) {
346 /* I2C */
347 at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
348 } else {
349 /* I2C */
350 at91_add_device_i2c(NULL, 0);
351 /* shutdown controller, wakeup button (5 msec low) */
352 at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10)
353 | AT91_SHDW_WKMODE0_LOW
236 | AT91_SHDW_RTTWKEN); 354 | AT91_SHDW_RTTWKEN);
355 }
237} 356}
238 357
239MACHINE_START(USB_A9263, "CALAO USB_A9263") 358MACHINE_START(USB_A9263, "CALAO USB_A9263")
@@ -244,3 +363,21 @@ MACHINE_START(USB_A9263, "CALAO USB_A9263")
244 .init_irq = at91_init_irq_default, 363 .init_irq = at91_init_irq_default,
245 .init_machine = ek_board_init, 364 .init_machine = ek_board_init,
246MACHINE_END 365MACHINE_END
366
367MACHINE_START(USB_A9260, "CALAO USB_A9260")
368 /* Maintainer: calao-systems */
369 .timer = &at91sam926x_timer,
370 .map_io = at91_map_io,
371 .init_early = ek_init_early,
372 .init_irq = at91_init_irq_default,
373 .init_machine = ek_board_init,
374MACHINE_END
375
376MACHINE_START(USB_A9G20, "CALAO USB_A92G0")
377 /* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */
378 .timer = &at91sam926x_timer,
379 .map_io = at91_map_io,
380 .init_early = ek_init_early,
381 .init_irq = at91_init_irq_default,
382 .init_machine = ek_board_init,
383MACHINE_END
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index 31ac2d97f14c..85820ad801cc 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -64,7 +64,12 @@
64 64
65#elif defined(CONFIG_ARCH_AT91SAM9G20) 65#elif defined(CONFIG_ARCH_AT91SAM9G20)
66 66
67#if defined(CONFIG_MACH_USB_A9G20)
68#define AT91SAM9_MASTER_CLOCK 133000000
69#else
67#define AT91SAM9_MASTER_CLOCK 132096000 70#define AT91SAM9_MASTER_CLOCK 132096000
71#endif
72
68#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 73#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
69 74
70#elif defined(CONFIG_ARCH_AT91SAM9G45) 75#elif defined(CONFIG_ARCH_AT91SAM9G45)
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index 3a08b18f6433..97a249395b5a 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -182,6 +182,13 @@ config MACH_TS72XX
182 Say 'Y' here if you want your kernel to support the 182 Say 'Y' here if you want your kernel to support the
183 Technologic Systems TS-72xx board. 183 Technologic Systems TS-72xx board.
184 184
185config MACH_VISION_EP9307
186 bool "Support Vision Engraving Systems EP9307 SoM"
187 depends on EP93XX_SDCE0_PHYS_OFFSET
188 help
189 Say 'Y' here if you want your kernel to support the
190 Vision Engraving Systems EP9307 SoM.
191
185choice 192choice
186 prompt "Select a UART for early kernel messages" 193 prompt "Select a UART for early kernel messages"
187 194
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index 3cedcf2d39e5..574209d9e246 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_MACH_MICRO9) += micro9.o
15obj-$(CONFIG_MACH_SIM_ONE) += simone.o 15obj-$(CONFIG_MACH_SIM_ONE) += simone.o
16obj-$(CONFIG_MACH_SNAPPER_CL15) += snappercl15.o 16obj-$(CONFIG_MACH_SNAPPER_CL15) += snappercl15.o
17obj-$(CONFIG_MACH_TS72XX) += ts72xx.o 17obj-$(CONFIG_MACH_TS72XX) += ts72xx.o
18obj-$(CONFIG_MACH_VISION_EP9307)+= vision_ep9307.o
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
new file mode 100644
index 000000000000..d96e4dbec6a8
--- /dev/null
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -0,0 +1,364 @@
1/*
2 * arch/arm/mach-ep93xx/vision_ep9307.c
3 * Vision Engraving Systems EP9307 SoM support.
4 *
5 * Copyright (C) 2008-2011 Vision Engraving Systems
6 * H Hartley Sweeten <hsweeten@visionengravers.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or (at
11 * your option) any later version.
12 */
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/irq.h>
20#include <linux/gpio.h>
21#include <linux/fb.h>
22#include <linux/io.h>
23#include <linux/mtd/partitions.h>
24#include <linux/i2c.h>
25#include <linux/i2c-gpio.h>
26#include <linux/i2c/pca953x.h>
27#include <linux/spi/spi.h>
28#include <linux/spi/flash.h>
29#include <linux/spi/mmc_spi.h>
30#include <linux/mmc/host.h>
31
32#include <mach/hardware.h>
33#include <mach/fb.h>
34#include <mach/ep93xx_spi.h>
35
36#include <asm/mach-types.h>
37#include <asm/mach/map.h>
38#include <asm/mach/arch.h>
39
40/*************************************************************************
41 * Static I/O mappings for the FPGA
42 *************************************************************************/
43#define VISION_PHYS_BASE EP93XX_CS7_PHYS_BASE
44#define VISION_VIRT_BASE 0xfebff000
45
46static struct map_desc vision_io_desc[] __initdata = {
47 {
48 .virtual = VISION_VIRT_BASE,
49 .pfn = __phys_to_pfn(VISION_PHYS_BASE),
50 .length = SZ_4K,
51 .type = MT_DEVICE,
52 },
53};
54
55static void __init vision_map_io(void)
56{
57 ep93xx_map_io();
58
59 iotable_init(vision_io_desc, ARRAY_SIZE(vision_io_desc));
60}
61
62/*************************************************************************
63 * Ethernet
64 *************************************************************************/
65static struct ep93xx_eth_data vision_eth_data __initdata = {
66 .phy_id = 1,
67};
68
69/*************************************************************************
70 * Framebuffer
71 *************************************************************************/
72#define VISION_LCD_ENABLE EP93XX_GPIO_LINE_EGPIO1
73
74static int vision_lcd_setup(struct platform_device *pdev)
75{
76 int err;
77
78 err = gpio_request_one(VISION_LCD_ENABLE, GPIOF_INIT_HIGH,
79 dev_name(&pdev->dev));
80 if (err)
81 return err;
82
83 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_RAS |
84 EP93XX_SYSCON_DEVCFG_RASONP3 |
85 EP93XX_SYSCON_DEVCFG_EXVC);
86
87 return 0;
88}
89
90static void vision_lcd_teardown(struct platform_device *pdev)
91{
92 gpio_free(VISION_LCD_ENABLE);
93}
94
95static void vision_lcd_blank(int blank_mode, struct fb_info *info)
96{
97 if (blank_mode)
98 gpio_set_value(VISION_LCD_ENABLE, 0);
99 else
100 gpio_set_value(VISION_LCD_ENABLE, 1);
101}
102
103static struct ep93xxfb_mach_info ep93xxfb_info __initdata = {
104 .num_modes = EP93XXFB_USE_MODEDB,
105 .bpp = 16,
106 .flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING,
107 .setup = vision_lcd_setup,
108 .teardown = vision_lcd_teardown,
109 .blank = vision_lcd_blank,
110};
111
112
113/*************************************************************************
114 * GPIO Expanders
115 *************************************************************************/
116#define PCA9539_74_GPIO_BASE (EP93XX_GPIO_LINE_MAX + 1)
117#define PCA9539_75_GPIO_BASE (PCA9539_74_GPIO_BASE + 16)
118#define PCA9539_76_GPIO_BASE (PCA9539_75_GPIO_BASE + 16)
119#define PCA9539_77_GPIO_BASE (PCA9539_76_GPIO_BASE + 16)
120
121static struct pca953x_platform_data pca953x_74_gpio_data = {
122 .gpio_base = PCA9539_74_GPIO_BASE,
123 .irq_base = EP93XX_BOARD_IRQ(0),
124};
125
126static struct pca953x_platform_data pca953x_75_gpio_data = {
127 .gpio_base = PCA9539_75_GPIO_BASE,
128 .irq_base = -1,
129};
130
131static struct pca953x_platform_data pca953x_76_gpio_data = {
132 .gpio_base = PCA9539_76_GPIO_BASE,
133 .irq_base = -1,
134};
135
136static struct pca953x_platform_data pca953x_77_gpio_data = {
137 .gpio_base = PCA9539_77_GPIO_BASE,
138 .irq_base = -1,
139};
140
141/*************************************************************************
142 * I2C Bus
143 *************************************************************************/
144static struct i2c_gpio_platform_data vision_i2c_gpio_data __initdata = {
145 .sda_pin = EP93XX_GPIO_LINE_EEDAT,
146 .scl_pin = EP93XX_GPIO_LINE_EECLK,
147};
148
149static struct i2c_board_info vision_i2c_info[] __initdata = {
150 {
151 I2C_BOARD_INFO("isl1208", 0x6f),
152 .irq = IRQ_EP93XX_EXT1,
153 }, {
154 I2C_BOARD_INFO("pca9539", 0x74),
155 .platform_data = &pca953x_74_gpio_data,
156 .irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7)),
157 }, {
158 I2C_BOARD_INFO("pca9539", 0x75),
159 .platform_data = &pca953x_75_gpio_data,
160 }, {
161 I2C_BOARD_INFO("pca9539", 0x76),
162 .platform_data = &pca953x_76_gpio_data,
163 }, {
164 I2C_BOARD_INFO("pca9539", 0x77),
165 .platform_data = &pca953x_77_gpio_data,
166 },
167};
168
169/*************************************************************************
170 * SPI Flash
171 *************************************************************************/
172#define VISION_SPI_FLASH_CS EP93XX_GPIO_LINE_EGPIO7
173
174static struct mtd_partition vision_spi_flash_partitions[] = {
175 {
176 .name = "SPI bootstrap",
177 .offset = 0,
178 .size = SZ_4K,
179 }, {
180 .name = "Bootstrap config",
181 .offset = MTDPART_OFS_APPEND,
182 .size = SZ_4K,
183 }, {
184 .name = "System config",
185 .offset = MTDPART_OFS_APPEND,
186 .size = MTDPART_SIZ_FULL,
187 },
188};
189
190static struct flash_platform_data vision_spi_flash_data = {
191 .name = "SPI Flash",
192 .parts = vision_spi_flash_partitions,
193 .nr_parts = ARRAY_SIZE(vision_spi_flash_partitions),
194};
195
196static int vision_spi_flash_hw_setup(struct spi_device *spi)
197{
198 return gpio_request_one(VISION_SPI_FLASH_CS, GPIOF_INIT_HIGH,
199 spi->modalias);
200}
201
202static void vision_spi_flash_hw_cleanup(struct spi_device *spi)
203{
204 gpio_free(VISION_SPI_FLASH_CS);
205}
206
207static void vision_spi_flash_hw_cs_control(struct spi_device *spi, int value)
208{
209 gpio_set_value(VISION_SPI_FLASH_CS, value);
210}
211
212static struct ep93xx_spi_chip_ops vision_spi_flash_hw = {
213 .setup = vision_spi_flash_hw_setup,
214 .cleanup = vision_spi_flash_hw_cleanup,
215 .cs_control = vision_spi_flash_hw_cs_control,
216};
217
218/*************************************************************************
219 * SPI SD/MMC host
220 *************************************************************************/
221#define VISION_SPI_MMC_CS EP93XX_GPIO_LINE_G(2)
222#define VISION_SPI_MMC_WP EP93XX_GPIO_LINE_F(0)
223#define VISION_SPI_MMC_CD EP93XX_GPIO_LINE_EGPIO15
224
225static struct gpio vision_spi_mmc_gpios[] = {
226 { VISION_SPI_MMC_WP, GPIOF_DIR_IN, "mmc_spi:wp" },
227 { VISION_SPI_MMC_CD, GPIOF_DIR_IN, "mmc_spi:cd" },
228};
229
230static int vision_spi_mmc_init(struct device *pdev,
231 irqreturn_t (*func)(int, void *), void *pdata)
232{
233 int err;
234
235 err = gpio_request_array(vision_spi_mmc_gpios,
236 ARRAY_SIZE(vision_spi_mmc_gpios));
237 if (err)
238 return err;
239
240 err = gpio_set_debounce(VISION_SPI_MMC_CD, 1);
241 if (err)
242 goto exit_err;
243
244 err = request_irq(gpio_to_irq(VISION_SPI_MMC_CD), func,
245 IRQ_TYPE_EDGE_BOTH, "mmc_spi:cd", pdata);
246 if (err)
247 goto exit_err;
248
249 return 0;
250
251exit_err:
252 gpio_free_array(vision_spi_mmc_gpios, ARRAY_SIZE(vision_spi_mmc_gpios));
253 return err;
254
255}
256
257static void vision_spi_mmc_exit(struct device *pdev, void *pdata)
258{
259 free_irq(gpio_to_irq(VISION_SPI_MMC_CD), pdata);
260 gpio_free_array(vision_spi_mmc_gpios, ARRAY_SIZE(vision_spi_mmc_gpios));
261}
262
263static int vision_spi_mmc_get_ro(struct device *pdev)
264{
265 return !!gpio_get_value(VISION_SPI_MMC_WP);
266}
267
268static int vision_spi_mmc_get_cd(struct device *pdev)
269{
270 return !gpio_get_value(VISION_SPI_MMC_CD);
271}
272
273static struct mmc_spi_platform_data vision_spi_mmc_data = {
274 .init = vision_spi_mmc_init,
275 .exit = vision_spi_mmc_exit,
276 .get_ro = vision_spi_mmc_get_ro,
277 .get_cd = vision_spi_mmc_get_cd,
278 .detect_delay = 100,
279 .powerup_msecs = 100,
280 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
281};
282
283static int vision_spi_mmc_hw_setup(struct spi_device *spi)
284{
285 return gpio_request_one(VISION_SPI_MMC_CS, GPIOF_INIT_HIGH,
286 spi->modalias);
287}
288
289static void vision_spi_mmc_hw_cleanup(struct spi_device *spi)
290{
291 gpio_free(VISION_SPI_MMC_CS);
292}
293
294static void vision_spi_mmc_hw_cs_control(struct spi_device *spi, int value)
295{
296 gpio_set_value(VISION_SPI_MMC_CS, value);
297}
298
299static struct ep93xx_spi_chip_ops vision_spi_mmc_hw = {
300 .setup = vision_spi_mmc_hw_setup,
301 .cleanup = vision_spi_mmc_hw_cleanup,
302 .cs_control = vision_spi_mmc_hw_cs_control,
303};
304
305/*************************************************************************
306 * SPI Bus
307 *************************************************************************/
308static struct spi_board_info vision_spi_board_info[] __initdata = {
309 {
310 .modalias = "sst25l",
311 .platform_data = &vision_spi_flash_data,
312 .controller_data = &vision_spi_flash_hw,
313 .max_speed_hz = 20000000,
314 .bus_num = 0,
315 .chip_select = 0,
316 .mode = SPI_MODE_3,
317 }, {
318 .modalias = "mmc_spi",
319 .platform_data = &vision_spi_mmc_data,
320 .controller_data = &vision_spi_mmc_hw,
321 .max_speed_hz = 20000000,
322 .bus_num = 0,
323 .chip_select = 1,
324 .mode = SPI_MODE_3,
325 },
326};
327
328static struct ep93xx_spi_info vision_spi_master __initdata = {
329 .num_chipselect = ARRAY_SIZE(vision_spi_board_info),
330};
331
332/*************************************************************************
333 * Machine Initialization
334 *************************************************************************/
335static void __init vision_init_machine(void)
336{
337 ep93xx_init_devices();
338 ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_64M);
339 ep93xx_register_eth(&vision_eth_data, 1);
340 ep93xx_register_fb(&ep93xxfb_info);
341 ep93xx_register_pwm(1, 0);
342
343 /*
344 * Request the gpio expander's interrupt gpio line now to prevent
345 * the kernel from doing a WARN in gpiolib:gpio_ensure_requested().
346 */
347 if (gpio_request_one(EP93XX_GPIO_LINE_F(7), GPIOF_DIR_IN,
348 "pca9539:74"))
349 pr_warn("cannot request interrupt gpio for pca9539:74\n");
350
351 ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info,
352 ARRAY_SIZE(vision_i2c_info));
353 ep93xx_register_spi(&vision_spi_master, vision_spi_board_info,
354 ARRAY_SIZE(vision_spi_board_info));
355}
356
357MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
358 /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
359 .atag_offset = 0x100,
360 .map_io = vision_map_io,
361 .init_irq = ep93xx_init_irq,
362 .timer = &ep93xx_timer,
363 .init_machine = vision_init_machine,
364MACHINE_END
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 1760ee73fbf8..a65273598036 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -16,6 +16,16 @@ config CPU_EXYNOS4210
16 help 16 help
17 Enable EXYNOS4210 CPU support 17 Enable EXYNOS4210 CPU support
18 18
19config SOC_EXYNOS4212
20 bool
21 help
22 Enable EXYNOS4212 SoC support
23
24config SOC_EXYNOS4412
25 bool
26 help
27 Enable EXYNOS4412 SoC support
28
19config EXYNOS4_MCT 29config EXYNOS4_MCT
20 bool 30 bool
21 default y 31 default y
@@ -112,6 +122,8 @@ config EXYNOS4_SETUP_USB_PHY
112 122
113menu "EXYNOS4 Machines" 123menu "EXYNOS4 Machines"
114 124
125comment "EXYNOS4210 Boards"
126
115config MACH_SMDKC210 127config MACH_SMDKC210
116 bool "SMDKC210" 128 bool "SMDKC210"
117 select MACH_SMDKV310 129 select MACH_SMDKV310
@@ -204,6 +216,48 @@ config MACH_NURI
204 help 216 help
205 Machine support for Samsung Mobile NURI Board. 217 Machine support for Samsung Mobile NURI Board.
206 218
219config MACH_ORIGEN
220 bool "ORIGEN"
221 select CPU_EXYNOS4210
222 select S3C_DEV_RTC
223 select S3C_DEV_WDT
224 select S3C_DEV_HSMMC2
225 select EXYNOS4_SETUP_SDHCI
226 help
227 Machine support for ORIGEN based on Samsung EXYNOS4210
228
229comment "EXYNOS4212 Boards"
230
231config MACH_SMDK4212
232 bool "SMDK4212"
233 select SOC_EXYNOS4212
234 select S3C_DEV_HSMMC2
235 select S3C_DEV_HSMMC3
236 select S3C_DEV_I2C1
237 select S3C_DEV_I2C3
238 select S3C_DEV_I2C7
239 select S3C_DEV_RTC
240 select S3C_DEV_WDT
241 select SAMSUNG_DEV_BACKLIGHT
242 select SAMSUNG_DEV_KEYPAD
243 select SAMSUNG_DEV_PWM
244 select EXYNOS4_SETUP_I2C1
245 select EXYNOS4_SETUP_I2C3
246 select EXYNOS4_SETUP_I2C7
247 select EXYNOS4_SETUP_KEYPAD
248 select EXYNOS4_SETUP_SDHCI
249 help
250 Machine support for Samsung SMDK4212
251
252comment "EXYNOS4412 Boards"
253
254config MACH_SMDK4412
255 bool "SMDK4412"
256 select SOC_EXYNOS4412
257 select MACH_SMDK4212
258 help
259 Machine support for Samsung SMDK4412
260
207endmenu 261endmenu
208 262
209comment "Configuration for HSMMC bus width" 263comment "Configuration for HSMMC bus width"
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index e3e93ea41385..c9b2e1f97e44 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -12,8 +12,10 @@ obj- :=
12 12
13# Core support for EXYNOS4 system 13# Core support for EXYNOS4 system
14 14
15obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o 15obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o
16obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o 16obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o irq-eint.o dma.o pmu.o
17obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
18obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
17obj-$(CONFIG_PM) += pm.o sleep.o 19obj-$(CONFIG_PM) += pm.o sleep.o
18obj-$(CONFIG_CPU_IDLE) += cpuidle.o 20obj-$(CONFIG_CPU_IDLE) += cpuidle.o
19 21
@@ -30,6 +32,10 @@ obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
30obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o 32obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o
31obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o 33obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
32obj-$(CONFIG_MACH_NURI) += mach-nuri.o 34obj-$(CONFIG_MACH_NURI) += mach-nuri.o
35obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o
36
37obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
38obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
33 39
34# device support 40# device support
35 41
diff --git a/arch/arm/mach-exynos4/clock-exynos4210.c b/arch/arm/mach-exynos4/clock-exynos4210.c
new file mode 100644
index 000000000000..b9d5ef670eb4
--- /dev/null
+++ b/arch/arm/mach-exynos4/clock-exynos4210.c
@@ -0,0 +1,139 @@
1/*
2 * linux/arch/arm/mach-exynos4/clock-exynos4210.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * EXYNOS4210 - Clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/syscore_ops.h>
19
20#include <plat/cpu-freq.h>
21#include <plat/clock.h>
22#include <plat/cpu.h>
23#include <plat/pll.h>
24#include <plat/s5p-clock.h>
25#include <plat/clock-clksrc.h>
26#include <plat/exynos4.h>
27#include <plat/pm.h>
28
29#include <mach/hardware.h>
30#include <mach/map.h>
31#include <mach/regs-clock.h>
32#include <mach/exynos4-clock.h>
33
34static struct sleep_save exynos4210_clock_save[] = {
35 SAVE_ITEM(S5P_CLKSRC_IMAGE),
36 SAVE_ITEM(S5P_CLKSRC_LCD1),
37 SAVE_ITEM(S5P_CLKDIV_IMAGE),
38 SAVE_ITEM(S5P_CLKDIV_LCD1),
39 SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
40 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
41 SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
42 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
43};
44
45static struct clksrc_clk *sysclks[] = {
46 /* nothing here yet */
47};
48
49static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
50{
51 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
52}
53
54static struct clksrc_clk clksrcs[] = {
55 {
56 .clk = {
57 .name = "sclk_sata",
58 .id = -1,
59 .enable = exynos4_clksrc_mask_fsys_ctrl,
60 .ctrlbit = (1 << 24),
61 },
62 .sources = &clkset_mout_corebus,
63 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
64 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
65 }, {
66 .clk = {
67 .name = "sclk_fimd",
68 .devname = "exynos4-fb.1",
69 .enable = exynos4_clksrc_mask_lcd1_ctrl,
70 .ctrlbit = (1 << 0),
71 },
72 .sources = &clkset_group,
73 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
74 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
75 },
76};
77
78static struct clk init_clocks_off[] = {
79 {
80 .name = "sataphy",
81 .id = -1,
82 .parent = &clk_aclk_133.clk,
83 .enable = exynos4_clk_ip_fsys_ctrl,
84 .ctrlbit = (1 << 3),
85 }, {
86 .name = "sata",
87 .id = -1,
88 .parent = &clk_aclk_133.clk,
89 .enable = exynos4_clk_ip_fsys_ctrl,
90 .ctrlbit = (1 << 10),
91 }, {
92 .name = "fimd",
93 .devname = "exynos4-fb.1",
94 .enable = exynos4_clk_ip_lcd1_ctrl,
95 .ctrlbit = (1 << 0),
96 },
97};
98
99#ifdef CONFIG_PM_SLEEP
100static int exynos4210_clock_suspend(void)
101{
102 s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
103
104 return 0;
105}
106
107static void exynos4210_clock_resume(void)
108{
109 s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
110}
111
112#else
113#define exynos4210_clock_suspend NULL
114#define exynos4210_clock_resume NULL
115#endif
116
117struct syscore_ops exynos4210_clock_syscore_ops = {
118 .suspend = exynos4210_clock_suspend,
119 .resume = exynos4210_clock_resume,
120};
121
122void __init exynos4210_register_clocks(void)
123{
124 int ptr;
125
126 clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
127 clk_mout_mpll.reg_src.shift = 8;
128 clk_mout_mpll.reg_src.size = 1;
129
130 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
131 s3c_register_clksrc(sysclks[ptr], 1);
132
133 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
134
135 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
136 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
137
138 register_syscore_ops(&exynos4210_clock_syscore_ops);
139}
diff --git a/arch/arm/mach-exynos4/clock-exynos4212.c b/arch/arm/mach-exynos4/clock-exynos4212.c
new file mode 100644
index 000000000000..77d5decb34fd
--- /dev/null
+++ b/arch/arm/mach-exynos4/clock-exynos4212.c
@@ -0,0 +1,118 @@
1/*
2 * linux/arch/arm/mach-exynos4/clock-exynos4212.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * EXYNOS4212 - Clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/syscore_ops.h>
19
20#include <plat/cpu-freq.h>
21#include <plat/clock.h>
22#include <plat/cpu.h>
23#include <plat/pll.h>
24#include <plat/s5p-clock.h>
25#include <plat/clock-clksrc.h>
26#include <plat/exynos4.h>
27#include <plat/pm.h>
28
29#include <mach/hardware.h>
30#include <mach/map.h>
31#include <mach/regs-clock.h>
32#include <mach/exynos4-clock.h>
33
34static struct sleep_save exynos4212_clock_save[] = {
35 SAVE_ITEM(S5P_CLKSRC_IMAGE),
36 SAVE_ITEM(S5P_CLKDIV_IMAGE),
37 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
38 SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
39};
40
41static struct clk *clk_src_mpll_user_list[] = {
42 [0] = &clk_fin_mpll,
43 [1] = &clk_mout_mpll.clk,
44};
45
46static struct clksrc_sources clk_src_mpll_user = {
47 .sources = clk_src_mpll_user_list,
48 .nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
49};
50
51static struct clksrc_clk clk_mout_mpll_user = {
52 .clk = {
53 .name = "mout_mpll_user",
54 },
55 .sources = &clk_src_mpll_user,
56 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
57};
58
59static struct clksrc_clk *sysclks[] = {
60 &clk_mout_mpll_user,
61};
62
63static struct clksrc_clk clksrcs[] = {
64 /* nothing here yet */
65};
66
67static struct clk init_clocks_off[] = {
68 /* nothing here yet */
69};
70
71#ifdef CONFIG_PM_SLEEP
72static int exynos4212_clock_suspend(void)
73{
74 s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
75
76 return 0;
77}
78
79static void exynos4212_clock_resume(void)
80{
81 s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
82}
83
84#else
85#define exynos4212_clock_suspend NULL
86#define exynos4212_clock_resume NULL
87#endif
88
89struct syscore_ops exynos4212_clock_syscore_ops = {
90 .suspend = exynos4212_clock_suspend,
91 .resume = exynos4212_clock_resume,
92};
93
94void __init exynos4212_register_clocks(void)
95{
96 int ptr;
97
98 /* usbphy1 is removed */
99 clkset_group_list[4] = NULL;
100
101 /* mout_mpll_user is used */
102 clkset_group_list[6] = &clk_mout_mpll_user.clk;
103 clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
104
105 clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
106 clk_mout_mpll.reg_src.shift = 12;
107 clk_mout_mpll.reg_src.size = 1;
108
109 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
110 s3c_register_clksrc(sysclks[ptr], 1);
111
112 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
113
114 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
115 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
116
117 register_syscore_ops(&exynos4212_clock_syscore_ops);
118}
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 86964d2e9e1b..0d59be3fa1fe 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -13,6 +13,7 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/syscore_ops.h>
16 17
17#include <plat/cpu-freq.h> 18#include <plat/cpu-freq.h>
18#include <plat/clock.h> 19#include <plat/clock.h>
@@ -20,26 +21,93 @@
20#include <plat/pll.h> 21#include <plat/pll.h>
21#include <plat/s5p-clock.h> 22#include <plat/s5p-clock.h>
22#include <plat/clock-clksrc.h> 23#include <plat/clock-clksrc.h>
24#include <plat/exynos4.h>
25#include <plat/pm.h>
23 26
24#include <mach/map.h> 27#include <mach/map.h>
25#include <mach/regs-clock.h> 28#include <mach/regs-clock.h>
26#include <mach/sysmmu.h> 29#include <mach/sysmmu.h>
27 30#include <mach/exynos4-clock.h>
28static struct clk clk_sclk_hdmi27m = { 31
32static struct sleep_save exynos4_clock_save[] = {
33 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
34 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
35 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
36 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
37 SAVE_ITEM(S5P_CLKSRC_TOP0),
38 SAVE_ITEM(S5P_CLKSRC_TOP1),
39 SAVE_ITEM(S5P_CLKSRC_CAM),
40 SAVE_ITEM(S5P_CLKSRC_TV),
41 SAVE_ITEM(S5P_CLKSRC_MFC),
42 SAVE_ITEM(S5P_CLKSRC_G3D),
43 SAVE_ITEM(S5P_CLKSRC_LCD0),
44 SAVE_ITEM(S5P_CLKSRC_MAUDIO),
45 SAVE_ITEM(S5P_CLKSRC_FSYS),
46 SAVE_ITEM(S5P_CLKSRC_PERIL0),
47 SAVE_ITEM(S5P_CLKSRC_PERIL1),
48 SAVE_ITEM(S5P_CLKDIV_CAM),
49 SAVE_ITEM(S5P_CLKDIV_TV),
50 SAVE_ITEM(S5P_CLKDIV_MFC),
51 SAVE_ITEM(S5P_CLKDIV_G3D),
52 SAVE_ITEM(S5P_CLKDIV_LCD0),
53 SAVE_ITEM(S5P_CLKDIV_MAUDIO),
54 SAVE_ITEM(S5P_CLKDIV_FSYS0),
55 SAVE_ITEM(S5P_CLKDIV_FSYS1),
56 SAVE_ITEM(S5P_CLKDIV_FSYS2),
57 SAVE_ITEM(S5P_CLKDIV_FSYS3),
58 SAVE_ITEM(S5P_CLKDIV_PERIL0),
59 SAVE_ITEM(S5P_CLKDIV_PERIL1),
60 SAVE_ITEM(S5P_CLKDIV_PERIL2),
61 SAVE_ITEM(S5P_CLKDIV_PERIL3),
62 SAVE_ITEM(S5P_CLKDIV_PERIL4),
63 SAVE_ITEM(S5P_CLKDIV_PERIL5),
64 SAVE_ITEM(S5P_CLKDIV_TOP),
65 SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
66 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
67 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
68 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
69 SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
70 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
71 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
72 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
73 SAVE_ITEM(S5P_CLKDIV2_RATIO),
74 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
75 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
76 SAVE_ITEM(S5P_CLKGATE_IP_TV),
77 SAVE_ITEM(S5P_CLKGATE_IP_MFC),
78 SAVE_ITEM(S5P_CLKGATE_IP_G3D),
79 SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
80 SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
81 SAVE_ITEM(S5P_CLKGATE_IP_GPS),
82 SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
83 SAVE_ITEM(S5P_CLKGATE_BLOCK),
84 SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
85 SAVE_ITEM(S5P_CLKSRC_DMC),
86 SAVE_ITEM(S5P_CLKDIV_DMC0),
87 SAVE_ITEM(S5P_CLKDIV_DMC1),
88 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
89 SAVE_ITEM(S5P_CLKSRC_CPU),
90 SAVE_ITEM(S5P_CLKDIV_CPU),
91 SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
92 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
93 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
94};
95
96struct clk clk_sclk_hdmi27m = {
29 .name = "sclk_hdmi27m", 97 .name = "sclk_hdmi27m",
30 .rate = 27000000, 98 .rate = 27000000,
31}; 99};
32 100
33static struct clk clk_sclk_hdmiphy = { 101struct clk clk_sclk_hdmiphy = {
34 .name = "sclk_hdmiphy", 102 .name = "sclk_hdmiphy",
35}; 103};
36 104
37static struct clk clk_sclk_usbphy0 = { 105struct clk clk_sclk_usbphy0 = {
38 .name = "sclk_usbphy0", 106 .name = "sclk_usbphy0",
39 .rate = 27000000, 107 .rate = 27000000,
40}; 108};
41 109
42static struct clk clk_sclk_usbphy1 = { 110struct clk clk_sclk_usbphy1 = {
43 .name = "sclk_usbphy1", 111 .name = "sclk_usbphy1",
44}; 112};
45 113
@@ -58,12 +126,7 @@ static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
58 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable); 126 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
59} 127}
60 128
61static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) 129int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
62{
63 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
64}
65
66static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
67{ 130{
68 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable); 131 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
69} 132}
@@ -103,12 +166,12 @@ static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
103 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable); 166 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
104} 167}
105 168
106static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable) 169int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
107{ 170{
108 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable); 171 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
109} 172}
110 173
111static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable) 174int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
112{ 175{
113 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable); 176 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
114} 177}
@@ -133,7 +196,7 @@ static struct clksrc_clk clk_mout_apll = {
133 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, 196 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
134}; 197};
135 198
136static struct clksrc_clk clk_sclk_apll = { 199struct clksrc_clk clk_sclk_apll = {
137 .clk = { 200 .clk = {
138 .name = "sclk_apll", 201 .name = "sclk_apll",
139 .parent = &clk_mout_apll.clk, 202 .parent = &clk_mout_apll.clk,
@@ -141,7 +204,7 @@ static struct clksrc_clk clk_sclk_apll = {
141 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, 204 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
142}; 205};
143 206
144static struct clksrc_clk clk_mout_epll = { 207struct clksrc_clk clk_mout_epll = {
145 .clk = { 208 .clk = {
146 .name = "mout_epll", 209 .name = "mout_epll",
147 }, 210 },
@@ -149,12 +212,13 @@ static struct clksrc_clk clk_mout_epll = {
149 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, 212 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
150}; 213};
151 214
152static struct clksrc_clk clk_mout_mpll = { 215struct clksrc_clk clk_mout_mpll = {
153 .clk = { 216 .clk = {
154 .name = "mout_mpll", 217 .name = "mout_mpll",
155 }, 218 },
156 .sources = &clk_src_mpll, 219 .sources = &clk_src_mpll,
157 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, 220
221 /* reg_src will be added in each SoCs' clock */
158}; 222};
159 223
160static struct clk *clkset_moutcore_list[] = { 224static struct clk *clkset_moutcore_list[] = {
@@ -224,12 +288,12 @@ static struct clksrc_clk clk_periphclk = {
224 288
225/* Core list of CMU_CORE side */ 289/* Core list of CMU_CORE side */
226 290
227static struct clk *clkset_corebus_list[] = { 291struct clk *clkset_corebus_list[] = {
228 [0] = &clk_mout_mpll.clk, 292 [0] = &clk_mout_mpll.clk,
229 [1] = &clk_sclk_apll.clk, 293 [1] = &clk_sclk_apll.clk,
230}; 294};
231 295
232static struct clksrc_sources clkset_mout_corebus = { 296struct clksrc_sources clkset_mout_corebus = {
233 .sources = clkset_corebus_list, 297 .sources = clkset_corebus_list,
234 .nr_sources = ARRAY_SIZE(clkset_corebus_list), 298 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
235}; 299};
@@ -284,12 +348,12 @@ static struct clksrc_clk clk_pclk_acp = {
284 348
285/* Core list of CMU_TOP side */ 349/* Core list of CMU_TOP side */
286 350
287static struct clk *clkset_aclk_top_list[] = { 351struct clk *clkset_aclk_top_list[] = {
288 [0] = &clk_mout_mpll.clk, 352 [0] = &clk_mout_mpll.clk,
289 [1] = &clk_sclk_apll.clk, 353 [1] = &clk_sclk_apll.clk,
290}; 354};
291 355
292static struct clksrc_sources clkset_aclk = { 356struct clksrc_sources clkset_aclk = {
293 .sources = clkset_aclk_top_list, 357 .sources = clkset_aclk_top_list,
294 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), 358 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
295}; 359};
@@ -321,7 +385,7 @@ static struct clksrc_clk clk_aclk_160 = {
321 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 }, 385 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
322}; 386};
323 387
324static struct clksrc_clk clk_aclk_133 = { 388struct clksrc_clk clk_aclk_133 = {
325 .clk = { 389 .clk = {
326 .name = "aclk_133", 390 .name = "aclk_133",
327 }, 391 },
@@ -360,7 +424,7 @@ static struct clksrc_sources clkset_sclk_vpll = {
360 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), 424 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
361}; 425};
362 426
363static struct clksrc_clk clk_sclk_vpll = { 427struct clksrc_clk clk_sclk_vpll = {
364 .clk = { 428 .clk = {
365 .name = "sclk_vpll", 429 .name = "sclk_vpll",
366 }, 430 },
@@ -410,16 +474,6 @@ static struct clk init_clocks_off[] = {
410 .enable = exynos4_clk_ip_lcd0_ctrl, 474 .enable = exynos4_clk_ip_lcd0_ctrl,
411 .ctrlbit = (1 << 0), 475 .ctrlbit = (1 << 0),
412 }, { 476 }, {
413 .name = "fimd",
414 .devname = "exynos4-fb.1",
415 .enable = exynos4_clk_ip_lcd1_ctrl,
416 .ctrlbit = (1 << 0),
417 }, {
418 .name = "sataphy",
419 .parent = &clk_aclk_133.clk,
420 .enable = exynos4_clk_ip_fsys_ctrl,
421 .ctrlbit = (1 << 3),
422 }, {
423 .name = "hsmmc", 477 .name = "hsmmc",
424 .devname = "s3c-sdhci.0", 478 .devname = "s3c-sdhci.0",
425 .parent = &clk_aclk_133.clk, 479 .parent = &clk_aclk_133.clk,
@@ -449,11 +503,6 @@ static struct clk init_clocks_off[] = {
449 .enable = exynos4_clk_ip_fsys_ctrl, 503 .enable = exynos4_clk_ip_fsys_ctrl,
450 .ctrlbit = (1 << 9), 504 .ctrlbit = (1 << 9),
451 }, { 505 }, {
452 .name = "sata",
453 .parent = &clk_aclk_133.clk,
454 .enable = exynos4_clk_ip_fsys_ctrl,
455 .ctrlbit = (1 << 10),
456 }, {
457 .name = "pdma", 506 .name = "pdma",
458 .devname = "s3c-pl330.0", 507 .devname = "s3c-pl330.0",
459 .enable = exynos4_clk_ip_fsys_ctrl, 508 .enable = exynos4_clk_ip_fsys_ctrl,
@@ -673,7 +722,7 @@ static struct clk init_clocks[] = {
673 } 722 }
674}; 723};
675 724
676static struct clk *clkset_group_list[] = { 725struct clk *clkset_group_list[] = {
677 [0] = &clk_ext_xtal_mux, 726 [0] = &clk_ext_xtal_mux,
678 [1] = &clk_xusbxti, 727 [1] = &clk_xusbxti,
679 [2] = &clk_sclk_hdmi27m, 728 [2] = &clk_sclk_hdmi27m,
@@ -685,7 +734,7 @@ static struct clk *clkset_group_list[] = {
685 [8] = &clk_sclk_vpll.clk, 734 [8] = &clk_sclk_vpll.clk,
686}; 735};
687 736
688static struct clksrc_sources clkset_group = { 737struct clksrc_sources clkset_group = {
689 .sources = clkset_group_list, 738 .sources = clkset_group_list,
690 .nr_sources = ARRAY_SIZE(clkset_group_list), 739 .nr_sources = ARRAY_SIZE(clkset_group_list),
691}; 740};
@@ -967,25 +1016,6 @@ static struct clksrc_clk clksrcs[] = {
967 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 }, 1016 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
968 }, { 1017 }, {
969 .clk = { 1018 .clk = {
970 .name = "sclk_fimd",
971 .devname = "exynos4-fb.1",
972 .enable = exynos4_clksrc_mask_lcd1_ctrl,
973 .ctrlbit = (1 << 0),
974 },
975 .sources = &clkset_group,
976 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
977 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
978 }, {
979 .clk = {
980 .name = "sclk_sata",
981 .enable = exynos4_clksrc_mask_fsys_ctrl,
982 .ctrlbit = (1 << 24),
983 },
984 .sources = &clkset_mout_corebus,
985 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
986 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
987 }, {
988 .clk = {
989 .name = "sclk_spi", 1019 .name = "sclk_spi",
990 .devname = "s3c64xx-spi.0", 1020 .devname = "s3c64xx-spi.0",
991 .enable = exynos4_clksrc_mask_peril1_ctrl, 1021 .enable = exynos4_clksrc_mask_peril1_ctrl,
@@ -1114,7 +1144,13 @@ static int xtal_rate;
1114 1144
1115static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) 1145static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1116{ 1146{
1117 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508); 1147 if (soc_is_exynos4210())
1148 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
1149 pll_4508);
1150 else if (soc_is_exynos4212() || soc_is_exynos4412())
1151 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
1152 else
1153 return 0;
1118} 1154}
1119 1155
1120static struct clk_ops exynos4_fout_apll_ops = { 1156static struct clk_ops exynos4_fout_apll_ops = {
@@ -1124,10 +1160,10 @@ static struct clk_ops exynos4_fout_apll_ops = {
1124void __init_or_cpufreq exynos4_setup_clocks(void) 1160void __init_or_cpufreq exynos4_setup_clocks(void)
1125{ 1161{
1126 struct clk *xtal_clk; 1162 struct clk *xtal_clk;
1127 unsigned long apll; 1163 unsigned long apll = 0;
1128 unsigned long mpll; 1164 unsigned long mpll = 0;
1129 unsigned long epll; 1165 unsigned long epll = 0;
1130 unsigned long vpll; 1166 unsigned long vpll = 0;
1131 unsigned long vpllsrc; 1167 unsigned long vpllsrc;
1132 unsigned long xtal; 1168 unsigned long xtal;
1133 unsigned long armclk; 1169 unsigned long armclk;
@@ -1151,14 +1187,29 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
1151 1187
1152 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); 1188 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1153 1189
1154 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508); 1190 if (soc_is_exynos4210()) {
1155 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508); 1191 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
1156 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0), 1192 pll_4508);
1157 __raw_readl(S5P_EPLL_CON1), pll_4600); 1193 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
1158 1194 pll_4508);
1159 vpllsrc = clk_get_rate(&clk_vpllsrc.clk); 1195 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1160 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), 1196 __raw_readl(S5P_EPLL_CON1), pll_4600);
1161 __raw_readl(S5P_VPLL_CON1), pll_4650c); 1197
1198 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1199 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1200 __raw_readl(S5P_VPLL_CON1), pll_4650c);
1201 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1202 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
1203 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
1204 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
1205 __raw_readl(S5P_EPLL_CON1));
1206
1207 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1208 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1209 __raw_readl(S5P_VPLL_CON1));
1210 } else {
1211 /* nothing */
1212 }
1162 1213
1163 clk_fout_apll.ops = &exynos4_fout_apll_ops; 1214 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1164 clk_fout_mpll.rate = mpll; 1215 clk_fout_mpll.rate = mpll;
@@ -1193,6 +1244,28 @@ static struct clk *clks[] __initdata = {
1193 /* Nothing here yet */ 1244 /* Nothing here yet */
1194}; 1245};
1195 1246
1247#ifdef CONFIG_PM_SLEEP
1248static int exynos4_clock_suspend(void)
1249{
1250 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1251 return 0;
1252}
1253
1254static void exynos4_clock_resume(void)
1255{
1256 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1257}
1258
1259#else
1260#define exynos4_clock_suspend NULL
1261#define exynos4_clock_resume NULL
1262#endif
1263
1264struct syscore_ops exynos4_clock_syscore_ops = {
1265 .suspend = exynos4_clock_suspend,
1266 .resume = exynos4_clock_resume,
1267};
1268
1196void __init exynos4_register_clocks(void) 1269void __init exynos4_register_clocks(void)
1197{ 1270{
1198 int ptr; 1271 int ptr;
@@ -1208,5 +1281,6 @@ void __init exynos4_register_clocks(void)
1208 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1281 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1209 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1282 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1210 1283
1284 register_syscore_ops(&exynos4_clock_syscore_ops);
1211 s3c_pwmclk_init(); 1285 s3c_pwmclk_init();
1212} 1286}
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 746d6fc6d397..a348434f17b5 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -32,6 +32,8 @@
32#include <mach/regs-irq.h> 32#include <mach/regs-irq.h>
33#include <mach/regs-pmu.h> 33#include <mach/regs-pmu.h>
34 34
35unsigned int gic_bank_offset __read_mostly;
36
35extern int combiner_init(unsigned int combiner_nr, void __iomem *base, 37extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
36 unsigned int irq_start); 38 unsigned int irq_start);
37extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); 39extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
@@ -44,11 +46,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
44 .length = SZ_4K, 46 .length = SZ_4K,
45 .type = MT_DEVICE, 47 .type = MT_DEVICE,
46 }, { 48 }, {
47 .virtual = (unsigned long)S5P_VA_SYSRAM,
48 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
49 .length = SZ_4K,
50 .type = MT_DEVICE,
51 }, {
52 .virtual = (unsigned long)S5P_VA_CMU, 49 .virtual = (unsigned long)S5P_VA_CMU,
53 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), 50 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
54 .length = SZ_128K, 51 .length = SZ_128K,
@@ -121,6 +118,24 @@ static struct map_desc exynos4_iodesc[] __initdata = {
121 }, 118 },
122}; 119};
123 120
121static struct map_desc exynos4_iodesc0[] __initdata = {
122 {
123 .virtual = (unsigned long)S5P_VA_SYSRAM,
124 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
125 .length = SZ_4K,
126 .type = MT_DEVICE,
127 },
128};
129
130static struct map_desc exynos4_iodesc1[] __initdata = {
131 {
132 .virtual = (unsigned long)S5P_VA_SYSRAM,
133 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
134 .length = SZ_4K,
135 .type = MT_DEVICE,
136 },
137};
138
124static void exynos4_idle(void) 139static void exynos4_idle(void)
125{ 140{
126 if (!need_resched()) 141 if (!need_resched())
@@ -143,6 +158,11 @@ void __init exynos4_map_io(void)
143{ 158{
144 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); 159 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
145 160
161 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
162 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
163 else
164 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
165
146 /* initialize device information early */ 166 /* initialize device information early */
147 exynos4_default_sdhci0(); 167 exynos4_default_sdhci0();
148 exynos4_default_sdhci1(); 168 exynos4_default_sdhci1();
@@ -170,24 +190,37 @@ void __init exynos4_init_clocks(int xtal)
170 190
171 s3c24xx_register_baseclocks(xtal); 191 s3c24xx_register_baseclocks(xtal);
172 s5p_register_clocks(xtal); 192 s5p_register_clocks(xtal);
193
194 if (soc_is_exynos4210())
195 exynos4210_register_clocks();
196 else if (soc_is_exynos4212() || soc_is_exynos4412())
197 exynos4212_register_clocks();
198
173 exynos4_register_clocks(); 199 exynos4_register_clocks();
174 exynos4_setup_clocks(); 200 exynos4_setup_clocks();
175} 201}
176 202
177static void exynos4_gic_irq_eoi(struct irq_data *d) 203static void exynos4_gic_irq_fix_base(struct irq_data *d)
178{ 204{
179 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 205 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
180 206
181 gic_data->cpu_base = S5P_VA_GIC_CPU + 207 gic_data->cpu_base = S5P_VA_GIC_CPU +
182 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); 208 (gic_bank_offset * smp_processor_id());
209
210 gic_data->dist_base = S5P_VA_GIC_DIST +
211 (gic_bank_offset * smp_processor_id());
183} 212}
184 213
185void __init exynos4_init_irq(void) 214void __init exynos4_init_irq(void)
186{ 215{
187 int irq; 216 int irq;
188 217
189 gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); 218 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
190 gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi; 219
220 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
221 gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
222 gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
223 gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
191 224
192 for (irq = 0; irq < MAX_COMBINER_NR; irq++) { 225 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
193 226
@@ -223,7 +256,11 @@ static int __init exynos4_l2x0_cache_init(void)
223{ 256{
224 /* TAG, Data Latency Control: 2cycle */ 257 /* TAG, Data Latency Control: 2cycle */
225 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); 258 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
226 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); 259
260 if (soc_is_exynos4210())
261 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
262 else if (soc_is_exynos4212() || soc_is_exynos4412())
263 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
227 264
228 /* L2X0 Prefetch Control */ 265 /* L2X0 Prefetch Control */
229 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); 266 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index 006a4f4c65c6..f5e9fd8e37b4 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -17,12 +17,25 @@
17 .endm 17 .endm
18 18
19 .macro get_irqnr_preamble, base, tmp 19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =gic_cpu_base_addr 20 mov \tmp, #0
21
22 mrc p15, 0, \base, c0, c0, 5
23 and \base, \base, #3
24 cmp \base, #0
25 beq 1f
26
27 ldr \tmp, =gic_bank_offset
28 ldr \tmp, [\tmp]
29 cmp \base, #1
30 beq 1f
31
32 cmp \base, #2
33 addeq \tmp, \tmp, \tmp
34 addne \tmp, \tmp, \tmp, LSL #1
35
361: ldr \base, =gic_cpu_base_addr
21 ldr \base, [\base] 37 ldr \base, [\base]
22 mrc p15, 0, \tmp, c0, c0, 5 38 add \base, \base, \tmp
23 and \tmp, \tmp, #3
24 cmp \tmp, #1
25 addeq \base, \base, #EXYNOS4_GIC_BANK_OFFSET
26 .endm 39 .endm
27 40
28 .macro arch_ret_to_user, tmp1, tmp2 41 .macro arch_ret_to_user, tmp1, tmp2
diff --git a/arch/arm/mach-exynos4/include/mach/exynos4-clock.h b/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
new file mode 100644
index 000000000000..a07fcbf55251
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
@@ -0,0 +1,43 @@
1/*
2 * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Header file for exynos4 clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_CLOCK_H
15#define __ASM_ARCH_CLOCK_H __FILE__
16
17#include <linux/clk.h>
18
19extern struct clk clk_sclk_hdmi27m;
20extern struct clk clk_sclk_usbphy0;
21extern struct clk clk_sclk_usbphy1;
22extern struct clk clk_sclk_hdmiphy;
23
24extern struct clksrc_clk clk_sclk_apll;
25extern struct clksrc_clk clk_mout_mpll;
26extern struct clksrc_clk clk_aclk_133;
27extern struct clksrc_clk clk_mout_epll;
28extern struct clksrc_clk clk_sclk_vpll;
29
30extern struct clk *clkset_corebus_list[];
31extern struct clksrc_sources clkset_mout_corebus;
32
33extern struct clk *clkset_aclk_top_list[];
34extern struct clksrc_sources clkset_aclk;
35
36extern struct clk *clkset_group_list[];
37extern struct clksrc_sources clkset_group;
38
39extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
40extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
41extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
42
43#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index f8952f8f3757..2d3f6bcd9bc0 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -19,6 +19,8 @@
19 19
20#define IRQ_PPI(x) S5P_IRQ(x+16) 20#define IRQ_PPI(x) S5P_IRQ(x+16)
21 21
22#define IRQ_MCT_LOCALTIMER IRQ_PPI(12)
23
22/* SPI: Shared Peripheral Interrupt */ 24/* SPI: Shared Peripheral Interrupt */
23 25
24#define IRQ_SPI(x) S5P_IRQ(x+32) 26#define IRQ_SPI(x) S5P_IRQ(x+32)
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index d32296dc65e2..9f97eb8499ee 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -23,7 +23,8 @@
23 23
24#include <plat/map-s5p.h> 24#include <plat/map-s5p.h>
25 25
26#define EXYNOS4_PA_SYSRAM 0x02020000 26#define EXYNOS4_PA_SYSRAM0 0x02025000
27#define EXYNOS4_PA_SYSRAM1 0x02020000
27 28
28#define EXYNOS4_PA_FIMC0 0x11800000 29#define EXYNOS4_PA_FIMC0 0x11800000
29#define EXYNOS4_PA_FIMC1 0x11810000 30#define EXYNOS4_PA_FIMC1 0x11810000
@@ -61,7 +62,6 @@
61 62
62#define EXYNOS4_PA_GIC_CPU 0x10480000 63#define EXYNOS4_PA_GIC_CPU 0x10480000
63#define EXYNOS4_PA_GIC_DIST 0x10490000 64#define EXYNOS4_PA_GIC_DIST 0x10490000
64#define EXYNOS4_GIC_BANK_OFFSET 0x8000
65 65
66#define EXYNOS4_PA_COREPERI 0x10500000 66#define EXYNOS4_PA_COREPERI 0x10500000
67#define EXYNOS4_PA_TWD 0x10500600 67#define EXYNOS4_PA_TWD 0x10500600
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index d493fdb422ff..6c37ebe94829 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -13,6 +13,7 @@
13#ifndef __ASM_ARCH_REGS_CLOCK_H 13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__ 14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15 15
16#include <plat/cpu.h>
16#include <mach/map.h> 17#include <mach/map.h>
17 18
18#define S5P_CLKREG(x) (S5P_VA_CMU + (x)) 19#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
@@ -41,12 +42,20 @@
41#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C) 42#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C)
42#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) 43#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
43#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) 44#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
44#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
45#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C) 45#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C)
46#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240) 46#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
47#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) 47#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
48#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254) 48#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
49 49
50#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
51#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
52#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
53#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
54#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
55#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
56#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
57#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
58
50#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) 59#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
51#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520) 60#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
52#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524) 61#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524)
@@ -54,7 +63,6 @@
54#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C) 63#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C)
55#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530) 64#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
56#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534) 65#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
57#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
58#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C) 66#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C)
59#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) 67#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
60#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544) 68#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
@@ -68,16 +76,6 @@
68#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) 76#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
69#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580) 77#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580)
70 78
71#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
72#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
73#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
74#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
75#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
76#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
77#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
78#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
79#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
80
81#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610) 79#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
82 80
83#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820) 81#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820)
@@ -85,13 +83,20 @@
85#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924) 83#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924)
86#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928) 84#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928)
87#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C) 85#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C)
88#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930) 86#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
87 S5P_CLKREG(0x0C930) : \
88 S5P_CLKREG(0x04930))
89#define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930)
90#define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930)
89#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) 91#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
90#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
91#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) 92#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
92#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C) 93#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C)
93#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) 94#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
94#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960) 95#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
96 S5P_CLKREG(0x0C960) : \
97 S5P_CLKREG(0x08960))
98#define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960)
99#define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960)
95#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970) 100#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970)
96 101
97#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300) 102#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300)
@@ -102,11 +107,17 @@
102#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900) 107#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900)
103 108
104#define S5P_APLL_LOCK S5P_CLKREG(0x14000) 109#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
105#define S5P_MPLL_LOCK S5P_CLKREG(0x14004) 110#define S5P_MPLL_LOCK (soc_is_exynos4210() ? \
111 S5P_CLKREG(0x14004) : \
112 S5P_CLKREG(0x10008))
106#define S5P_APLL_CON0 S5P_CLKREG(0x14100) 113#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
107#define S5P_APLL_CON1 S5P_CLKREG(0x14104) 114#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
108#define S5P_MPLL_CON0 S5P_CLKREG(0x14108) 115#define S5P_MPLL_CON0 (soc_is_exynos4210() ? \
109#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C) 116 S5P_CLKREG(0x14108) : \
117 S5P_CLKREG(0x10108))
118#define S5P_MPLL_CON1 (soc_is_exynos4210() ? \
119 S5P_CLKREG(0x1410C) : \
120 S5P_CLKREG(0x1010C))
110 121
111#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200) 122#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
112#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) 123#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
@@ -183,6 +194,13 @@
183#define S5P_CLKDIV_BUS_GPLR_SHIFT (4) 194#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
184#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT) 195#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
185 196
197/* Only for EXYNOS4210 */
198
199#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
200#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
201#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
202#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
203
186/* Compatibility defines and inclusion */ 204/* Compatibility defines and inclusion */
187 205
188#include <mach/regs-pmu.h> 206#include <mach/regs-pmu.h>
diff --git a/arch/arm/mach-exynos4/include/mach/regs-mct.h b/arch/arm/mach-exynos4/include/mach/regs-mct.h
index ca9c8434b023..80dd02ad6d61 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-mct.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-mct.h
@@ -31,8 +31,9 @@
31#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) 31#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
32#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) 32#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
33 33
34#define EXYNOS4_MCT_L0_BASE EXYNOS4_MCTREG(0x300) 34#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
35#define EXYNOS4_MCT_L1_BASE EXYNOS4_MCTREG(0x400) 35#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
36#define EXYNOS4_MCT_L_MASK (0xffffff00)
36 37
37#define MCT_L_TCNTB_OFFSET (0x00) 38#define MCT_L_TCNTB_OFFSET (0x00)
38#define MCT_L_ICNTB_OFFSET (0x08) 39#define MCT_L_ICNTB_OFFSET (0x08)
diff --git a/arch/arm/mach-exynos4/mach-origen.c b/arch/arm/mach-exynos4/mach-origen.c
new file mode 100644
index 000000000000..b5f6f38557c9
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-origen.c
@@ -0,0 +1,108 @@
1/* linux/arch/arm/mach-exynos4/mach-origen.c
2 *
3 * Copyright (c) 2011 Insignal Co., Ltd.
4 * http://www.insignal.co.kr/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/serial_core.h>
12#include <linux/gpio.h>
13#include <linux/mmc/host.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/input.h>
17
18#include <asm/mach/arch.h>
19#include <asm/mach-types.h>
20
21#include <plat/regs-serial.h>
22#include <plat/exynos4.h>
23#include <plat/cpu.h>
24#include <plat/devs.h>
25#include <plat/sdhci.h>
26#include <plat/iic.h>
27
28#include <mach/map.h>
29
30/* Following are default values for UCON, ULCON and UFCON UART registers */
31#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
32 S3C2410_UCON_RXILEVEL | \
33 S3C2410_UCON_TXIRQMODE | \
34 S3C2410_UCON_RXIRQMODE | \
35 S3C2410_UCON_RXFIFO_TOI | \
36 S3C2443_UCON_RXERR_IRQEN)
37
38#define ORIGEN_ULCON_DEFAULT S3C2410_LCON_CS8
39
40#define ORIGEN_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
41 S5PV210_UFCON_TXTRIG4 | \
42 S5PV210_UFCON_RXTRIG4)
43
44static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
45 [0] = {
46 .hwport = 0,
47 .flags = 0,
48 .ucon = ORIGEN_UCON_DEFAULT,
49 .ulcon = ORIGEN_ULCON_DEFAULT,
50 .ufcon = ORIGEN_UFCON_DEFAULT,
51 },
52 [1] = {
53 .hwport = 1,
54 .flags = 0,
55 .ucon = ORIGEN_UCON_DEFAULT,
56 .ulcon = ORIGEN_ULCON_DEFAULT,
57 .ufcon = ORIGEN_UFCON_DEFAULT,
58 },
59 [2] = {
60 .hwport = 2,
61 .flags = 0,
62 .ucon = ORIGEN_UCON_DEFAULT,
63 .ulcon = ORIGEN_ULCON_DEFAULT,
64 .ufcon = ORIGEN_UFCON_DEFAULT,
65 },
66 [3] = {
67 .hwport = 3,
68 .flags = 0,
69 .ucon = ORIGEN_UCON_DEFAULT,
70 .ulcon = ORIGEN_ULCON_DEFAULT,
71 .ufcon = ORIGEN_UFCON_DEFAULT,
72 },
73};
74
75static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
76 .cd_type = S3C_SDHCI_CD_GPIO,
77 .ext_cd_gpio = EXYNOS4_GPK2(2),
78 .ext_cd_gpio_invert = 1,
79 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
80};
81
82static struct platform_device *origen_devices[] __initdata = {
83 &s3c_device_hsmmc2,
84 &s3c_device_rtc,
85 &s3c_device_wdt,
86};
87
88static void __init origen_map_io(void)
89{
90 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
91 s3c24xx_init_clocks(24000000);
92 s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
93}
94
95static void __init origen_machine_init(void)
96{
97 s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
98 platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
99}
100
101MACHINE_START(ORIGEN, "ORIGEN")
102 /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
103 .atag_offset = 0x100,
104 .init_irq = exynos4_init_irq,
105 .map_io = origen_map_io,
106 .init_machine = origen_machine_init,
107 .timer = &exynos4_timer,
108MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdk4x12.c b/arch/arm/mach-exynos4/mach-smdk4x12.c
new file mode 100644
index 000000000000..fcf2e0e23d53
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-smdk4x12.c
@@ -0,0 +1,302 @@
1/*
2 * linux/arch/arm/mach-exynos4/mach-smdk4x12.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/gpio.h>
13#include <linux/i2c.h>
14#include <linux/input.h>
15#include <linux/io.h>
16#include <linux/mfd/max8997.h>
17#include <linux/mmc/host.h>
18#include <linux/platform_device.h>
19#include <linux/pwm_backlight.h>
20#include <linux/regulator/machine.h>
21#include <linux/serial_core.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach-types.h>
25
26#include <plat/backlight.h>
27#include <plat/clock.h>
28#include <plat/cpu.h>
29#include <plat/devs.h>
30#include <plat/exynos4.h>
31#include <plat/gpio-cfg.h>
32#include <plat/iic.h>
33#include <plat/keypad.h>
34#include <plat/regs-serial.h>
35#include <plat/sdhci.h>
36
37#include <mach/map.h>
38
39/* Following are default values for UCON, ULCON and UFCON UART registers */
40#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
41 S3C2410_UCON_RXILEVEL | \
42 S3C2410_UCON_TXIRQMODE | \
43 S3C2410_UCON_RXIRQMODE | \
44 S3C2410_UCON_RXFIFO_TOI | \
45 S3C2443_UCON_RXERR_IRQEN)
46
47#define SMDK4X12_ULCON_DEFAULT S3C2410_LCON_CS8
48
49#define SMDK4X12_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
50 S5PV210_UFCON_TXTRIG4 | \
51 S5PV210_UFCON_RXTRIG4)
52
53static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = {
54 [0] = {
55 .hwport = 0,
56 .flags = 0,
57 .ucon = SMDK4X12_UCON_DEFAULT,
58 .ulcon = SMDK4X12_ULCON_DEFAULT,
59 .ufcon = SMDK4X12_UFCON_DEFAULT,
60 },
61 [1] = {
62 .hwport = 1,
63 .flags = 0,
64 .ucon = SMDK4X12_UCON_DEFAULT,
65 .ulcon = SMDK4X12_ULCON_DEFAULT,
66 .ufcon = SMDK4X12_UFCON_DEFAULT,
67 },
68 [2] = {
69 .hwport = 2,
70 .flags = 0,
71 .ucon = SMDK4X12_UCON_DEFAULT,
72 .ulcon = SMDK4X12_ULCON_DEFAULT,
73 .ufcon = SMDK4X12_UFCON_DEFAULT,
74 },
75 [3] = {
76 .hwport = 3,
77 .flags = 0,
78 .ucon = SMDK4X12_UCON_DEFAULT,
79 .ulcon = SMDK4X12_ULCON_DEFAULT,
80 .ufcon = SMDK4X12_UFCON_DEFAULT,
81 },
82};
83
84static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
85 .cd_type = S3C_SDHCI_CD_INTERNAL,
86 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
87#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
88 .max_width = 8,
89 .host_caps = MMC_CAP_8_BIT_DATA,
90#endif
91};
92
93static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
94 .cd_type = S3C_SDHCI_CD_INTERNAL,
95 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
96};
97
98static struct regulator_consumer_supply max8997_buck1 =
99 REGULATOR_SUPPLY("vdd_arm", NULL);
100
101static struct regulator_consumer_supply max8997_buck2 =
102 REGULATOR_SUPPLY("vdd_int", NULL);
103
104static struct regulator_consumer_supply max8997_buck3 =
105 REGULATOR_SUPPLY("vdd_g3d", NULL);
106
107static struct regulator_init_data max8997_buck1_data = {
108 .constraints = {
109 .name = "VDD_ARM_SMDK4X12",
110 .min_uV = 925000,
111 .max_uV = 1350000,
112 .always_on = 1,
113 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
114 .state_mem = {
115 .disabled = 1,
116 },
117 },
118 .num_consumer_supplies = 1,
119 .consumer_supplies = &max8997_buck1,
120};
121
122static struct regulator_init_data max8997_buck2_data = {
123 .constraints = {
124 .name = "VDD_INT_SMDK4X12",
125 .min_uV = 950000,
126 .max_uV = 1150000,
127 .always_on = 1,
128 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
129 .state_mem = {
130 .disabled = 1,
131 },
132 },
133 .num_consumer_supplies = 1,
134 .consumer_supplies = &max8997_buck2,
135};
136
137static struct regulator_init_data max8997_buck3_data = {
138 .constraints = {
139 .name = "VDD_G3D_SMDK4X12",
140 .min_uV = 950000,
141 .max_uV = 1150000,
142 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
143 REGULATOR_CHANGE_STATUS,
144 .state_mem = {
145 .disabled = 1,
146 },
147 },
148 .num_consumer_supplies = 1,
149 .consumer_supplies = &max8997_buck3,
150};
151
152static struct max8997_regulator_data smdk4x12_max8997_regulators[] = {
153 { MAX8997_BUCK1, &max8997_buck1_data },
154 { MAX8997_BUCK2, &max8997_buck2_data },
155 { MAX8997_BUCK3, &max8997_buck3_data },
156};
157
158static struct max8997_platform_data smdk4x12_max8997_pdata = {
159 .num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators),
160 .regulators = smdk4x12_max8997_regulators,
161
162 .buck1_voltage[0] = 1100000, /* 1.1V */
163 .buck1_voltage[1] = 1100000, /* 1.1V */
164 .buck1_voltage[2] = 1100000, /* 1.1V */
165 .buck1_voltage[3] = 1100000, /* 1.1V */
166 .buck1_voltage[4] = 1100000, /* 1.1V */
167 .buck1_voltage[5] = 1100000, /* 1.1V */
168 .buck1_voltage[6] = 1000000, /* 1.0V */
169 .buck1_voltage[7] = 950000, /* 0.95V */
170
171 .buck2_voltage[0] = 1100000, /* 1.1V */
172 .buck2_voltage[1] = 1000000, /* 1.0V */
173 .buck2_voltage[2] = 950000, /* 0.95V */
174 .buck2_voltage[3] = 900000, /* 0.9V */
175 .buck2_voltage[4] = 1100000, /* 1.1V */
176 .buck2_voltage[5] = 1000000, /* 1.0V */
177 .buck2_voltage[6] = 950000, /* 0.95V */
178 .buck2_voltage[7] = 900000, /* 0.9V */
179
180 .buck5_voltage[0] = 1100000, /* 1.1V */
181 .buck5_voltage[1] = 1100000, /* 1.1V */
182 .buck5_voltage[2] = 1100000, /* 1.1V */
183 .buck5_voltage[3] = 1100000, /* 1.1V */
184 .buck5_voltage[4] = 1100000, /* 1.1V */
185 .buck5_voltage[5] = 1100000, /* 1.1V */
186 .buck5_voltage[6] = 1100000, /* 1.1V */
187 .buck5_voltage[7] = 1100000, /* 1.1V */
188};
189
190static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = {
191 {
192 I2C_BOARD_INFO("max8997", 0x66),
193 .platform_data = &smdk4x12_max8997_pdata,
194 }
195};
196
197static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = {
198 { I2C_BOARD_INFO("wm8994", 0x1a), }
199};
200
201static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = {
202 /* nothing here yet */
203};
204
205static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = {
206 /* nothing here yet */
207};
208
209static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = {
210 .no = EXYNOS4_GPD0(1),
211 .func = S3C_GPIO_SFN(2),
212};
213
214static struct platform_pwm_backlight_data smdk4x12_bl_data = {
215 .pwm_id = 1,
216 .pwm_period_ns = 1000,
217};
218
219static uint32_t smdk4x12_keymap[] __initdata = {
220 /* KEY(row, col, keycode) */
221 KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B),
222 KEY(1, 3, KEY_E), KEY(1, 4, KEY_C)
223};
224
225static struct matrix_keymap_data smdk4x12_keymap_data __initdata = {
226 .keymap = smdk4x12_keymap,
227 .keymap_size = ARRAY_SIZE(smdk4x12_keymap),
228};
229
230static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = {
231 .keymap_data = &smdk4x12_keymap_data,
232 .rows = 2,
233 .cols = 5,
234};
235
236static struct platform_device *smdk4x12_devices[] __initdata = {
237 &s3c_device_hsmmc2,
238 &s3c_device_hsmmc3,
239 &s3c_device_i2c0,
240 &s3c_device_i2c1,
241 &s3c_device_i2c3,
242 &s3c_device_i2c7,
243 &s3c_device_rtc,
244 &s3c_device_wdt,
245 &samsung_device_keypad,
246};
247
248static void __init smdk4x12_map_io(void)
249{
250 clk_xusbxti.rate = 24000000;
251
252 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
253 s3c24xx_init_clocks(clk_xusbxti.rate);
254 s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
255}
256
257static void __init smdk4x12_machine_init(void)
258{
259 s3c_i2c0_set_platdata(NULL);
260 i2c_register_board_info(0, smdk4x12_i2c_devs0,
261 ARRAY_SIZE(smdk4x12_i2c_devs0));
262
263 s3c_i2c1_set_platdata(NULL);
264 i2c_register_board_info(1, smdk4x12_i2c_devs1,
265 ARRAY_SIZE(smdk4x12_i2c_devs1));
266
267 s3c_i2c3_set_platdata(NULL);
268 i2c_register_board_info(3, smdk4x12_i2c_devs3,
269 ARRAY_SIZE(smdk4x12_i2c_devs3));
270
271 s3c_i2c7_set_platdata(NULL);
272 i2c_register_board_info(7, smdk4x12_i2c_devs7,
273 ARRAY_SIZE(smdk4x12_i2c_devs7));
274
275 samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);
276
277 samsung_keypad_set_platdata(&smdk4x12_keypad_data);
278
279 s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata);
280 s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata);
281
282 platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
283}
284
285MACHINE_START(SMDK4212, "SMDK4212")
286 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
287 .atag_offset = 0x100,
288 .init_irq = exynos4_init_irq,
289 .map_io = smdk4x12_map_io,
290 .init_machine = smdk4x12_machine_init,
291 .timer = &exynos4_timer,
292MACHINE_END
293
294MACHINE_START(SMDK4412, "SMDK4412")
295 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
296 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
297 .atag_offset = 0x100,
298 .init_irq = exynos4_init_irq,
299 .map_io = smdk4x12_map_io,
300 .init_machine = smdk4x12_machine_init,
301 .timer = &exynos4_timer,
302MACHINE_END
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index 582b874aab0e..f191608b28d6 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -20,19 +20,31 @@
20#include <linux/delay.h> 20#include <linux/delay.h>
21#include <linux/percpu.h> 21#include <linux/percpu.h>
22 22
23#include <asm/hardware/gic.h>
24
25#include <plat/cpu.h>
26
23#include <mach/map.h> 27#include <mach/map.h>
28#include <mach/irqs.h>
24#include <mach/regs-mct.h> 29#include <mach/regs-mct.h>
25#include <asm/mach/time.h> 30#include <asm/mach/time.h>
26 31
32enum {
33 MCT_INT_SPI,
34 MCT_INT_PPI
35};
36
27static unsigned long clk_cnt_per_tick; 37static unsigned long clk_cnt_per_tick;
28static unsigned long clk_rate; 38static unsigned long clk_rate;
39static unsigned int mct_int_type;
29 40
30struct mct_clock_event_device { 41struct mct_clock_event_device {
31 struct clock_event_device *evt; 42 struct clock_event_device *evt;
32 void __iomem *base; 43 void __iomem *base;
44 char name[10];
33}; 45};
34 46
35struct mct_clock_event_device mct_tick[2]; 47struct mct_clock_event_device mct_tick[NR_CPUS];
36 48
37static void exynos4_mct_write(unsigned int value, void *addr) 49static void exynos4_mct_write(unsigned int value, void *addr)
38{ 50{
@@ -42,57 +54,53 @@ static void exynos4_mct_write(unsigned int value, void *addr)
42 54
43 __raw_writel(value, addr); 55 __raw_writel(value, addr);
44 56
45 switch ((u32) addr) { 57 if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
46 case (u32) EXYNOS4_MCT_G_TCON: 58 u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
47 stat_addr = EXYNOS4_MCT_G_WSTAT; 59 switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
48 mask = 1 << 16; /* G_TCON write status */ 60 case (u32) MCT_L_TCON_OFFSET:
49 break; 61 stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
50 case (u32) EXYNOS4_MCT_G_COMP0_L: 62 mask = 1 << 3; /* L_TCON write status */
51 stat_addr = EXYNOS4_MCT_G_WSTAT; 63 break;
52 mask = 1 << 0; /* G_COMP0_L write status */ 64 case (u32) MCT_L_ICNTB_OFFSET:
53 break; 65 stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
54 case (u32) EXYNOS4_MCT_G_COMP0_U: 66 mask = 1 << 1; /* L_ICNTB write status */
55 stat_addr = EXYNOS4_MCT_G_WSTAT; 67 break;
56 mask = 1 << 1; /* G_COMP0_U write status */ 68 case (u32) MCT_L_TCNTB_OFFSET:
57 break; 69 stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
58 case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR: 70 mask = 1 << 0; /* L_TCNTB write status */
59 stat_addr = EXYNOS4_MCT_G_WSTAT; 71 break;
60 mask = 1 << 2; /* G_COMP0_ADD_INCR write status */ 72 default:
61 break; 73 return;
62 case (u32) EXYNOS4_MCT_G_CNT_L: 74 }
63 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; 75 } else {
64 mask = 1 << 0; /* G_CNT_L write status */ 76 switch ((u32) addr) {
65 break; 77 case (u32) EXYNOS4_MCT_G_TCON:
66 case (u32) EXYNOS4_MCT_G_CNT_U: 78 stat_addr = EXYNOS4_MCT_G_WSTAT;
67 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; 79 mask = 1 << 16; /* G_TCON write status */
68 mask = 1 << 1; /* G_CNT_U write status */ 80 break;
69 break; 81 case (u32) EXYNOS4_MCT_G_COMP0_L:
70 case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET): 82 stat_addr = EXYNOS4_MCT_G_WSTAT;
71 stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET; 83 mask = 1 << 0; /* G_COMP0_L write status */
72 mask = 1 << 3; /* L0_TCON write status */ 84 break;
73 break; 85 case (u32) EXYNOS4_MCT_G_COMP0_U:
74 case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET): 86 stat_addr = EXYNOS4_MCT_G_WSTAT;
75 stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET; 87 mask = 1 << 1; /* G_COMP0_U write status */
76 mask = 1 << 3; /* L1_TCON write status */ 88 break;
77 break; 89 case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
78 case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET): 90 stat_addr = EXYNOS4_MCT_G_WSTAT;
79 stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET; 91 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
80 mask = 1 << 0; /* L0_TCNTB write status */ 92 break;
81 break; 93 case (u32) EXYNOS4_MCT_G_CNT_L:
82 case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET): 94 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
83 stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET; 95 mask = 1 << 0; /* G_CNT_L write status */
84 mask = 1 << 0; /* L1_TCNTB write status */ 96 break;
85 break; 97 case (u32) EXYNOS4_MCT_G_CNT_U:
86 case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET): 98 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
87 stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET; 99 mask = 1 << 1; /* G_CNT_U write status */
88 mask = 1 << 1; /* L0_ICNTB write status */ 100 break;
89 break; 101 default:
90 case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET): 102 return;
91 stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET; 103 }
92 mask = 1 << 1; /* L1_ICNTB write status */
93 break;
94 default:
95 return;
96 } 104 }
97 105
98 /* Wait maximum 1 ms until written values are applied */ 106 /* Wait maximum 1 ms until written values are applied */
@@ -321,9 +329,8 @@ static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
321 } 329 }
322} 330}
323 331
324static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) 332static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
325{ 333{
326 struct mct_clock_event_device *mevt = dev_id;
327 struct clock_event_device *evt = mevt->evt; 334 struct clock_event_device *evt = mevt->evt;
328 335
329 /* 336 /*
@@ -335,7 +342,20 @@ static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
335 exynos4_mct_tick_stop(mevt); 342 exynos4_mct_tick_stop(mevt);
336 343
337 /* Clear the MCT tick interrupt */ 344 /* Clear the MCT tick interrupt */
338 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); 345 if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
346 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
347 return 1;
348 } else {
349 return 0;
350 }
351}
352
353static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
354{
355 struct mct_clock_event_device *mevt = dev_id;
356 struct clock_event_device *evt = mevt->evt;
357
358 exynos4_mct_tick_clear(mevt);
339 359
340 evt->event_handler(evt); 360 evt->event_handler(evt);
341 361
@@ -360,14 +380,10 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
360 380
361 mct_tick[cpu].evt = evt; 381 mct_tick[cpu].evt = evt;
362 382
363 if (cpu == 0) { 383 mct_tick[cpu].base = EXYNOS4_MCT_L_BASE(cpu);
364 mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE; 384 sprintf(mct_tick[cpu].name, "mct_tick%d", cpu);
365 evt->name = "mct_tick0";
366 } else {
367 mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE;
368 evt->name = "mct_tick1";
369 }
370 385
386 evt->name = mct_tick[cpu].name;
371 evt->cpumask = cpumask_of(cpu); 387 evt->cpumask = cpumask_of(cpu);
372 evt->set_next_event = exynos4_tick_set_next_event; 388 evt->set_next_event = exynos4_tick_set_next_event;
373 evt->set_mode = exynos4_tick_set_mode; 389 evt->set_mode = exynos4_tick_set_mode;
@@ -384,15 +400,19 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
384 400
385 exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET); 401 exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
386 402
387 if (cpu == 0) { 403 if (mct_int_type == MCT_INT_SPI) {
388 mct_tick0_event_irq.dev_id = &mct_tick[cpu]; 404 if (cpu == 0) {
389 evt->irq = IRQ_MCT_L0; 405 mct_tick0_event_irq.dev_id = &mct_tick[cpu];
390 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq); 406 evt->irq = IRQ_MCT_L0;
407 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
408 } else {
409 mct_tick1_event_irq.dev_id = &mct_tick[cpu];
410 evt->irq = IRQ_MCT_L1;
411 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
412 irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
413 }
391 } else { 414 } else {
392 mct_tick1_event_irq.dev_id = &mct_tick[cpu]; 415 gic_enable_ppi(IRQ_MCT_LOCALTIMER);
393 evt->irq = IRQ_MCT_L1;
394 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
395 irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
396 } 416 }
397} 417}
398 418
@@ -422,6 +442,11 @@ static void __init exynos4_timer_resources(void)
422 442
423static void __init exynos4_timer_init(void) 443static void __init exynos4_timer_init(void)
424{ 444{
445 if (soc_is_exynos4210())
446 mct_int_type = MCT_INT_SPI;
447 else
448 mct_int_type = MCT_INT_PPI;
449
425 exynos4_timer_resources(); 450 exynos4_timer_resources();
426 exynos4_clocksource_init(); 451 exynos4_clocksource_init();
427 exynos4_clockevent_init(); 452 exynos4_clockevent_init();
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index 0c90896ad9a0..782dcf11d234 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -30,9 +30,13 @@
30#include <mach/regs-clock.h> 30#include <mach/regs-clock.h>
31#include <mach/regs-pmu.h> 31#include <mach/regs-pmu.h>
32 32
33#include <plat/cpu.h>
34
35extern unsigned int gic_bank_offset;
33extern void exynos4_secondary_startup(void); 36extern void exynos4_secondary_startup(void);
34 37
35#define CPU1_BOOT_REG S5P_VA_SYSRAM 38#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
39 S5P_INFORM5 : S5P_VA_SYSRAM)
36 40
37/* 41/*
38 * control for which core is the next to come out of the secondary 42 * control for which core is the next to come out of the secondary
@@ -64,9 +68,9 @@ static DEFINE_SPINLOCK(boot_lock);
64static void __cpuinit exynos4_gic_secondary_init(void) 68static void __cpuinit exynos4_gic_secondary_init(void)
65{ 69{
66 void __iomem *dist_base = S5P_VA_GIC_DIST + 70 void __iomem *dist_base = S5P_VA_GIC_DIST +
67 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); 71 (gic_bank_offset * smp_processor_id());
68 void __iomem *cpu_base = S5P_VA_GIC_CPU + 72 void __iomem *cpu_base = S5P_VA_GIC_CPU +
69 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); 73 (gic_bank_offset * smp_processor_id());
70 int i; 74 int i;
71 75
72 /* 76 /*
@@ -216,5 +220,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
216 * until it receives a soft interrupt, and then the 220 * until it receives a soft interrupt, and then the
217 * secondary CPU branches to this address. 221 * secondary CPU branches to this address.
218 */ 222 */
219 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM); 223 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
224 CPU1_BOOT_REG);
220} 225}
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index bc6ca9482de1..62e4f4363006 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -41,7 +41,6 @@ static struct sleep_save exynos4_set_clksrc[] = {
41 { .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, }, 41 { .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, },
42 { .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, }, 42 { .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, },
43 { .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, 43 { .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
44 { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
45 { .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, 44 { .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
46 { .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, }, 45 { .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, },
47 { .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, 46 { .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
@@ -49,6 +48,10 @@ static struct sleep_save exynos4_set_clksrc[] = {
49 { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, }, 48 { .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
50}; 49};
51 50
51static struct sleep_save exynos4210_set_clksrc[] = {
52 { .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
53};
54
52static struct sleep_save exynos4_epll_save[] = { 55static struct sleep_save exynos4_epll_save[] = {
53 SAVE_ITEM(S5P_EPLL_CON0), 56 SAVE_ITEM(S5P_EPLL_CON0),
54 SAVE_ITEM(S5P_EPLL_CON1), 57 SAVE_ITEM(S5P_EPLL_CON1),
@@ -60,77 +63,6 @@ static struct sleep_save exynos4_vpll_save[] = {
60}; 63};
61 64
62static struct sleep_save exynos4_core_save[] = { 65static struct sleep_save exynos4_core_save[] = {
63 /* CMU side */
64 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
65 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
66 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
67 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
68 SAVE_ITEM(S5P_CLKSRC_TOP0),
69 SAVE_ITEM(S5P_CLKSRC_TOP1),
70 SAVE_ITEM(S5P_CLKSRC_CAM),
71 SAVE_ITEM(S5P_CLKSRC_TV),
72 SAVE_ITEM(S5P_CLKSRC_MFC),
73 SAVE_ITEM(S5P_CLKSRC_G3D),
74 SAVE_ITEM(S5P_CLKSRC_IMAGE),
75 SAVE_ITEM(S5P_CLKSRC_LCD0),
76 SAVE_ITEM(S5P_CLKSRC_LCD1),
77 SAVE_ITEM(S5P_CLKSRC_MAUDIO),
78 SAVE_ITEM(S5P_CLKSRC_FSYS),
79 SAVE_ITEM(S5P_CLKSRC_PERIL0),
80 SAVE_ITEM(S5P_CLKSRC_PERIL1),
81 SAVE_ITEM(S5P_CLKDIV_CAM),
82 SAVE_ITEM(S5P_CLKDIV_TV),
83 SAVE_ITEM(S5P_CLKDIV_MFC),
84 SAVE_ITEM(S5P_CLKDIV_G3D),
85 SAVE_ITEM(S5P_CLKDIV_IMAGE),
86 SAVE_ITEM(S5P_CLKDIV_LCD0),
87 SAVE_ITEM(S5P_CLKDIV_LCD1),
88 SAVE_ITEM(S5P_CLKDIV_MAUDIO),
89 SAVE_ITEM(S5P_CLKDIV_FSYS0),
90 SAVE_ITEM(S5P_CLKDIV_FSYS1),
91 SAVE_ITEM(S5P_CLKDIV_FSYS2),
92 SAVE_ITEM(S5P_CLKDIV_FSYS3),
93 SAVE_ITEM(S5P_CLKDIV_PERIL0),
94 SAVE_ITEM(S5P_CLKDIV_PERIL1),
95 SAVE_ITEM(S5P_CLKDIV_PERIL2),
96 SAVE_ITEM(S5P_CLKDIV_PERIL3),
97 SAVE_ITEM(S5P_CLKDIV_PERIL4),
98 SAVE_ITEM(S5P_CLKDIV_PERIL5),
99 SAVE_ITEM(S5P_CLKDIV_TOP),
100 SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
101 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
102 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
103 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
104 SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
105 SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
106 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
107 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
108 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
109 SAVE_ITEM(S5P_CLKDIV2_RATIO),
110 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
111 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
112 SAVE_ITEM(S5P_CLKGATE_IP_TV),
113 SAVE_ITEM(S5P_CLKGATE_IP_MFC),
114 SAVE_ITEM(S5P_CLKGATE_IP_G3D),
115 SAVE_ITEM(S5P_CLKGATE_IP_IMAGE),
116 SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
117 SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
118 SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
119 SAVE_ITEM(S5P_CLKGATE_IP_GPS),
120 SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
121 SAVE_ITEM(S5P_CLKGATE_IP_PERIR),
122 SAVE_ITEM(S5P_CLKGATE_BLOCK),
123 SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
124 SAVE_ITEM(S5P_CLKSRC_DMC),
125 SAVE_ITEM(S5P_CLKDIV_DMC0),
126 SAVE_ITEM(S5P_CLKDIV_DMC1),
127 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
128 SAVE_ITEM(S5P_CLKSRC_CPU),
129 SAVE_ITEM(S5P_CLKDIV_CPU),
130 SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
131 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
132 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
133
134 /* GIC side */ 66 /* GIC side */
135 SAVE_ITEM(S5P_VA_GIC_CPU + 0x000), 67 SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
136 SAVE_ITEM(S5P_VA_GIC_CPU + 0x004), 68 SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
@@ -268,6 +200,9 @@ static void exynos4_pm_prepare(void)
268 200
269 s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc)); 201 s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
270 202
203 if (soc_is_exynos4210())
204 s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
205
271} 206}
272 207
273static int exynos4_pm_add(struct sys_device *sysdev) 208static int exynos4_pm_add(struct sys_device *sysdev)
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 6f991c5ae863..fd5e7b6881bf 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -179,6 +179,25 @@ config MACH_GTWX5715
179 "High Speed" UART is n/c (as far as I can tell) 179 "High Speed" UART is n/c (as far as I can tell)
180 20 Pin ARM/Xscale JTAG interface on J2 180 20 Pin ARM/Xscale JTAG interface on J2
181 181
182config MACH_DEVIXP
183 bool "Omicron DEVIXP"
184 help
185 Say 'Y' here if you want your kernel to support the DEVIXP
186 board from OMICRON electronics GmbH.
187
188config MACH_MICCPT
189 bool "Omicron MICCPT"
190 select PCI
191 help
192 Say 'Y' here if you want your kernel to support the MICCPT
193 board from OMICRON electronics GmbH.
194
195config MACH_MIC256
196 bool "Omicron MIC256"
197 help
198 Say 'Y' here if you want your kernel to support the MIC256
199 board from OMICRON electronics GmbH.
200
182comment "IXP4xx Options" 201comment "IXP4xx Options"
183 202
184config IXP4XX_INDIRECT_PCI 203config IXP4XX_INDIRECT_PCI
diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
index d807fc367dd3..eded94c96dd4 100644
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -10,6 +10,7 @@ obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o
10obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o 10obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o
11obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o 11obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o
12obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o 12obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o
13obj-pci-$(CONFIG_MACH_MICCPT) += miccpt-pci.o
13obj-pci-$(CONFIG_MACH_NSLU2) += nslu2-pci.o 14obj-pci-$(CONFIG_MACH_NSLU2) += nslu2-pci.o
14obj-pci-$(CONFIG_MACH_NAS100D) += nas100d-pci.o 15obj-pci-$(CONFIG_MACH_NAS100D) += nas100d-pci.o
15obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o 16obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o
@@ -25,6 +26,9 @@ obj-$(CONFIG_MACH_AVILA) += avila-setup.o
25obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o 26obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o
26obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o 27obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o
27obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o 28obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o
29obj-$(CONFIG_MACH_DEVIXP) += omixp-setup.o
30obj-$(CONFIG_MACH_MICCPT) += omixp-setup.o
31obj-$(CONFIG_MACH_MIC256) += omixp-setup.o
28obj-$(CONFIG_MACH_NSLU2) += nslu2-setup.o 32obj-$(CONFIG_MACH_NSLU2) += nslu2-setup.o
29obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o 33obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o
30obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o 34obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o
diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
index 219d7c1dcdba..eb945a926d07 100644
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -41,7 +41,8 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
41 * Some boards are using UART2 as console 41 * Some boards are using UART2 as console
42 */ 42 */
43 if (machine_is_adi_coyote() || machine_is_gtwx5715() || 43 if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
44 machine_is_gateway7001() || machine_is_wg302v2()) 44 machine_is_gateway7001() || machine_is_wg302v2() ||
45 machine_is_devixp() || machine_is_miccpt() || machine_is_mic256())
45 uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS; 46 uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
46 else 47 else
47 uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS; 48 uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
diff --git a/arch/arm/mach-ixp4xx/miccpt-pci.c b/arch/arm/mach-ixp4xx/miccpt-pci.c
new file mode 100644
index 000000000000..ca0bae7fca90
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/miccpt-pci.c
@@ -0,0 +1,78 @@
1/*
2 * arch/arm/mach-ixp4xx/miccpt-pci.c
3 *
4 * MICCPT board-level PCI initialization
5 *
6 * Copyright (C) 2002 Intel Corporation.
7 * Copyright (C) 2003-2004 MontaVista Software, Inc.
8 * Copyright (C) 2006 OMICRON electronics GmbH
9 *
10 * Author: Michael Jochum <michael.jochum@omicron.at>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/pci.h>
20#include <linux/init.h>
21#include <linux/delay.h>
22#include <linux/irq.h>
23#include <asm/mach/pci.h>
24#include <asm/irq.h>
25#include <mach/hardware.h>
26#include <asm/mach-types.h>
27
28#define MAX_DEV 4
29#define IRQ_LINES 4
30
31/* PCI controller GPIO to IRQ pin mappings */
32#define INTA 1
33#define INTB 2
34#define INTC 3
35#define INTD 4
36
37
38void __init miccpt_pci_preinit(void)
39{
40 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
41 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
42 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
43 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
44 ixp4xx_pci_preinit();
45}
46
47static int __init miccpt_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
48{
49 static int pci_irq_table[IRQ_LINES] = {
50 IXP4XX_GPIO_IRQ(INTA),
51 IXP4XX_GPIO_IRQ(INTB),
52 IXP4XX_GPIO_IRQ(INTC),
53 IXP4XX_GPIO_IRQ(INTD)
54 };
55
56 if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
57 return pci_irq_table[(slot + pin - 2) % 4];
58
59 return -1;
60}
61
62struct hw_pci miccpt_pci __initdata = {
63 .nr_controllers = 1,
64 .preinit = miccpt_pci_preinit,
65 .swizzle = pci_std_swizzle,
66 .setup = ixp4xx_setup,
67 .scan = ixp4xx_scan_bus,
68 .map_irq = miccpt_map_irq,
69};
70
71int __init miccpt_pci_init(void)
72{
73 if (machine_is_miccpt())
74 pci_common_init(&miccpt_pci);
75 return 0;
76}
77
78subsys_initcall(miccpt_pci_init);
diff --git a/arch/arm/mach-ixp4xx/omixp-setup.c b/arch/arm/mach-ixp4xx/omixp-setup.c
new file mode 100644
index 000000000000..3b6a81a696fc
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/omixp-setup.c
@@ -0,0 +1,273 @@
1/*
2 * arch/arm/mach-ixp4xx/omixp-setup.c
3 *
4 * omicron ixp4xx board setup
5 * Copyright (C) 2009 OMICRON electronics GmbH
6 *
7 * based nslu2-setup.c, ixdp425-setup.c:
8 * Copyright (C) 2003-2004 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/serial.h>
17#include <linux/serial_8250.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/partitions.h>
20#ifdef CONFIG_LEDS_CLASS
21#include <linux/leds.h>
22#endif
23
24#include <asm/setup.h>
25#include <asm/memory.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/flash.h>
29
30static struct resource omixp_flash_resources[] = {
31 {
32 .flags = IORESOURCE_MEM,
33 }, {
34 .flags = IORESOURCE_MEM,
35 },
36};
37
38static struct mtd_partition omixp_partitions[] = {
39 {
40 .name = "Recovery Bootloader",
41 .size = 0x00020000,
42 .offset = 0,
43 }, {
44 .name = "Calibration Data",
45 .size = 0x00020000,
46 .offset = 0x00020000,
47 }, {
48 .name = "Recovery FPGA",
49 .size = 0x00020000,
50 .offset = 0x00040000,
51 }, {
52 .name = "Release Bootloader",
53 .size = 0x00020000,
54 .offset = 0x00060000,
55 }, {
56 .name = "Release FPGA",
57 .size = 0x00020000,
58 .offset = 0x00080000,
59 }, {
60 .name = "Kernel",
61 .size = 0x00160000,
62 .offset = 0x000a0000,
63 }, {
64 .name = "Filesystem",
65 .size = 0x00C00000,
66 .offset = 0x00200000,
67 }, {
68 .name = "Persistent Storage",
69 .size = 0x00200000,
70 .offset = 0x00E00000,
71 },
72};
73
74static struct flash_platform_data omixp_flash_data[] = {
75 {
76 .map_name = "cfi_probe",
77 .parts = omixp_partitions,
78 .nr_parts = ARRAY_SIZE(omixp_partitions),
79 }, {
80 .map_name = "cfi_probe",
81 .parts = NULL,
82 .nr_parts = 0,
83 },
84};
85
86static struct platform_device omixp_flash_device[] = {
87 {
88 .name = "IXP4XX-Flash",
89 .id = 0,
90 .dev = {
91 .platform_data = &omixp_flash_data[0],
92 },
93 .resource = &omixp_flash_resources[0],
94 .num_resources = 1,
95 }, {
96 .name = "IXP4XX-Flash",
97 .id = 1,
98 .dev = {
99 .platform_data = &omixp_flash_data[1],
100 },
101 .resource = &omixp_flash_resources[1],
102 .num_resources = 1,
103 },
104};
105
106/* Swap UART's - These boards have the console on UART2. The following
107 * configuration is used:
108 * ttyS0 .. UART2
109 * ttyS1 .. UART1
110 * This way standard images can be used with the kernel that expect
111 * the console on ttyS0.
112 */
113static struct resource omixp_uart_resources[] = {
114 {
115 .start = IXP4XX_UART2_BASE_PHYS,
116 .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
117 .flags = IORESOURCE_MEM,
118 }, {
119 .start = IXP4XX_UART1_BASE_PHYS,
120 .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
121 .flags = IORESOURCE_MEM,
122 },
123};
124
125static struct plat_serial8250_port omixp_uart_data[] = {
126 {
127 .mapbase = IXP4XX_UART2_BASE_PHYS,
128 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
129 .irq = IRQ_IXP4XX_UART2,
130 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
131 .iotype = UPIO_MEM,
132 .regshift = 2,
133 .uartclk = IXP4XX_UART_XTAL,
134 }, {
135 .mapbase = IXP4XX_UART1_BASE_PHYS,
136 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
137 .irq = IRQ_IXP4XX_UART1,
138 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
139 .iotype = UPIO_MEM,
140 .regshift = 2,
141 .uartclk = IXP4XX_UART_XTAL,
142 }, {
143 /* list termination */
144 }
145};
146
147static struct platform_device omixp_uart = {
148 .name = "serial8250",
149 .id = PLAT8250_DEV_PLATFORM,
150 .dev.platform_data = omixp_uart_data,
151 .num_resources = 2,
152 .resource = omixp_uart_resources,
153};
154
155static struct gpio_led mic256_led_pins[] = {
156 {
157 .name = "LED-A",
158 .gpio = 7,
159 },
160};
161
162static struct gpio_led_platform_data mic256_led_data = {
163 .num_leds = ARRAY_SIZE(mic256_led_pins),
164 .leds = mic256_led_pins,
165};
166
167static struct platform_device mic256_leds = {
168 .name = "leds-gpio",
169 .id = -1,
170 .dev.platform_data = &mic256_led_data,
171};
172
173/* Built-in 10/100 Ethernet MAC interfaces */
174static struct eth_plat_info ixdp425_plat_eth[] = {
175 {
176 .phy = 0,
177 .rxq = 3,
178 .txreadyq = 20,
179 }, {
180 .phy = 1,
181 .rxq = 4,
182 .txreadyq = 21,
183 },
184};
185
186static struct platform_device ixdp425_eth[] = {
187 {
188 .name = "ixp4xx_eth",
189 .id = IXP4XX_ETH_NPEB,
190 .dev.platform_data = ixdp425_plat_eth,
191 }, {
192 .name = "ixp4xx_eth",
193 .id = IXP4XX_ETH_NPEC,
194 .dev.platform_data = ixdp425_plat_eth + 1,
195 },
196};
197
198
199static struct platform_device *devixp_pldev[] __initdata = {
200 &omixp_uart,
201 &omixp_flash_device[0],
202 &ixdp425_eth[0],
203 &ixdp425_eth[1],
204};
205
206static struct platform_device *mic256_pldev[] __initdata = {
207 &omixp_uart,
208 &omixp_flash_device[0],
209 &mic256_leds,
210 &ixdp425_eth[0],
211 &ixdp425_eth[1],
212};
213
214static struct platform_device *miccpt_pldev[] __initdata = {
215 &omixp_uart,
216 &omixp_flash_device[0],
217 &omixp_flash_device[1],
218 &ixdp425_eth[0],
219 &ixdp425_eth[1],
220};
221
222static void __init omixp_init(void)
223{
224 ixp4xx_sys_init();
225
226 /* 16MiB Boot Flash */
227 omixp_flash_resources[0].start = IXP4XX_EXP_BUS_BASE(0);
228 omixp_flash_resources[0].end = IXP4XX_EXP_BUS_END(0);
229
230 /* 32 MiB Data Flash */
231 omixp_flash_resources[1].start = IXP4XX_EXP_BUS_BASE(2);
232 omixp_flash_resources[1].end = IXP4XX_EXP_BUS_END(2);
233
234 if (machine_is_devixp())
235 platform_add_devices(devixp_pldev, ARRAY_SIZE(devixp_pldev));
236 else if (machine_is_miccpt())
237 platform_add_devices(miccpt_pldev, ARRAY_SIZE(miccpt_pldev));
238 else if (machine_is_mic256())
239 platform_add_devices(mic256_pldev, ARRAY_SIZE(mic256_pldev));
240}
241
242#ifdef CONFIG_MACH_DEVIXP
243MACHINE_START(DEVIXP, "Omicron DEVIXP")
244 .atag_offset = 0x100,
245 .map_io = ixp4xx_map_io,
246 .init_irq = ixp4xx_init_irq,
247 .timer = &ixp4xx_timer,
248 .init_machine = omixp_init,
249MACHINE_END
250#endif
251
252#ifdef CONFIG_MACH_MICCPT
253MACHINE_START(MICCPT, "Omicron MICCPT")
254 .atag_offset = 0x100,
255 .map_io = ixp4xx_map_io,
256 .init_irq = ixp4xx_init_irq,
257 .timer = &ixp4xx_timer,
258 .init_machine = omixp_init,
259#if defined(CONFIG_PCI)
260 .dma_zone_size = SZ_64M,
261#endif
262MACHINE_END
263#endif
264
265#ifdef CONFIG_MACH_MIC256
266MACHINE_START(MIC256, "Omicron MIC256")
267 .atag_offset = 0x100,
268 .map_io = ixp4xx_map_io,
269 .init_irq = ixp4xx_init_irq,
270 .timer = &ixp4xx_timer,
271 .init_machine = omixp_init,
272MACHINE_END
273#endif
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 4cd0231ee539..ea5ec0f3b5b1 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -64,8 +64,25 @@ config MODULE_TX28
64 select MXS_HAVE_PLATFORM_MXS_MMC 64 select MXS_HAVE_PLATFORM_MXS_MMC
65 select MXS_HAVE_PLATFORM_MXS_PWM 65 select MXS_HAVE_PLATFORM_MXS_PWM
66 66
67config MODULE_M28
68 bool
69 select SOC_IMX28
70 select LEDS_GPIO_REGISTER
71 select MXS_HAVE_AMBA_DUART
72 select MXS_HAVE_PLATFORM_AUART
73 select MXS_HAVE_PLATFORM_FEC
74 select MXS_HAVE_PLATFORM_FLEXCAN
75 select MXS_HAVE_PLATFORM_MXS_I2C
76 select MXS_HAVE_PLATFORM_MXS_MMC
77 select MXS_HAVE_PLATFORM_MXSFB
78 select MXS_OCOTP
79
67config MACH_TX28 80config MACH_TX28
68 bool "Ka-Ro TX28 module" 81 bool "Ka-Ro TX28 module"
69 select MODULE_TX28 82 select MODULE_TX28
70 83
84config MACH_M28EVK
85 bool "Support DENX M28EVK Platform"
86 select MODULE_M28
87
71endif 88endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index ea8dcb7742bc..8c93b24896bf 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
10obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o 10obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
11obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o 11obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
12obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o 12obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
13obj-$(CONFIG_MACH_M28EVK) += mach-m28evk.o
13obj-$(CONFIG_MODULE_TX28) += module-tx28.o 14obj-$(CONFIG_MODULE_TX28) += module-tx28.o
14obj-$(CONFIG_MACH_TX28) += mach-tx28.o 15obj-$(CONFIG_MACH_TX28) += mach-tx28.o
15 16
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index ba532279d1a1..7fa1ac4de7d8 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -738,11 +738,17 @@ static int clk_misc_init(void)
738 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, 738 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
739 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET); 739 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
740 740
741 /* Extra fec clock setting */ 741 /*
742 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); 742 * Extra fec clock setting
743 reg &= ~BM_CLKCTRL_ENET_SLEEP; 743 * The DENX M28 uses an external clock source
744 reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; 744 * and the clock output must not be enabled
745 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); 745 */
746 if (!machine_is_m28evk()) {
747 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
748 reg &= ~BM_CLKCTRL_ENET_SLEEP;
749 reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
750 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
751 }
746 752
747 /* 753 /*
748 * 480 MHz seems too high to be ssp clock source directly, 754 * 480 MHz seems too high to be ssp clock source directly,
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
index 5aa5f754c846..0d2d2b470998 100644
--- a/arch/arm/mach-mxs/include/mach/mxs.h
+++ b/arch/arm/mach-mxs/include/mach/mxs.h
@@ -33,6 +33,7 @@
33 0) 33 0)
34#define cpu_is_mx28() ( \ 34#define cpu_is_mx28() ( \
35 machine_is_mx28evk() || \ 35 machine_is_mx28evk() || \
36 machine_is_m28evk() || \
36 machine_is_tx28() || \ 37 machine_is_tx28() || \
37 0) 38 0)
38 39
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
index 7f8bf6539646..67776746f143 100644
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -63,6 +63,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
63 mxs_duart_base = MX23_DUART_BASE_ADDR; 63 mxs_duart_base = MX23_DUART_BASE_ADDR;
64 break; 64 break;
65 case MACH_TYPE_MX28EVK: 65 case MACH_TYPE_MX28EVK:
66 case MACH_TYPE_M28EVK:
66 case MACH_TYPE_TX28: 67 case MACH_TYPE_TX28:
67 mxs_duart_base = MX28_DUART_BASE_ADDR; 68 mxs_duart_base = MX28_DUART_BASE_ADDR;
68 break; 69 break;
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
new file mode 100644
index 000000000000..3b1681e4f49a
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-m28evk.c
@@ -0,0 +1,366 @@
1/*
2 * Copyright (C) 2011
3 * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
4 *
5 * based on: mach-mx28_evk.c
6 * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/delay.h>
20#include <linux/platform_device.h>
21#include <linux/gpio.h>
22#include <linux/leds.h>
23#include <linux/irq.h>
24#include <linux/clk.h>
25#include <linux/i2c.h>
26#include <linux/i2c/at24.h>
27
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30#include <asm/mach/time.h>
31
32#include <mach/common.h>
33#include <mach/iomux-mx28.h>
34
35#include "devices-mx28.h"
36
37#define M28EVK_GPIO_USERLED1 MXS_GPIO_NR(3, 16)
38#define M28EVK_GPIO_USERLED2 MXS_GPIO_NR(3, 17)
39
40#define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18)
41#define M28EVK_LCD_ENABLE MXS_GPIO_NR(3, 28)
42
43#define MX28EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(2, 12)
44#define MX28EVK_MMC1_WRITE_PROTECT MXS_GPIO_NR(0, 28)
45
46static const iomux_cfg_t m28evk_pads[] __initconst = {
47 /* duart */
48 MX28_PAD_AUART0_CTS__DUART_RX | MXS_PAD_CTRL,
49 MX28_PAD_AUART0_RTS__DUART_TX | MXS_PAD_CTRL,
50
51 /* auart0 */
52 MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
53 MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
54
55 /* auart3 */
56 MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
57 MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
58 MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
59 MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
60
61#define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
62 /* fec0 */
63 MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
64 MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
65 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
66 MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
67 MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
68 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
69 MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
70 MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
71 MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
72 /* fec1 */
73 MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
74 MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
75 MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
76 MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
77 MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
78 MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
79
80 /* flexcan0 */
81 MX28_PAD_GPMI_RDY2__CAN0_TX,
82 MX28_PAD_GPMI_RDY3__CAN0_RX,
83
84 /* flexcan1 */
85 MX28_PAD_GPMI_CE2N__CAN1_TX,
86 MX28_PAD_GPMI_CE3N__CAN1_RX,
87
88 /* I2C */
89 MX28_PAD_I2C0_SCL__I2C0_SCL,
90 MX28_PAD_I2C0_SDA__I2C0_SDA,
91
92 /* mxsfb (lcdif) */
93 MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
94 MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
95 MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
96 MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
97 MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
98 MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
99 MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
100 MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
101 MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
102 MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
103 MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
104 MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
105 MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
106 MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
107 MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
108 MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
109 MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
110 MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
111 MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
112 MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
113 MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
114 MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
115 MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
116 MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
117
118 MX28_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL,
119 MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL,
120
121 /* mmc0 */
122 MX28_PAD_SSP0_DATA0__SSP0_D0 |
123 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
124 MX28_PAD_SSP0_DATA1__SSP0_D1 |
125 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
126 MX28_PAD_SSP0_DATA2__SSP0_D2 |
127 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
128 MX28_PAD_SSP0_DATA3__SSP0_D3 |
129 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
130 MX28_PAD_SSP0_DATA4__SSP0_D4 |
131 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
132 MX28_PAD_SSP0_DATA5__SSP0_D5 |
133 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
134 MX28_PAD_SSP0_DATA6__SSP0_D6 |
135 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
136 MX28_PAD_SSP0_DATA7__SSP0_D7 |
137 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
138 MX28_PAD_SSP0_CMD__SSP0_CMD |
139 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
140 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
141 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
142 MX28_PAD_SSP0_SCK__SSP0_SCK |
143 (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
144
145 /* mmc1 */
146 MX28_PAD_GPMI_D00__SSP1_D0 |
147 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
148 MX28_PAD_GPMI_D01__SSP1_D1 |
149 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
150 MX28_PAD_GPMI_D02__SSP1_D2 |
151 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
152 MX28_PAD_GPMI_D03__SSP1_D3 |
153 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
154 MX28_PAD_GPMI_D04__SSP1_D4 |
155 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
156 MX28_PAD_GPMI_D05__SSP1_D5 |
157 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
158 MX28_PAD_GPMI_D06__SSP1_D6 |
159 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
160 MX28_PAD_GPMI_D07__SSP1_D7 |
161 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
162 MX28_PAD_GPMI_RDY1__SSP1_CMD |
163 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
164 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
165 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
166 MX28_PAD_GPMI_WRN__SSP1_SCK |
167 (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
168 /* write protect */
169 MX28_PAD_GPMI_RESETN__GPIO_0_28 |
170 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
171 /* slot power enable */
172 MX28_PAD_PWM4__GPIO_3_29 |
173 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
174
175 /* led */
176 MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
177 MX28_PAD_PWM1__GPIO_3_17 | MXS_PAD_CTRL,
178
179 /* nand */
180 MX28_PAD_GPMI_D00__GPMI_D0 |
181 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
182 MX28_PAD_GPMI_D01__GPMI_D1 |
183 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
184 MX28_PAD_GPMI_D02__GPMI_D2 |
185 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
186 MX28_PAD_GPMI_D03__GPMI_D3 |
187 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
188 MX28_PAD_GPMI_D04__GPMI_D4 |
189 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
190 MX28_PAD_GPMI_D05__GPMI_D5 |
191 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
192 MX28_PAD_GPMI_D06__GPMI_D6 |
193 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
194 MX28_PAD_GPMI_D07__GPMI_D7 |
195 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
196 MX28_PAD_GPMI_CE0N__GPMI_CE0N |
197 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
198 MX28_PAD_GPMI_RDY0__GPMI_READY0 |
199 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
200 MX28_PAD_GPMI_RDN__GPMI_RDN |
201 (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
202 MX28_PAD_GPMI_WRN__GPMI_WRN |
203 (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
204 MX28_PAD_GPMI_ALE__GPMI_ALE |
205 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
206 MX28_PAD_GPMI_CLE__GPMI_CLE |
207 (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
208 MX28_PAD_GPMI_RESETN__GPMI_RESETN |
209 (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
210
211 /* Backlight */
212 MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL,
213};
214
215/* led */
216static const struct gpio_led m28evk_leds[] __initconst = {
217 {
218 .name = "user-led1",
219 .default_trigger = "heartbeat",
220 .gpio = M28EVK_GPIO_USERLED1,
221 },
222 {
223 .name = "user-led2",
224 .default_trigger = "heartbeat",
225 .gpio = M28EVK_GPIO_USERLED2,
226 },
227};
228
229static const struct gpio_led_platform_data m28evk_led_data __initconst = {
230 .leds = m28evk_leds,
231 .num_leds = ARRAY_SIZE(m28evk_leds),
232};
233
234static struct fec_platform_data mx28_fec_pdata[] __initdata = {
235 {
236 /* fec0 */
237 .phy = PHY_INTERFACE_MODE_RMII,
238 }, {
239 /* fec1 */
240 .phy = PHY_INTERFACE_MODE_RMII,
241 },
242};
243
244static int __init m28evk_fec_get_mac(void)
245{
246 int i;
247 u32 val;
248 const u32 *ocotp = mxs_get_ocotp();
249
250 if (!ocotp) {
251 pr_err("%s: timeout when reading fec mac from OCOTP\n",
252 __func__);
253 return -ETIMEDOUT;
254 }
255
256 /*
257 * OCOTP only stores the last 4 octets for each mac address,
258 * so hard-code DENX OUI (C0:E5:4E) here.
259 */
260 for (i = 0; i < 2; i++) {
261 val = ocotp[i * 4];
262 mx28_fec_pdata[i].mac[0] = 0xC0;
263 mx28_fec_pdata[i].mac[1] = 0xE5;
264 mx28_fec_pdata[i].mac[2] = 0x4E;
265 mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
266 mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
267 mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
268 }
269
270 return 0;
271}
272
273/* mxsfb (lcdif) */
274static struct fb_videomode m28evk_video_modes[] = {
275 {
276 .name = "Ampire AM-800480R2TMQW-T01H",
277 .refresh = 60,
278 .xres = 800,
279 .yres = 480,
280 .pixclock = 30066, /* picosecond (33.26 MHz) */
281 .left_margin = 0,
282 .right_margin = 256,
283 .upper_margin = 0,
284 .lower_margin = 45,
285 .hsync_len = 1,
286 .vsync_len = 1,
287 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
288 },
289};
290
291static const struct mxsfb_platform_data m28evk_mxsfb_pdata __initconst = {
292 .mode_list = m28evk_video_modes,
293 .mode_count = ARRAY_SIZE(m28evk_video_modes),
294 .default_bpp = 16,
295 .ld_intf_width = STMLCDIF_18BIT,
296};
297
298static struct at24_platform_data m28evk_eeprom = {
299 .byte_len = 16384,
300 .page_size = 32,
301 .flags = AT24_FLAG_ADDR16,
302};
303
304static struct i2c_board_info m28_stk5v3_i2c_boardinfo[] __initdata = {
305 {
306 I2C_BOARD_INFO("at24", 0x51), /* E0=1, E1=0, E2=0 */
307 .platform_data = &m28evk_eeprom,
308 },
309};
310
311static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = {
312 {
313 /* mmc0 */
314 .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT,
315 .flags = SLOTF_8_BIT_CAPABLE,
316 }, {
317 /* mmc1 */
318 .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT,
319 .flags = SLOTF_8_BIT_CAPABLE,
320 },
321};
322
323static void __init m28evk_init(void)
324{
325 mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
326
327 mx28_add_duart();
328 mx28_add_auart0();
329 mx28_add_auart3();
330
331 if (!m28evk_fec_get_mac()) {
332 mx28_add_fec(0, &mx28_fec_pdata[0]);
333 mx28_add_fec(1, &mx28_fec_pdata[1]);
334 }
335
336 mx28_add_flexcan(0, NULL);
337 mx28_add_flexcan(1, NULL);
338
339 mx28_add_mxsfb(&m28evk_mxsfb_pdata);
340
341 mx28_add_mxs_mmc(0, &m28evk_mmc_pdata[0]);
342 mx28_add_mxs_mmc(1, &m28evk_mmc_pdata[1]);
343
344 gpio_led_register_device(0, &m28evk_led_data);
345
346 /* I2C */
347 mx28_add_mxs_i2c(0);
348 i2c_register_board_info(0, m28_stk5v3_i2c_boardinfo,
349 ARRAY_SIZE(m28_stk5v3_i2c_boardinfo));
350}
351
352static void __init m28evk_timer_init(void)
353{
354 mx28_clocks_init();
355}
356
357static struct sys_timer m28evk_timer = {
358 .init = m28evk_timer_init,
359};
360
361MACHINE_START(M28EVK, "DENX M28 EVK")
362 .map_io = mx28_map_io,
363 .init_irq = mx28_init_irq,
364 .init_machine = m28evk_init,
365 .timer = &m28evk_timer,
366MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/cpu.c b/arch/arm/mach-s3c64xx/cpu.c
index 8dc05763a7eb..c7047838e112 100644
--- a/arch/arm/mach-s3c64xx/cpu.c
+++ b/arch/arm/mach-s3c64xx/cpu.c
@@ -44,16 +44,16 @@ static const char name_s3c6410[] = "S3C6410";
44 44
45static struct cpu_table cpu_ids[] __initdata = { 45static struct cpu_table cpu_ids[] __initdata = {
46 { 46 {
47 .idcode = 0x36400000, 47 .idcode = S3C6400_CPU_ID,
48 .idmask = 0xfffff000, 48 .idmask = S3C64XX_CPU_MASK,
49 .map_io = s3c6400_map_io, 49 .map_io = s3c6400_map_io,
50 .init_clocks = s3c6400_init_clocks, 50 .init_clocks = s3c6400_init_clocks,
51 .init_uarts = s3c6400_init_uarts, 51 .init_uarts = s3c6400_init_uarts,
52 .init = s3c6400_init, 52 .init = s3c6400_init,
53 .name = name_s3c6400, 53 .name = name_s3c6400,
54 }, { 54 }, {
55 .idcode = 0x36410100, 55 .idcode = S3C6410_CPU_ID,
56 .idmask = 0xffffff00, 56 .idmask = S3C64XX_CPU_MASK,
57 .map_io = s3c6410_map_io, 57 .map_io = s3c6410_map_io,
58 .init_clocks = s3c6410_init_clocks, 58 .init_clocks = s3c6410_init_clocks,
59 .init_uarts = s3c6410_init_uarts, 59 .init_uarts = s3c6410_init_uarts,
@@ -141,23 +141,15 @@ void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
141 141
142void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) 142void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
143{ 143{
144 unsigned long idcode;
145
146 /* initialise the io descriptors we need for initialisation */ 144 /* initialise the io descriptors we need for initialisation */
147 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); 145 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
148 iotable_init(mach_desc, size); 146 iotable_init(mach_desc, size);
149 init_consistent_dma_size(SZ_8M); 147 init_consistent_dma_size(SZ_8M);
150 148
151 idcode = __raw_readl(S3C_VA_SYS + 0x118); 149 /* detect cpu id */
152 if (!idcode) { 150 s3c64xx_init_cpu();
153 /* S3C6400 has the ID register in a different place,
154 * and needs a write before it can be read. */
155
156 __raw_writel(0x0, S3C_VA_SYS + 0xA1C);
157 idcode = __raw_readl(S3C_VA_SYS + 0xA1C);
158 }
159 151
160 s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); 152 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
161} 153}
162 154
163static __init int s3c64xx_sysdev_init(void) 155static __init int s3c64xx_sysdev_init(void)
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
index ac825e826326..1fd9c79c7dbc 100644
--- a/arch/arm/mach-s5p64x0/dev-spi.c
+++ b/arch/arm/mach-s5p64x0/dev-spi.c
@@ -21,6 +21,7 @@
21#include <mach/regs-clock.h> 21#include <mach/regs-clock.h>
22#include <mach/spi-clocks.h> 22#include <mach/spi-clocks.h>
23 23
24#include <plat/cpu.h>
24#include <plat/s3c64xx-spi.h> 25#include <plat/s3c64xx-spi.h>
25#include <plat/gpio-cfg.h> 26#include <plat/gpio-cfg.h>
26 27
@@ -185,11 +186,8 @@ struct platform_device s5p64x0_device_spi1 = {
185 186
186void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) 187void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
187{ 188{
188 unsigned int id;
189 struct s3c64xx_spi_info *pd; 189 struct s3c64xx_spi_info *pd;
190 190
191 id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
192
193 /* Reject invalid configuration */ 191 /* Reject invalid configuration */
194 if (!num_cs || src_clk_nr < 0 192 if (!num_cs || src_clk_nr < 0
195 || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) { 193 || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
@@ -199,7 +197,7 @@ void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
199 197
200 switch (cntrlr) { 198 switch (cntrlr) {
201 case 0: 199 case 0:
202 if (id == 0x50000) 200 if (soc_is_s5p6450())
203 pd = &s5p6450_spi0_pdata; 201 pd = &s5p6450_spi0_pdata;
204 else 202 else
205 pd = &s5p6440_spi0_pdata; 203 pd = &s5p6440_spi0_pdata;
@@ -207,7 +205,7 @@ void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
207 s5p64x0_device_spi0.dev.platform_data = pd; 205 s5p64x0_device_spi0.dev.platform_data = pd;
208 break; 206 break;
209 case 1: 207 case 1:
210 if (id == 0x50000) 208 if (soc_is_s5p6450())
211 pd = &s5p6450_spi1_pdata; 209 pd = &s5p6450_spi1_pdata;
212 else 210 else
213 pd = &s5p6440_spi1_pdata; 211 pd = &s5p6440_spi1_pdata;
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index d7ad944b3475..0e5b3e63e5b3 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -28,6 +28,7 @@
28#include <mach/irqs.h> 28#include <mach/irqs.h>
29#include <mach/regs-clock.h> 29#include <mach/regs-clock.h>
30 30
31#include <plat/cpu.h>
31#include <plat/devs.h> 32#include <plat/devs.h>
32#include <plat/s3c-pl330-pdata.h> 33#include <plat/s3c-pl330-pdata.h>
33 34
@@ -133,11 +134,7 @@ static struct platform_device s5p64x0_device_pdma = {
133 134
134static int __init s5p64x0_dma_init(void) 135static int __init s5p64x0_dma_init(void)
135{ 136{
136 unsigned int id; 137 if (soc_is_s5p6450())
137
138 id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
139
140 if (id == 0x50000)
141 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata; 138 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
142 else 139 else
143 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata; 140 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
diff --git a/arch/arm/mach-s5p64x0/gpiolib.c b/arch/arm/mach-s5p64x0/gpiolib.c
index e7fb3b004e77..700dac6c43f3 100644
--- a/arch/arm/mach-s5p64x0/gpiolib.c
+++ b/arch/arm/mach-s5p64x0/gpiolib.c
@@ -19,6 +19,7 @@
19#include <mach/regs-gpio.h> 19#include <mach/regs-gpio.h>
20#include <mach/regs-clock.h> 20#include <mach/regs-clock.h>
21 21
22#include <plat/cpu.h>
22#include <plat/gpio-core.h> 23#include <plat/gpio-core.h>
23#include <plat/gpio-cfg.h> 24#include <plat/gpio-cfg.h>
24#include <plat/gpio-cfg-helpers.h> 25#include <plat/gpio-cfg-helpers.h>
@@ -473,14 +474,10 @@ static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
473 474
474static int __init s5p64x0_gpiolib_init(void) 475static int __init s5p64x0_gpiolib_init(void)
475{ 476{
476 unsigned int chipid;
477
478 chipid = __raw_readl(S5P64X0_SYS_ID);
479
480 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs, 477 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
481 ARRAY_SIZE(s5p64x0_gpio_cfgs)); 478 ARRAY_SIZE(s5p64x0_gpio_cfgs));
482 479
483 if ((chipid & 0xff000) == 0x50000) { 480 if (soc_is_s5p6450()) {
484 samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit, 481 samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit,
485 ARRAY_SIZE(s5p6450_gpio_2bit)); 482 ARRAY_SIZE(s5p6450_gpio_2bit));
486 483
diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c
index fe7380f5c3cd..494e1a8f6f6d 100644
--- a/arch/arm/mach-s5p64x0/irq-eint.c
+++ b/arch/arm/mach-s5p64x0/irq-eint.c
@@ -17,6 +17,7 @@
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <linux/io.h> 18#include <linux/io.h>
19 19
20#include <plat/cpu.h>
20#include <plat/regs-irqtype.h> 21#include <plat/regs-irqtype.h>
21#include <plat/gpio-cfg.h> 22#include <plat/gpio-cfg.h>
22 23
@@ -67,7 +68,7 @@ static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
67 __raw_writel(ctrl, S5P64X0_EINT0CON0); 68 __raw_writel(ctrl, S5P64X0_EINT0CON0);
68 69
69 /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */ 70 /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
70 if (0x50000 == (__raw_readl(S5P64X0_SYS_ID) & 0xFF000)) 71 if (soc_is_s5p6450())
71 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2)); 72 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
72 else 73 else
73 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2)); 74 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index 93c793f48caf..f0bdc5e3fe52 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -49,7 +49,8 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
49 .membase = IO_ADDRESS(TEGRA_UARTD_BASE), 49 .membase = IO_ADDRESS(TEGRA_UARTD_BASE),
50 .mapbase = TEGRA_UARTD_BASE, 50 .mapbase = TEGRA_UARTD_BASE,
51 .irq = INT_UARTD, 51 .irq = INT_UARTD,
52 .flags = UPF_BOOT_AUTOCONF, 52 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
53 .type = PORT_TEGRA,
53 .iotype = UPIO_MEM, 54 .iotype = UPIO_MEM,
54 .regshift = 2, 55 .regshift = 2,
55 .uartclk = 216000000, 56 .uartclk = 216000000,
@@ -117,6 +118,7 @@ static struct platform_device *harmony_devices[] __initdata = {
117 &tegra_sdhci_device1, 118 &tegra_sdhci_device1,
118 &tegra_sdhci_device2, 119 &tegra_sdhci_device2,
119 &tegra_sdhci_device4, 120 &tegra_sdhci_device4,
121 &tegra_ehci3_device,
120 &tegra_i2s_device1, 122 &tegra_i2s_device1,
121 &tegra_das_device, 123 &tegra_das_device,
122 &tegra_pcm_device, 124 &tegra_pcm_device,
@@ -140,6 +142,7 @@ static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = {
140 { "pll_a_out0", "pll_a", 11289600, true }, 142 { "pll_a_out0", "pll_a", 11289600, true },
141 { "cdev1", NULL, 0, true }, 143 { "cdev1", NULL, 0, true },
142 { "i2s1", "pll_a_out0", 11289600, false}, 144 { "i2s1", "pll_a_out0", 11289600, false},
145 { "usb3", "clk_m", 12000000, true },
143 { NULL, NULL, 0, 0}, 146 { NULL, NULL, 0, 0},
144}; 147};
145 148
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index bdd2627dd87b..22257697d3ee 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -145,6 +145,9 @@ static struct tegra_gpio_table gpio_table[] = {
145 { .gpio = TEGRA_GPIO_SD1_WP, .enable = true }, 145 { .gpio = TEGRA_GPIO_SD1_WP, .enable = true },
146 { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true }, 146 { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true },
147 { .gpio = TEGRA_ULPI_RST, .enable = true }, 147 { .gpio = TEGRA_ULPI_RST, .enable = true },
148 { .gpio = TEGRA_WIFI_PWRN, .enable = true },
149 { .gpio = TEGRA_WIFI_RST, .enable = true },
150 { .gpio = TEGRA_WIFI_LED, .enable = true },
148}; 151};
149 152
150void paz00_pinmux_init(void) 153void paz00_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index fbc9e0ed926e..55c55ba89f1e 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -26,6 +26,8 @@
26#include <linux/pda_power.h> 26#include <linux/pda_power.h>
27#include <linux/io.h> 27#include <linux/io.h>
28#include <linux/i2c.h> 28#include <linux/i2c.h>
29#include <linux/gpio.h>
30#include <linux/rfkill-gpio.h>
29 31
30#include <asm/mach-types.h> 32#include <asm/mach-types.h>
31#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
@@ -35,7 +37,6 @@
35#include <mach/iomap.h> 37#include <mach/iomap.h>
36#include <mach/irqs.h> 38#include <mach/irqs.h>
37#include <mach/sdhci.h> 39#include <mach/sdhci.h>
38#include <mach/gpio.h>
39 40
40#include "board.h" 41#include "board.h"
41#include "board-paz00.h" 42#include "board-paz00.h"
@@ -45,10 +46,22 @@
45 46
46static struct plat_serial8250_port debug_uart_platform_data[] = { 47static struct plat_serial8250_port debug_uart_platform_data[] = {
47 { 48 {
49 /* serial port on JP1 */
50 .membase = IO_ADDRESS(TEGRA_UARTA_BASE),
51 .mapbase = TEGRA_UARTA_BASE,
52 .irq = INT_UARTA,
53 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
54 .type = PORT_TEGRA,
55 .iotype = UPIO_MEM,
56 .regshift = 2,
57 .uartclk = 216000000,
58 }, {
59 /* serial port on mini-pcie */
48 .membase = IO_ADDRESS(TEGRA_UARTD_BASE), 60 .membase = IO_ADDRESS(TEGRA_UARTD_BASE),
49 .mapbase = TEGRA_UARTD_BASE, 61 .mapbase = TEGRA_UARTD_BASE,
50 .irq = INT_UARTD, 62 .irq = INT_UARTD,
51 .flags = UPF_BOOT_AUTOCONF, 63 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
64 .type = PORT_TEGRA,
52 .iotype = UPIO_MEM, 65 .iotype = UPIO_MEM,
53 .regshift = 2, 66 .regshift = 2,
54 .uartclk = 216000000, 67 .uartclk = 216000000,
@@ -65,10 +78,48 @@ static struct platform_device debug_uart = {
65 }, 78 },
66}; 79};
67 80
81static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = {
82 .name = "wifi_rfkill",
83 .reset_gpio = TEGRA_WIFI_RST,
84 .shutdown_gpio = TEGRA_WIFI_PWRN,
85 .type = RFKILL_TYPE_WLAN,
86};
87
88static struct platform_device wifi_rfkill_device = {
89 .name = "rfkill_gpio",
90 .id = -1,
91 .dev = {
92 .platform_data = &wifi_rfkill_platform_data,
93 },
94};
95
96static struct gpio_led gpio_leds[] = {
97 {
98 .name = "wifi-led",
99 .default_trigger = "rfkill0",
100 .gpio = TEGRA_WIFI_LED,
101 },
102};
103
104static struct gpio_led_platform_data gpio_led_info = {
105 .leds = gpio_leds,
106 .num_leds = ARRAY_SIZE(gpio_leds),
107};
108
109static struct platform_device leds_gpio = {
110 .name = "leds-gpio",
111 .id = -1,
112 .dev = {
113 .platform_data = &gpio_led_info,
114 },
115};
116
68static struct platform_device *paz00_devices[] __initdata = { 117static struct platform_device *paz00_devices[] __initdata = {
69 &debug_uart, 118 &debug_uart,
70 &tegra_sdhci_device1,
71 &tegra_sdhci_device4, 119 &tegra_sdhci_device4,
120 &tegra_sdhci_device1,
121 &wifi_rfkill_device,
122 &leds_gpio,
72}; 123};
73 124
74static void paz00_i2c_init(void) 125static void paz00_i2c_init(void)
@@ -94,7 +145,14 @@ static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline,
94 145
95static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { 146static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
96 /* name parent rate enabled */ 147 /* name parent rate enabled */
148 { "uarta", "pll_p", 216000000, true },
97 { "uartd", "pll_p", 216000000, true }, 149 { "uartd", "pll_p", 216000000, true },
150
151 { "pll_p_out4", "pll_p", 24000000, true },
152 { "usbd", "clk_m", 12000000, false },
153 { "usb2", "clk_m", 12000000, false },
154 { "usb3", "clk_m", 12000000, false },
155
98 { NULL, NULL, 0, 0}, 156 { NULL, NULL, 0, 0},
99}; 157};
100 158
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
index 42ce8639b90c..8aff06eb58c3 100644
--- a/arch/arm/mach-tegra/board-paz00.h
+++ b/arch/arm/mach-tegra/board-paz00.h
@@ -19,11 +19,19 @@
19 19
20#include <mach/gpio-tegra.h> 20#include <mach/gpio-tegra.h>
21 21
22/* SDCARD */
22#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5 23#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5
23#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1 24#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1
24#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PT3 25#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PT3
26
27/* ULPI */
25#define TEGRA_ULPI_RST TEGRA_GPIO_PV0 28#define TEGRA_ULPI_RST TEGRA_GPIO_PV0
26 29
30/* WIFI */
31#define TEGRA_WIFI_PWRN TEGRA_GPIO_PK5
32#define TEGRA_WIFI_RST TEGRA_GPIO_PD1
33#define TEGRA_WIFI_LED TEGRA_GPIO_PD0
34
27void paz00_pinmux_init(void); 35void paz00_pinmux_init(void);
28 36
29#endif 37#endif
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index 0bda495e9742..74f78b7e3f19 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -49,7 +49,7 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
49 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 49 {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
50 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 50 {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
51 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 51 {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
52 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 52 {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
53 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 53 {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
54 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 54 {TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
55 {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 55 {TEGRA_PINGROUP_DDC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
@@ -133,7 +133,7 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
133 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, 133 {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
134 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, 134 {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
135 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 135 {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
136 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 136 {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
137 {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 137 {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
138 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, 138 {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
139 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, 139 {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
@@ -167,6 +167,8 @@ static struct tegra_gpio_table gpio_table[] = {
167 { .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true }, 167 { .gpio = TEGRA_GPIO_LIDSWITCH, .enable = true },
168 { .gpio = TEGRA_GPIO_POWERKEY, .enable = true }, 168 { .gpio = TEGRA_GPIO_POWERKEY, .enable = true },
169 { .gpio = TEGRA_GPIO_ISL29018_IRQ, .enable = true }, 169 { .gpio = TEGRA_GPIO_ISL29018_IRQ, .enable = true },
170 { .gpio = TEGRA_GPIO_CDC_IRQ, .enable = true },
171 { .gpio = TEGRA_GPIO_USB1, .enable = true },
170}; 172};
171 173
172void __init seaboard_pinmux_init(void) 174void __init seaboard_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index 9e98ac706f40..bf13ea355efc 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -25,9 +25,12 @@
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <linux/gpio_keys.h> 26#include <linux/gpio_keys.h>
27 27
28#include <sound/wm8903.h>
29
28#include <mach/iomap.h> 30#include <mach/iomap.h>
29#include <mach/irqs.h> 31#include <mach/irqs.h>
30#include <mach/sdhci.h> 32#include <mach/sdhci.h>
33#include <mach/tegra_wm8903_pdata.h>
31 34
32#include <asm/mach-types.h> 35#include <asm/mach-types.h>
33#include <asm/mach/arch.h> 36#include <asm/mach/arch.h>
@@ -41,7 +44,8 @@
41static struct plat_serial8250_port debug_uart_platform_data[] = { 44static struct plat_serial8250_port debug_uart_platform_data[] = {
42 { 45 {
43 /* Memory and IRQ filled in before registration */ 46 /* Memory and IRQ filled in before registration */
44 .flags = UPF_BOOT_AUTOCONF, 47 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
48 .type = PORT_TEGRA,
45 .iotype = UPIO_MEM, 49 .iotype = UPIO_MEM,
46 .regshift = 2, 50 .regshift = 2,
47 .uartclk = 216000000, 51 .uartclk = 216000000,
@@ -62,6 +66,12 @@ static __initdata struct tegra_clk_init_table seaboard_clk_init_table[] = {
62 /* name parent rate enabled */ 66 /* name parent rate enabled */
63 { "uartb", "pll_p", 216000000, true}, 67 { "uartb", "pll_p", 216000000, true},
64 { "uartd", "pll_p", 216000000, true}, 68 { "uartd", "pll_p", 216000000, true},
69 { "pll_a", "pll_p_out1", 56448000, true },
70 { "pll_a_out0", "pll_a", 11289600, true },
71 { "cdev1", NULL, 0, true },
72 { "i2s1", "pll_a_out0", 11289600, false},
73 { "usbd", "clk_m", 12000000, true},
74 { "usb3", "clk_m", 12000000, true},
65 { NULL, NULL, 0, 0}, 75 { NULL, NULL, 0, 0},
66}; 76};
67 77
@@ -117,6 +127,22 @@ static struct tegra_sdhci_platform_data sdhci_pdata4 = {
117 .is_8bit = 1, 127 .is_8bit = 1,
118}; 128};
119 129
130static struct tegra_wm8903_platform_data seaboard_audio_pdata = {
131 .gpio_spkr_en = TEGRA_GPIO_SPKR_EN,
132 .gpio_hp_det = TEGRA_GPIO_HP_DET,
133 .gpio_hp_mute = -1,
134 .gpio_int_mic_en = -1,
135 .gpio_ext_mic_en = -1,
136};
137
138static struct platform_device seaboard_audio_device = {
139 .name = "tegra-snd-wm8903",
140 .id = 0,
141 .dev = {
142 .platform_data = &seaboard_audio_pdata,
143 },
144};
145
120static struct platform_device *seaboard_devices[] __initdata = { 146static struct platform_device *seaboard_devices[] __initdata = {
121 &debug_uart, 147 &debug_uart,
122 &tegra_pmu_device, 148 &tegra_pmu_device,
@@ -124,6 +150,10 @@ static struct platform_device *seaboard_devices[] __initdata = {
124 &tegra_sdhci_device3, 150 &tegra_sdhci_device3,
125 &tegra_sdhci_device1, 151 &tegra_sdhci_device1,
126 &seaboard_gpio_keys_device, 152 &seaboard_gpio_keys_device,
153 &tegra_i2s_device1,
154 &tegra_das_device,
155 &tegra_pcm_device,
156 &seaboard_audio_device,
127}; 157};
128 158
129static struct i2c_board_info __initdata isl29018_device = { 159static struct i2c_board_info __initdata isl29018_device = {
@@ -135,12 +165,56 @@ static struct i2c_board_info __initdata adt7461_device = {
135 I2C_BOARD_INFO("adt7461", 0x4c), 165 I2C_BOARD_INFO("adt7461", 0x4c),
136}; 166};
137 167
168static struct wm8903_platform_data wm8903_pdata = {
169 .irq_active_low = 0,
170 .micdet_cfg = 0,
171 .micdet_delay = 100,
172 .gpio_base = SEABOARD_GPIO_WM8903(0),
173 .gpio_cfg = {
174 WM8903_GPIO_NO_CONFIG,
175 WM8903_GPIO_NO_CONFIG,
176 0,
177 WM8903_GPIO_NO_CONFIG,
178 WM8903_GPIO_NO_CONFIG,
179 },
180};
181
182static struct i2c_board_info __initdata wm8903_device = {
183 I2C_BOARD_INFO("wm8903", 0x1a),
184 .platform_data = &wm8903_pdata,
185 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
186};
187
188static int seaboard_ehci_init(void)
189{
190 int gpio_status;
191
192 gpio_status = gpio_request(TEGRA_GPIO_USB1, "VBUS_USB1");
193 if (gpio_status < 0) {
194 pr_err("VBUS_USB1 request GPIO FAILED\n");
195 WARN_ON(1);
196 }
197
198 gpio_status = gpio_direction_output(TEGRA_GPIO_USB1, 1);
199 if (gpio_status < 0) {
200 pr_err("VBUS_USB1 request GPIO DIRECTION FAILED\n");
201 WARN_ON(1);
202 }
203 gpio_set_value(TEGRA_GPIO_USB1, 1);
204
205 platform_device_register(&tegra_ehci1_device);
206 platform_device_register(&tegra_ehci3_device);
207
208 return 0;
209}
210
138static void __init seaboard_i2c_init(void) 211static void __init seaboard_i2c_init(void)
139{ 212{
140 gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018"); 213 gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018");
141 gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ); 214 gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ);
142 215
143 i2c_register_board_info(0, &isl29018_device, 1); 216 i2c_register_board_info(0, &isl29018_device, 1);
217 i2c_register_board_info(0, &wm8903_device, 1);
144 218
145 i2c_register_board_info(3, &adt7461_device, 1); 219 i2c_register_board_info(3, &adt7461_device, 1);
146 220
@@ -161,6 +235,8 @@ static void __init seaboard_common_init(void)
161 tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4; 235 tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
162 236
163 platform_add_devices(seaboard_devices, ARRAY_SIZE(seaboard_devices)); 237 platform_add_devices(seaboard_devices, ARRAY_SIZE(seaboard_devices));
238
239 seaboard_ehci_init();
164} 240}
165 241
166static void __init tegra_seaboard_init(void) 242static void __init tegra_seaboard_init(void)
@@ -182,6 +258,9 @@ static void __init tegra_kaen_init(void)
182 debug_uart_platform_data[0].mapbase = TEGRA_UARTB_BASE; 258 debug_uart_platform_data[0].mapbase = TEGRA_UARTB_BASE;
183 debug_uart_platform_data[0].irq = INT_UARTB; 259 debug_uart_platform_data[0].irq = INT_UARTB;
184 260
261 seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE;
262 tegra_gpio_enable(TEGRA_GPIO_KAEN_HP_MUTE);
263
185 seaboard_common_init(); 264 seaboard_common_init();
186 265
187 seaboard_i2c_init(); 266 seaboard_i2c_init();
diff --git a/arch/arm/mach-tegra/board-seaboard.h b/arch/arm/mach-tegra/board-seaboard.h
index 15b6c57361be..4c45d4ca3c49 100644
--- a/arch/arm/mach-tegra/board-seaboard.h
+++ b/arch/arm/mach-tegra/board-seaboard.h
@@ -19,6 +19,9 @@
19 19
20#include <mach/gpio-tegra.h> 20#include <mach/gpio-tegra.h>
21 21
22#define SEABOARD_GPIO_TPS6586X(_x_) (TEGRA_NR_GPIOS + (_x_))
23#define SEABOARD_GPIO_WM8903(_x_) (SEABOARD_GPIO_TPS6586X(4) + (_x_))
24
22#define TEGRA_GPIO_SD2_CD TEGRA_GPIO_PI5 25#define TEGRA_GPIO_SD2_CD TEGRA_GPIO_PI5
23#define TEGRA_GPIO_SD2_WP TEGRA_GPIO_PH1 26#define TEGRA_GPIO_SD2_WP TEGRA_GPIO_PH1
24#define TEGRA_GPIO_SD2_POWER TEGRA_GPIO_PI6 27#define TEGRA_GPIO_SD2_POWER TEGRA_GPIO_PI6
@@ -33,10 +36,11 @@
33#define TEGRA_GPIO_MAGNETOMETER TEGRA_GPIO_PN5 36#define TEGRA_GPIO_MAGNETOMETER TEGRA_GPIO_PN5
34#define TEGRA_GPIO_ISL29018_IRQ TEGRA_GPIO_PZ2 37#define TEGRA_GPIO_ISL29018_IRQ TEGRA_GPIO_PZ2
35#define TEGRA_GPIO_AC_ONLINE TEGRA_GPIO_PV3 38#define TEGRA_GPIO_AC_ONLINE TEGRA_GPIO_PV3
36 39#define TEGRA_GPIO_WWAN_PWR SEABOARD_GPIO_TPS6586X(2)
37#define TPS_GPIO_BASE TEGRA_NR_GPIOS 40#define TEGRA_GPIO_CDC_IRQ TEGRA_GPIO_PX3
38 41#define TEGRA_GPIO_SPKR_EN SEABOARD_GPIO_WM8903(2)
39#define TPS_GPIO_WWAN_PWR (TPS_GPIO_BASE + 2) 42#define TEGRA_GPIO_HP_DET TEGRA_GPIO_PX1
43#define TEGRA_GPIO_KAEN_HP_MUTE TEGRA_GPIO_PA5
40 44
41void seaboard_pinmux_init(void); 45void seaboard_pinmux_init(void);
42 46
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index e3d9ec2f0fe1..1a6617b7806f 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -32,7 +32,6 @@
32 32
33#include <mach/iomap.h> 33#include <mach/iomap.h>
34#include <mach/sdhci.h> 34#include <mach/sdhci.h>
35#include <mach/gpio.h>
36 35
37#include "board.h" 36#include "board.h"
38#include "clock.h" 37#include "clock.h"
@@ -46,7 +45,8 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
46 .membase = IO_ADDRESS(TEGRA_UARTA_BASE), 45 .membase = IO_ADDRESS(TEGRA_UARTA_BASE),
47 .mapbase = TEGRA_UARTA_BASE, 46 .mapbase = TEGRA_UARTA_BASE,
48 .irq = INT_UARTA, 47 .irq = INT_UARTA,
49 .flags = UPF_BOOT_AUTOCONF, 48 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
49 .type = PORT_TEGRA,
50 .iotype = UPIO_MEM, 50 .iotype = UPIO_MEM,
51 .regshift = 2, 51 .regshift = 2,
52 .uartclk = 216000000, 52 .uartclk = 216000000,
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index c1fc6c6fac72..3c6335307fb1 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -215,19 +215,18 @@ static void s3c24xx_pm_restart(char mode, const char *cmd)
215 215
216void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) 216void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
217{ 217{
218 unsigned long idcode = 0x0;
219
220 /* initialise the io descriptors we need for initialisation */ 218 /* initialise the io descriptors we need for initialisation */
221 iotable_init(mach_desc, size); 219 iotable_init(mach_desc, size);
222 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); 220 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
223 221
224 if (cpu_architecture() >= CPU_ARCH_ARMv5) { 222 if (cpu_architecture() >= CPU_ARCH_ARMv5) {
225 idcode = s3c24xx_read_idcode_v5(); 223 samsung_cpu_id = s3c24xx_read_idcode_v5();
226 } else { 224 } else {
227 idcode = s3c24xx_read_idcode_v4(); 225 samsung_cpu_id = s3c24xx_read_idcode_v4();
228 } 226 }
227 s3c24xx_init_cpu();
229 228
230 arm_pm_restart = s3c24xx_pm_restart; 229 arm_pm_restart = s3c24xx_pm_restart;
231 230
232 s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); 231 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
233} 232}
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index bbc2aa7449ca..7b0a28f73a68 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -33,48 +33,66 @@ static const char name_s5p6450[] = "S5P6450";
33static const char name_s5pc100[] = "S5PC100"; 33static const char name_s5pc100[] = "S5PC100";
34static const char name_s5pv210[] = "S5PV210/S5PC110"; 34static const char name_s5pv210[] = "S5PV210/S5PC110";
35static const char name_exynos4210[] = "EXYNOS4210"; 35static const char name_exynos4210[] = "EXYNOS4210";
36static const char name_exynos4212[] = "EXYNOS4212";
37static const char name_exynos4412[] = "EXYNOS4412";
36 38
37static struct cpu_table cpu_ids[] __initdata = { 39static struct cpu_table cpu_ids[] __initdata = {
38 { 40 {
39 .idcode = 0x56440100, 41 .idcode = S5P6440_CPU_ID,
40 .idmask = 0xfffff000, 42 .idmask = S5P64XX_CPU_MASK,
41 .map_io = s5p6440_map_io, 43 .map_io = s5p6440_map_io,
42 .init_clocks = s5p6440_init_clocks, 44 .init_clocks = s5p6440_init_clocks,
43 .init_uarts = s5p6440_init_uarts, 45 .init_uarts = s5p6440_init_uarts,
44 .init = s5p64x0_init, 46 .init = s5p64x0_init,
45 .name = name_s5p6440, 47 .name = name_s5p6440,
46 }, { 48 }, {
47 .idcode = 0x36450000, 49 .idcode = S5P6450_CPU_ID,
48 .idmask = 0xfffff000, 50 .idmask = S5P64XX_CPU_MASK,
49 .map_io = s5p6450_map_io, 51 .map_io = s5p6450_map_io,
50 .init_clocks = s5p6450_init_clocks, 52 .init_clocks = s5p6450_init_clocks,
51 .init_uarts = s5p6450_init_uarts, 53 .init_uarts = s5p6450_init_uarts,
52 .init = s5p64x0_init, 54 .init = s5p64x0_init,
53 .name = name_s5p6450, 55 .name = name_s5p6450,
54 }, { 56 }, {
55 .idcode = 0x43100000, 57 .idcode = S5PC100_CPU_ID,
56 .idmask = 0xfffff000, 58 .idmask = S5PC100_CPU_MASK,
57 .map_io = s5pc100_map_io, 59 .map_io = s5pc100_map_io,
58 .init_clocks = s5pc100_init_clocks, 60 .init_clocks = s5pc100_init_clocks,
59 .init_uarts = s5pc100_init_uarts, 61 .init_uarts = s5pc100_init_uarts,
60 .init = s5pc100_init, 62 .init = s5pc100_init,
61 .name = name_s5pc100, 63 .name = name_s5pc100,
62 }, { 64 }, {
63 .idcode = 0x43110000, 65 .idcode = S5PV210_CPU_ID,
64 .idmask = 0xfffff000, 66 .idmask = S5PV210_CPU_MASK,
65 .map_io = s5pv210_map_io, 67 .map_io = s5pv210_map_io,
66 .init_clocks = s5pv210_init_clocks, 68 .init_clocks = s5pv210_init_clocks,
67 .init_uarts = s5pv210_init_uarts, 69 .init_uarts = s5pv210_init_uarts,
68 .init = s5pv210_init, 70 .init = s5pv210_init,
69 .name = name_s5pv210, 71 .name = name_s5pv210,
70 }, { 72 }, {
71 .idcode = 0x43210000, 73 .idcode = EXYNOS4210_CPU_ID,
72 .idmask = 0xfffe0000, 74 .idmask = EXYNOS4_CPU_MASK,
73 .map_io = exynos4_map_io, 75 .map_io = exynos4_map_io,
74 .init_clocks = exynos4_init_clocks, 76 .init_clocks = exynos4_init_clocks,
75 .init_uarts = exynos4_init_uarts, 77 .init_uarts = exynos4_init_uarts,
76 .init = exynos4_init, 78 .init = exynos4_init,
77 .name = name_exynos4210, 79 .name = name_exynos4210,
80 }, {
81 .idcode = EXYNOS4212_CPU_ID,
82 .idmask = EXYNOS4_CPU_MASK,
83 .map_io = exynos4_map_io,
84 .init_clocks = exynos4_init_clocks,
85 .init_uarts = exynos4_init_uarts,
86 .init = exynos4_init,
87 .name = name_exynos4212,
88 }, {
89 .idcode = EXYNOS4412_CPU_ID,
90 .idmask = EXYNOS4_CPU_MASK,
91 .map_io = exynos4_map_io,
92 .init_clocks = exynos4_init_clocks,
93 .init_uarts = exynos4_init_uarts,
94 .init = exynos4_init,
95 .name = name_exynos4412,
78 }, 96 },
79}; 97};
80 98
@@ -114,13 +132,13 @@ static struct map_desc s5p_iodesc[] __initdata = {
114void __init s5p_init_io(struct map_desc *mach_desc, 132void __init s5p_init_io(struct map_desc *mach_desc,
115 int size, void __iomem *cpuid_addr) 133 int size, void __iomem *cpuid_addr)
116{ 134{
117 unsigned long idcode;
118
119 /* initialize the io descriptors we need for initialization */ 135 /* initialize the io descriptors we need for initialization */
120 iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc)); 136 iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc));
121 if (mach_desc) 137 if (mach_desc)
122 iotable_init(mach_desc, size); 138 iotable_init(mach_desc, size);
123 139
124 idcode = __raw_readl(cpuid_addr); 140 /* detect cpu id and rev. */
125 s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); 141 s5p_init_cpu(cpuid_addr);
142
143 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
126} 144}
diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-s5p/include/plat/exynos4.h
index 907caab53dcf..f680a143e38c 100644
--- a/arch/arm/plat-s5p/include/plat/exynos4.h
+++ b/arch/arm/plat-s5p/include/plat/exynos4.h
@@ -14,10 +14,11 @@
14 14
15extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); 15extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void exynos4_register_clocks(void); 16extern void exynos4_register_clocks(void);
17extern void exynos4210_register_clocks(void);
18extern void exynos4212_register_clocks(void);
17extern void exynos4_setup_clocks(void); 19extern void exynos4_setup_clocks(void);
18 20
19#ifdef CONFIG_CPU_EXYNOS4210 21#ifdef CONFIG_ARCH_EXYNOS4
20
21extern int exynos4_init(void); 22extern int exynos4_init(void);
22extern void exynos4_init_irq(void); 23extern void exynos4_init_irq(void);
23extern void exynos4_map_io(void); 24extern void exynos4_map_io(void);
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h
index ebc142c5c84c..3e21b9444cc5 100644
--- a/arch/arm/plat-s5p/include/plat/pll.h
+++ b/arch/arm/plat-s5p/include/plat/pll.h
@@ -12,6 +12,59 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13*/ 13*/
14 14
15#include <asm/div64.h>
16
17#define PLL35XX_MDIV_MASK (0x3FF)
18#define PLL35XX_PDIV_MASK (0x3F)
19#define PLL35XX_SDIV_MASK (0x7)
20#define PLL35XX_MDIV_SHIFT (16)
21#define PLL35XX_PDIV_SHIFT (8)
22#define PLL35XX_SDIV_SHIFT (0)
23
24static inline unsigned long s5p_get_pll35xx(unsigned long baseclk, u32 pll_con)
25{
26 u32 mdiv, pdiv, sdiv;
27 u64 fvco = baseclk;
28
29 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
30 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
31 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
32
33 fvco *= mdiv;
34 do_div(fvco, (pdiv << sdiv));
35
36 return (unsigned long)fvco;
37}
38
39#define PLL36XX_KDIV_MASK (0xFFFF)
40#define PLL36XX_MDIV_MASK (0x1FF)
41#define PLL36XX_PDIV_MASK (0x3F)
42#define PLL36XX_SDIV_MASK (0x7)
43#define PLL36XX_MDIV_SHIFT (16)
44#define PLL36XX_PDIV_SHIFT (8)
45#define PLL36XX_SDIV_SHIFT (0)
46
47static inline unsigned long s5p_get_pll36xx(unsigned long baseclk,
48 u32 pll_con0, u32 pll_con1)
49{
50 unsigned long result;
51 u32 mdiv, pdiv, sdiv, kdiv;
52 u64 tmp;
53
54 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
55 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
56 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
57 kdiv = pll_con1 & PLL36XX_KDIV_MASK;
58
59 tmp = baseclk;
60
61 tmp *= (mdiv << 16) + kdiv;
62 do_div(tmp, (pdiv << sdiv));
63 result = tmp >> 16;
64
65 return result;
66}
67
15#define PLL45XX_MDIV_MASK (0x3FF) 68#define PLL45XX_MDIV_MASK (0x3FF)
16#define PLL45XX_PDIV_MASK (0x3F) 69#define PLL45XX_PDIV_MASK (0x3F)
17#define PLL45XX_SDIV_MASK (0x7) 70#define PLL45XX_SDIV_MASK (0x7)
@@ -19,8 +72,6 @@
19#define PLL45XX_PDIV_SHIFT (8) 72#define PLL45XX_PDIV_SHIFT (8)
20#define PLL45XX_SDIV_SHIFT (0) 73#define PLL45XX_SDIV_SHIFT (0)
21 74
22#include <asm/div64.h>
23
24enum pll45xx_type_t { 75enum pll45xx_type_t {
25 pll_4500, 76 pll_4500,
26 pll_4502, 77 pll_4502,
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 1105922342fe..09adb84f2718 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -11,7 +11,7 @@ obj- :=
11 11
12# Objects we always build independent of SoC choice 12# Objects we always build independent of SoC choice
13 13
14obj-y += init.o 14obj-y += init.o cpu.o
15obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o 15obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o
16obj-y += clock.o 16obj-y += clock.o
17obj-y += pwm-clock.o 17obj-y += pwm-clock.o
diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/plat-samsung/cpu.c
new file mode 100644
index 000000000000..81c06d44c11e
--- /dev/null
+++ b/arch/arm/plat-samsung/cpu.c
@@ -0,0 +1,58 @@
1/* linux/arch/arm/plat-samsung/cpu.c
2 *
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung CPU Support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/io.h>
17
18#include <asm/system.h>
19
20#include <mach/map.h>
21#include <plat/cpu.h>
22
23unsigned long samsung_cpu_id;
24static unsigned int samsung_cpu_rev;
25
26unsigned int samsung_rev(void)
27{
28 return samsung_cpu_rev;
29}
30EXPORT_SYMBOL(samsung_rev);
31
32void __init s3c24xx_init_cpu(void)
33{
34 /* nothing here yet */
35
36 samsung_cpu_rev = 0;
37}
38
39void __init s3c64xx_init_cpu(void)
40{
41 samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0x118);
42 if (!samsung_cpu_id) {
43 /*
44 * S3C6400 has the ID register in a different place,
45 * and needs a write before it can be read.
46 */
47 __raw_writel(0x0, S3C_VA_SYS + 0xA1C);
48 samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0xA1C);
49 }
50
51 samsung_cpu_rev = 0;
52}
53
54void __init s5p_init_cpu(void __iomem *cpuid_addr)
55{
56 samsung_cpu_id = __raw_readl(cpuid_addr);
57 samsung_cpu_rev = samsung_cpu_id & 0xFF;
58}
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index c0a5741b23e6..54f370f0fc07 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -1,9 +1,12 @@
1/* linux/arch/arm/plat-samsung/include/plat/cpu.h 1/* linux/arch/arm/plat-samsung/include/plat/cpu.h
2 * 2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
3 * Copyright (c) 2004-2005 Simtec Electronics 6 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 7 * Ben Dooks <ben@simtec.co.uk>
5 * 8 *
6 * Header file for S3C24XX CPU support 9 * Header file for Samsung CPU support
7 * 10 *
8 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
@@ -15,6 +18,108 @@
15#ifndef __SAMSUNG_PLAT_CPU_H 18#ifndef __SAMSUNG_PLAT_CPU_H
16#define __SAMSUNG_PLAT_CPU_H 19#define __SAMSUNG_PLAT_CPU_H
17 20
21extern unsigned long samsung_cpu_id;
22
23#define S3C24XX_CPU_ID 0x32400000
24#define S3C24XX_CPU_MASK 0xFFF00000
25
26#define S3C6400_CPU_ID 0x36400000
27#define S3C6410_CPU_ID 0x36410000
28#define S3C64XX_CPU_ID (S3C6400_CPU_ID & S3C6410_CPU_ID)
29#define S3C64XX_CPU_MASK 0xFFFFF000
30
31#define S5P6440_CPU_ID 0x56440000
32#define S5P6450_CPU_ID 0x36450000
33#define S5P64XX_CPU_MASK 0xFFFFF000
34
35#define S5PC100_CPU_ID 0x43100000
36#define S5PC100_CPU_MASK 0xFFFFF000
37
38#define S5PV210_CPU_ID 0x43110000
39#define S5PV210_CPU_MASK 0xFFFFF000
40
41#define EXYNOS4210_CPU_ID 0x43210000
42#define EXYNOS4212_CPU_ID 0x43220000
43#define EXYNOS4412_CPU_ID 0xE4412200
44#define EXYNOS4_CPU_MASK 0xFFFE0000
45
46#define IS_SAMSUNG_CPU(name, id, mask) \
47static inline int is_samsung_##name(void) \
48{ \
49 return ((samsung_cpu_id & mask) == (id & mask)); \
50}
51
52IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
53IS_SAMSUNG_CPU(s3c64xx, S3C64XX_CPU_ID, S3C64XX_CPU_MASK)
54IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
55IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
56IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
57IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
58IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
59IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
60IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
61
62#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
63 defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
64 defined(CONFIG_CPU_S3C2442) || defined(CONFIG_CPU_S3C244X) || \
65 defined(CONFIG_CPU_S3C2443)
66# define soc_is_s3c24xx() is_samsung_s3c24xx()
67#else
68# define soc_is_s3c24xx() 0
69#endif
70
71#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
72# define soc_is_s3c64xx() is_samsung_s3c64xx()
73#else
74# define soc_is_s3c64xx() 0
75#endif
76
77#if defined(CONFIG_CPU_S5P6440)
78# define soc_is_s5p6440() is_samsung_s5p6440()
79#else
80# define soc_is_s5p6440() 0
81#endif
82
83#if defined(CONFIG_CPU_S5P6450)
84# define soc_is_s5p6450() is_samsung_s5p6450()
85#else
86# define soc_is_s5p6450() 0
87#endif
88
89#if defined(CONFIG_CPU_S5PC100)
90# define soc_is_s5pc100() is_samsung_s5pc100()
91#else
92# define soc_is_s5pc100() 0
93#endif
94
95#if defined(CONFIG_CPU_S5PV210)
96# define soc_is_s5pv210() is_samsung_s5pv210()
97#else
98# define soc_is_s5pv210() 0
99#endif
100
101#if defined(CONFIG_CPU_EXYNOS4210)
102# define soc_is_exynos4210() is_samsung_exynos4210()
103#else
104# define soc_is_exynos4210() 0
105#endif
106
107#if defined(CONFIG_SOC_EXYNOS4212)
108# define soc_is_exynos4212() is_samsung_exynos4212()
109#else
110# define soc_is_exynos4212() 0
111#endif
112
113#if defined(CONFIG_SOC_EXYNOS4412)
114# define soc_is_exynos4412() is_samsung_exynos4412()
115#else
116# define soc_is_exynos4412() 0
117#endif
118
119#define EXYNOS4210_REV_0 (0x0)
120#define EXYNOS4210_REV_1_0 (0x10)
121#define EXYNOS4210_REV_1_1 (0x11)
122
18#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } 123#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
19 124
20#ifndef MHZ 125#ifndef MHZ
@@ -55,6 +160,12 @@ extern void s3c64xx_init_io(struct map_desc *mach_desc, int size);
55extern void s5p_init_io(struct map_desc *mach_desc, 160extern void s5p_init_io(struct map_desc *mach_desc,
56 int size, void __iomem *cpuid_addr); 161 int size, void __iomem *cpuid_addr);
57 162
163extern void s3c24xx_init_cpu(void);
164extern void s3c64xx_init_cpu(void);
165extern void s5p_init_cpu(void __iomem *cpuid_addr);
166
167extern unsigned int samsung_rev(void);
168
58extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); 169extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
59 170
60extern void s3c24xx_init_clocks(int xtal); 171extern void s3c24xx_init_clocks(int xtal);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 17:21:51 -0400