7 files changed, 564 insertions, 183 deletions

diff --git a/arch/arm/mach-exynos/include/mach/debug-macro.S b/arch/arm/mach-exynos/include/mach/debug-macro.S
index 6cacf16a67a6..6c857ff0b5d8 100644
--- a/arch/arm/mach-exynos/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos/include/mach/debug-macro.S
@@ -21,8 +21,13 @@
          */
 
         .macro addruart, rp, rv, tmp
-                ldr     \rp, = S3C_PA_UART
-                ldr     \rv, = S3C_VA_UART
+                mov     \rp, #0x10000000
+                ldr     \rp, [\rp, #0x0]
+                and     \rp, \rp, #0xf00000
+                teq     \rp, #0x500000          @@ EXYNOS5
+                ldreq   \rp, =EXYNOS5_PA_UART
+                movne   \rp, #EXYNOS4_PA_UART   @@ EXYNOS4
+                ldr     \rv, =S3C_VA_UART
 #if CONFIG_DEBUG_S3C_UART != 0
                 add     \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
                 add     \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 1d401c957835..9bee8535d9e0 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * EXYNOS4 - IRQ definitions
+ * EXYNOS - IRQ definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -17,160 +16,450 @@
 
 /* PPI: Private Peripheral Interrupt */
 
-#define IRQ_PPI(x)              (x+16)
-
-#define IRQ_MCT_LOCALTIMER      IRQ_PPI(12)
+#define IRQ_PPI(x)                      (x + 16)
 
 /* SPI: Shared Peripheral Interrupt */
 
-#define IRQ_SPI(x)              (x+32)
-
-#define IRQ_EINT0               IRQ_SPI(16)
-#define IRQ_EINT1               IRQ_SPI(17)
-#define IRQ_EINT2               IRQ_SPI(18)
-#define IRQ_EINT3               IRQ_SPI(19)
-#define IRQ_EINT4               IRQ_SPI(20)
-#define IRQ_EINT5               IRQ_SPI(21)
-#define IRQ_EINT6               IRQ_SPI(22)
-#define IRQ_EINT7               IRQ_SPI(23)
-#define IRQ_EINT8               IRQ_SPI(24)
-#define IRQ_EINT9               IRQ_SPI(25)
-#define IRQ_EINT10              IRQ_SPI(26)
-#define IRQ_EINT11              IRQ_SPI(27)
-#define IRQ_EINT12              IRQ_SPI(28)
-#define IRQ_EINT13              IRQ_SPI(29)
-#define IRQ_EINT14              IRQ_SPI(30)
-#define IRQ_EINT15              IRQ_SPI(31)
-#define IRQ_EINT16_31           IRQ_SPI(32)
-
-#define IRQ_MDMA0               IRQ_SPI(33)
-#define IRQ_MDMA1               IRQ_SPI(34)
-#define IRQ_PDMA0               IRQ_SPI(35)
-#define IRQ_PDMA1               IRQ_SPI(36)
-#define IRQ_TIMER0_VIC          IRQ_SPI(37)
-#define IRQ_TIMER1_VIC          IRQ_SPI(38)
-#define IRQ_TIMER2_VIC          IRQ_SPI(39)
-#define IRQ_TIMER3_VIC          IRQ_SPI(40)
-#define IRQ_TIMER4_VIC          IRQ_SPI(41)
-#define IRQ_MCT_L0              IRQ_SPI(42)
-#define IRQ_WDT                 IRQ_SPI(43)
-#define IRQ_RTC_ALARM           IRQ_SPI(44)
-#define IRQ_RTC_TIC             IRQ_SPI(45)
-#define IRQ_GPIO_XB             IRQ_SPI(46)
-#define IRQ_GPIO_XA             IRQ_SPI(47)
-#define IRQ_MCT_L1              IRQ_SPI(48)
-
-#define IRQ_UART0               IRQ_SPI(52)
-#define IRQ_UART1               IRQ_SPI(53)
-#define IRQ_UART2               IRQ_SPI(54)
-#define IRQ_UART3               IRQ_SPI(55)
-#define IRQ_UART4               IRQ_SPI(56)
-#define IRQ_MCT_G0              IRQ_SPI(57)
-#define IRQ_IIC                 IRQ_SPI(58)
-#define IRQ_IIC1                IRQ_SPI(59)
-#define IRQ_IIC2                IRQ_SPI(60)
-#define IRQ_IIC3                IRQ_SPI(61)
-#define IRQ_IIC4                IRQ_SPI(62)
-#define IRQ_IIC5                IRQ_SPI(63)
-#define IRQ_IIC6                IRQ_SPI(64)
-#define IRQ_IIC7                IRQ_SPI(65)
-#define IRQ_SPI0                IRQ_SPI(66)
-#define IRQ_SPI1                IRQ_SPI(67)
-#define IRQ_SPI2                IRQ_SPI(68)
-
-#define IRQ_USB_HOST            IRQ_SPI(70)
-#define IRQ_USB_HSOTG           IRQ_SPI(71)
-#define IRQ_MODEM_IF            IRQ_SPI(72)
-#define IRQ_HSMMC0              IRQ_SPI(73)
-#define IRQ_HSMMC1              IRQ_SPI(74)
-#define IRQ_HSMMC2              IRQ_SPI(75)
-#define IRQ_HSMMC3              IRQ_SPI(76)
-#define IRQ_DWMCI               IRQ_SPI(77)
-
-#define IRQ_MIPI_CSIS0          IRQ_SPI(78)
-#define IRQ_MIPI_CSIS1          IRQ_SPI(80)
-
-#define IRQ_ONENAND_AUDI        IRQ_SPI(82)
-#define IRQ_ROTATOR             IRQ_SPI(83)
-#define IRQ_FIMC0               IRQ_SPI(84)
-#define IRQ_FIMC1               IRQ_SPI(85)
-#define IRQ_FIMC2               IRQ_SPI(86)
-#define IRQ_FIMC3               IRQ_SPI(87)
-#define IRQ_JPEG                IRQ_SPI(88)
-#define IRQ_2D                  IRQ_SPI(89)
-#define IRQ_PCIE                IRQ_SPI(90)
-
-#define IRQ_MIXER               IRQ_SPI(91)
-#define IRQ_HDMI                IRQ_SPI(92)
-#define IRQ_IIC_HDMIPHY         IRQ_SPI(93)
-#define IRQ_MFC                 IRQ_SPI(94)
-#define IRQ_SDO                 IRQ_SPI(95)
-
-#define IRQ_AUDIO_SS            IRQ_SPI(96)
-#define IRQ_I2S0                IRQ_SPI(97)
-#define IRQ_I2S1                IRQ_SPI(98)
-#define IRQ_I2S2                IRQ_SPI(99)
-#define IRQ_AC97                IRQ_SPI(100)
-
-#define IRQ_SPDIF               IRQ_SPI(104)
-#define IRQ_ADC0                IRQ_SPI(105)
-#define IRQ_PEN0                IRQ_SPI(106)
-#define IRQ_ADC1                IRQ_SPI(107)
-#define IRQ_PEN1                IRQ_SPI(108)
-#define IRQ_KEYPAD              IRQ_SPI(109)
-#define IRQ_PMU                 IRQ_SPI(110)
-#define IRQ_GPS                 IRQ_SPI(111)
-#define IRQ_INTFEEDCTRL_SSS     IRQ_SPI(112)
-#define IRQ_SLIMBUS             IRQ_SPI(113)
-
-#define IRQ_TSI                 IRQ_SPI(115)
-#define IRQ_SATA                IRQ_SPI(116)
-
-#define MAX_IRQ_IN_COMBINER     8
-#define COMBINER_GROUP(x)       ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
-#define COMBINER_IRQ(x, y)      (COMBINER_GROUP(x) + y)
-
-#define IRQ_SYSMMU_MDMA0_0      COMBINER_IRQ(4, 0)
-#define IRQ_SYSMMU_SSS_0        COMBINER_IRQ(4, 1)
-#define IRQ_SYSMMU_FIMC0_0      COMBINER_IRQ(4, 2)
-#define IRQ_SYSMMU_FIMC1_0      COMBINER_IRQ(4, 3)
-#define IRQ_SYSMMU_FIMC2_0      COMBINER_IRQ(4, 4)
-#define IRQ_SYSMMU_FIMC3_0      COMBINER_IRQ(4, 5)
-#define IRQ_SYSMMU_JPEG_0       COMBINER_IRQ(4, 6)
-#define IRQ_SYSMMU_2D_0         COMBINER_IRQ(4, 7)
-
-#define IRQ_SYSMMU_ROTATOR_0    COMBINER_IRQ(5, 0)
-#define IRQ_SYSMMU_MDMA1_0      COMBINER_IRQ(5, 1)
-#define IRQ_SYSMMU_LCD0_M0_0    COMBINER_IRQ(5, 2)
-#define IRQ_SYSMMU_LCD1_M1_0    COMBINER_IRQ(5, 3)
-#define IRQ_SYSMMU_TV_M0_0      COMBINER_IRQ(5, 4)
-#define IRQ_SYSMMU_MFC_M0_0     COMBINER_IRQ(5, 5)
-#define IRQ_SYSMMU_MFC_M1_0     COMBINER_IRQ(5, 6)
-#define IRQ_SYSMMU_PCIE_0       COMBINER_IRQ(5, 7)
-
-#define IRQ_FIMD0_FIFO          COMBINER_IRQ(11, 0)
-#define IRQ_FIMD0_VSYNC         COMBINER_IRQ(11, 1)
-#define IRQ_FIMD0_SYSTEM        COMBINER_IRQ(11, 2)
-
-#define MAX_COMBINER_NR         16
-
-#define IRQ_ADC                 IRQ_ADC0
-#define IRQ_TC                  IRQ_PEN0
-
-#define S5P_IRQ_EINT_BASE       COMBINER_IRQ(MAX_COMBINER_NR, 0)
-
-#define S5P_EINT_BASE1          (S5P_IRQ_EINT_BASE + 0)
-#define S5P_EINT_BASE2          (S5P_IRQ_EINT_BASE + 16)
-
-/* optional GPIO interrupts */
-#define S5P_GPIOINT_BASE        (S5P_IRQ_EINT_BASE + 32)
-#define IRQ_GPIO1_NR_GROUPS     16
-#define IRQ_GPIO2_NR_GROUPS     9
-#define IRQ_GPIO_END            (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
-
-#define IRQ_TIMER_BASE          (IRQ_GPIO_END + 64)
+#define IRQ_SPI(x)                      (x + 32)
+
+/* COMBINER */
+
+#define MAX_IRQ_IN_COMBINER             8
+#define COMBINER_GROUP(x)               ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
+#define COMBINER_IRQ(x, y)              (COMBINER_GROUP(x) + y)
+
+/* For EXYNOS4 and EXYNOS5 */
+
+#define EXYNOS_IRQ_MCT_LOCALTIMER       IRQ_PPI(12)
+
+#define EXYNOS_IRQ_EINT16_31            IRQ_SPI(32)
+
+/* For EXYNOS4 SoCs */
+
+#define EXYNOS4_IRQ_EINT0               IRQ_SPI(16)
+#define EXYNOS4_IRQ_EINT1               IRQ_SPI(17)
+#define EXYNOS4_IRQ_EINT2               IRQ_SPI(18)
+#define EXYNOS4_IRQ_EINT3               IRQ_SPI(19)
+#define EXYNOS4_IRQ_EINT4               IRQ_SPI(20)
+#define EXYNOS4_IRQ_EINT5               IRQ_SPI(21)
+#define EXYNOS4_IRQ_EINT6               IRQ_SPI(22)
+#define EXYNOS4_IRQ_EINT7               IRQ_SPI(23)
+#define EXYNOS4_IRQ_EINT8               IRQ_SPI(24)
+#define EXYNOS4_IRQ_EINT9               IRQ_SPI(25)
+#define EXYNOS4_IRQ_EINT10              IRQ_SPI(26)
+#define EXYNOS4_IRQ_EINT11              IRQ_SPI(27)
+#define EXYNOS4_IRQ_EINT12              IRQ_SPI(28)
+#define EXYNOS4_IRQ_EINT13              IRQ_SPI(29)
+#define EXYNOS4_IRQ_EINT14              IRQ_SPI(30)
+#define EXYNOS4_IRQ_EINT15              IRQ_SPI(31)
+
+#define EXYNOS4_IRQ_MDMA0               IRQ_SPI(33)
+#define EXYNOS4_IRQ_MDMA1               IRQ_SPI(34)
+#define EXYNOS4_IRQ_PDMA0               IRQ_SPI(35)
+#define EXYNOS4_IRQ_PDMA1               IRQ_SPI(36)
+#define EXYNOS4_IRQ_TIMER0_VIC          IRQ_SPI(37)
+#define EXYNOS4_IRQ_TIMER1_VIC          IRQ_SPI(38)
+#define EXYNOS4_IRQ_TIMER2_VIC          IRQ_SPI(39)
+#define EXYNOS4_IRQ_TIMER3_VIC          IRQ_SPI(40)
+#define EXYNOS4_IRQ_TIMER4_VIC          IRQ_SPI(41)
+#define EXYNOS4_IRQ_MCT_L0              IRQ_SPI(42)
+#define EXYNOS4_IRQ_WDT                 IRQ_SPI(43)
+#define EXYNOS4_IRQ_RTC_ALARM           IRQ_SPI(44)
+#define EXYNOS4_IRQ_RTC_TIC             IRQ_SPI(45)
+#define EXYNOS4_IRQ_GPIO_XB             IRQ_SPI(46)
+#define EXYNOS4_IRQ_GPIO_XA             IRQ_SPI(47)
+#define EXYNOS4_IRQ_MCT_L1              IRQ_SPI(48)
+
+#define EXYNOS4_IRQ_UART0               IRQ_SPI(52)
+#define EXYNOS4_IRQ_UART1               IRQ_SPI(53)
+#define EXYNOS4_IRQ_UART2               IRQ_SPI(54)
+#define EXYNOS4_IRQ_UART3               IRQ_SPI(55)
+#define EXYNOS4_IRQ_UART4               IRQ_SPI(56)
+#define EXYNOS4_IRQ_MCT_G0              IRQ_SPI(57)
+#define EXYNOS4_IRQ_IIC                 IRQ_SPI(58)
+#define EXYNOS4_IRQ_IIC1                IRQ_SPI(59)
+#define EXYNOS4_IRQ_IIC2                IRQ_SPI(60)
+#define EXYNOS4_IRQ_IIC3                IRQ_SPI(61)
+#define EXYNOS4_IRQ_IIC4                IRQ_SPI(62)
+#define EXYNOS4_IRQ_IIC5                IRQ_SPI(63)
+#define EXYNOS4_IRQ_IIC6                IRQ_SPI(64)
+#define EXYNOS4_IRQ_IIC7                IRQ_SPI(65)
+#define EXYNOS4_IRQ_SPI0                IRQ_SPI(66)
+#define EXYNOS4_IRQ_SPI1                IRQ_SPI(67)
+#define EXYNOS4_IRQ_SPI2                IRQ_SPI(68)
+
+#define EXYNOS4_IRQ_USB_HOST            IRQ_SPI(70)
+#define EXYNOS4_IRQ_USB_HSOTG           IRQ_SPI(71)
+#define EXYNOS4_IRQ_MODEM_IF            IRQ_SPI(72)
+#define EXYNOS4_IRQ_HSMMC0              IRQ_SPI(73)
+#define EXYNOS4_IRQ_HSMMC1              IRQ_SPI(74)
+#define EXYNOS4_IRQ_HSMMC2              IRQ_SPI(75)
+#define EXYNOS4_IRQ_HSMMC3              IRQ_SPI(76)
+#define EXYNOS4_IRQ_DWMCI               IRQ_SPI(77)
+
+#define EXYNOS4_IRQ_MIPI_CSIS0          IRQ_SPI(78)
+#define EXYNOS4_IRQ_MIPI_CSIS1          IRQ_SPI(80)
+
+#define EXYNOS4_IRQ_ONENAND_AUDI        IRQ_SPI(82)
+#define EXYNOS4_IRQ_ROTATOR             IRQ_SPI(83)
+#define EXYNOS4_IRQ_FIMC0               IRQ_SPI(84)
+#define EXYNOS4_IRQ_FIMC1               IRQ_SPI(85)
+#define EXYNOS4_IRQ_FIMC2               IRQ_SPI(86)
+#define EXYNOS4_IRQ_FIMC3               IRQ_SPI(87)
+#define EXYNOS4_IRQ_JPEG                IRQ_SPI(88)
+#define EXYNOS4_IRQ_2D                  IRQ_SPI(89)
+#define EXYNOS4_IRQ_PCIE                IRQ_SPI(90)
+
+#define EXYNOS4_IRQ_MIXER               IRQ_SPI(91)
+#define EXYNOS4_IRQ_HDMI                IRQ_SPI(92)
+#define EXYNOS4_IRQ_IIC_HDMIPHY         IRQ_SPI(93)
+#define EXYNOS4_IRQ_MFC                 IRQ_SPI(94)
+#define EXYNOS4_IRQ_SDO                 IRQ_SPI(95)
+
+#define EXYNOS4_IRQ_AUDIO_SS            IRQ_SPI(96)
+#define EXYNOS4_IRQ_I2S0                IRQ_SPI(97)
+#define EXYNOS4_IRQ_I2S1                IRQ_SPI(98)
+#define EXYNOS4_IRQ_I2S2                IRQ_SPI(99)
+#define EXYNOS4_IRQ_AC97                IRQ_SPI(100)
+
+#define EXYNOS4_IRQ_SPDIF               IRQ_SPI(104)
+#define EXYNOS4_IRQ_ADC0                IRQ_SPI(105)
+#define EXYNOS4_IRQ_PEN0                IRQ_SPI(106)
+#define EXYNOS4_IRQ_ADC1                IRQ_SPI(107)
+#define EXYNOS4_IRQ_PEN1                IRQ_SPI(108)
+#define EXYNOS4_IRQ_KEYPAD              IRQ_SPI(109)
+#define EXYNOS4_IRQ_PMU                 IRQ_SPI(110)
+#define EXYNOS4_IRQ_GPS                 IRQ_SPI(111)
+#define EXYNOS4_IRQ_INTFEEDCTRL_SSS     IRQ_SPI(112)
+#define EXYNOS4_IRQ_SLIMBUS             IRQ_SPI(113)
+
+#define EXYNOS4_IRQ_TSI                 IRQ_SPI(115)
+#define EXYNOS4_IRQ_SATA                IRQ_SPI(116)
+
+#define EXYNOS4_IRQ_SYSMMU_MDMA0_0      COMBINER_IRQ(4, 0)
+#define EXYNOS4_IRQ_SYSMMU_SSS_0        COMBINER_IRQ(4, 1)
+#define EXYNOS4_IRQ_SYSMMU_FIMC0_0      COMBINER_IRQ(4, 2)
+#define EXYNOS4_IRQ_SYSMMU_FIMC1_0      COMBINER_IRQ(4, 3)
+#define EXYNOS4_IRQ_SYSMMU_FIMC2_0      COMBINER_IRQ(4, 4)
+#define EXYNOS4_IRQ_SYSMMU_FIMC3_0      COMBINER_IRQ(4, 5)
+#define EXYNOS4_IRQ_SYSMMU_JPEG_0       COMBINER_IRQ(4, 6)
+#define EXYNOS4_IRQ_SYSMMU_2D_0         COMBINER_IRQ(4, 7)
+
+#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0    COMBINER_IRQ(5, 0)
+#define EXYNOS4_IRQ_SYSMMU_MDMA1_0      COMBINER_IRQ(5, 1)
+#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0    COMBINER_IRQ(5, 2)
+#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0    COMBINER_IRQ(5, 3)
+#define EXYNOS4_IRQ_SYSMMU_TV_M0_0      COMBINER_IRQ(5, 4)
+#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0     COMBINER_IRQ(5, 5)
+#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0     COMBINER_IRQ(5, 6)
+#define EXYNOS4_IRQ_SYSMMU_PCIE_0       COMBINER_IRQ(5, 7)
+
+#define EXYNOS4_IRQ_FIMD0_FIFO          COMBINER_IRQ(11, 0)
+#define EXYNOS4_IRQ_FIMD0_VSYNC         COMBINER_IRQ(11, 1)
+#define EXYNOS4_IRQ_FIMD0_SYSTEM        COMBINER_IRQ(11, 2)
+
+#define EXYNOS4_MAX_COMBINER_NR         16
+
+#define EXYNOS4_IRQ_GPIO1_NR_GROUPS     16
+#define EXYNOS4_IRQ_GPIO2_NR_GROUPS     9
+
+/*
+ * For Compatibility:
+ * the default is for EXYNOS4, and
+ * for exynos5, should be re-mapped at function
+ */
+
+#define IRQ_TIMER0_VIC                  EXYNOS4_IRQ_TIMER0_VIC
+#define IRQ_TIMER1_VIC                  EXYNOS4_IRQ_TIMER1_VIC
+#define IRQ_TIMER2_VIC                  EXYNOS4_IRQ_TIMER2_VIC
+#define IRQ_TIMER3_VIC                  EXYNOS4_IRQ_TIMER3_VIC
+#define IRQ_TIMER4_VIC                  EXYNOS4_IRQ_TIMER4_VIC
+
+#define IRQ_WDT                         EXYNOS4_IRQ_WDT
+#define IRQ_RTC_ALARM                   EXYNOS4_IRQ_RTC_ALARM
+#define IRQ_RTC_TIC                     EXYNOS4_IRQ_RTC_TIC
+#define IRQ_GPIO_XB                     EXYNOS4_IRQ_GPIO_XB
+#define IRQ_GPIO_XA                     EXYNOS4_IRQ_GPIO_XA
+
+#define IRQ_IIC                         EXYNOS4_IRQ_IIC
+#define IRQ_IIC1                        EXYNOS4_IRQ_IIC1
+#define IRQ_IIC3                        EXYNOS4_IRQ_IIC3
+#define IRQ_IIC5                        EXYNOS4_IRQ_IIC5
+#define IRQ_IIC6                        EXYNOS4_IRQ_IIC6
+#define IRQ_IIC7                        EXYNOS4_IRQ_IIC7
+
+#define IRQ_USB_HOST                    EXYNOS4_IRQ_USB_HOST
+
+#define IRQ_HSMMC0                      EXYNOS4_IRQ_HSMMC0
+#define IRQ_HSMMC1                      EXYNOS4_IRQ_HSMMC1
+#define IRQ_HSMMC2                      EXYNOS4_IRQ_HSMMC2
+#define IRQ_HSMMC3                      EXYNOS4_IRQ_HSMMC3
+
+#define IRQ_MIPI_CSIS0                  EXYNOS4_IRQ_MIPI_CSIS0
+
+#define IRQ_ONENAND_AUDI                EXYNOS4_IRQ_ONENAND_AUDI
+
+#define IRQ_FIMC0                       EXYNOS4_IRQ_FIMC0
+#define IRQ_FIMC1                       EXYNOS4_IRQ_FIMC1
+#define IRQ_FIMC2                       EXYNOS4_IRQ_FIMC2
+#define IRQ_FIMC3                       EXYNOS4_IRQ_FIMC3
+#define IRQ_JPEG                        EXYNOS4_IRQ_JPEG
+#define IRQ_2D                          EXYNOS4_IRQ_2D
+
+#define IRQ_MIXER                       EXYNOS4_IRQ_MIXER
+#define IRQ_HDMI                        EXYNOS4_IRQ_HDMI
+#define IRQ_IIC_HDMIPHY                 EXYNOS4_IRQ_IIC_HDMIPHY
+#define IRQ_MFC                         EXYNOS4_IRQ_MFC
+#define IRQ_SDO                         EXYNOS4_IRQ_SDO
+
+#define IRQ_ADC                         EXYNOS4_IRQ_ADC0
+#define IRQ_TC                          EXYNOS4_IRQ_PEN0
+
+#define IRQ_KEYPAD                      EXYNOS4_IRQ_KEYPAD
+#define IRQ_PMU                         EXYNOS4_IRQ_PMU
+
+#define IRQ_SYSMMU_MDMA0_0              EXYNOS4_IRQ_SYSMMU_MDMA0_0
+#define IRQ_SYSMMU_SSS_0                EXYNOS4_IRQ_SYSMMU_SSS_0
+#define IRQ_SYSMMU_FIMC0_0              EXYNOS4_IRQ_SYSMMU_FIMC0_0
+#define IRQ_SYSMMU_FIMC1_0              EXYNOS4_IRQ_SYSMMU_FIMC1_0
+#define IRQ_SYSMMU_FIMC2_0              EXYNOS4_IRQ_SYSMMU_FIMC2_0
+#define IRQ_SYSMMU_FIMC3_0              EXYNOS4_IRQ_SYSMMU_FIMC3_0
+#define IRQ_SYSMMU_JPEG_0               EXYNOS4_IRQ_SYSMMU_JPEG_0
+#define IRQ_SYSMMU_2D_0                 EXYNOS4_IRQ_SYSMMU_2D_0
+
+#define IRQ_SYSMMU_ROTATOR_0            EXYNOS4_IRQ_SYSMMU_ROTATOR_0
+#define IRQ_SYSMMU_MDMA1_0              EXYNOS4_IRQ_SYSMMU_MDMA1_0
+#define IRQ_SYSMMU_LCD0_M0_0            EXYNOS4_IRQ_SYSMMU_LCD0_M0_0
+#define IRQ_SYSMMU_LCD1_M1_0            EXYNOS4_IRQ_SYSMMU_LCD1_M1_0
+#define IRQ_SYSMMU_TV_M0_0              EXYNOS4_IRQ_SYSMMU_TV_M0_0
+#define IRQ_SYSMMU_MFC_M0_0             EXYNOS4_IRQ_SYSMMU_MFC_M0_0
+#define IRQ_SYSMMU_MFC_M1_0             EXYNOS4_IRQ_SYSMMU_MFC_M1_0
+#define IRQ_SYSMMU_PCIE_0               EXYNOS4_IRQ_SYSMMU_PCIE_0
+
+#define IRQ_FIMD0_FIFO                  EXYNOS4_IRQ_FIMD0_FIFO
+#define IRQ_FIMD0_VSYNC                 EXYNOS4_IRQ_FIMD0_VSYNC
+#define IRQ_FIMD0_SYSTEM                EXYNOS4_IRQ_FIMD0_SYSTEM
+
+#define IRQ_GPIO1_NR_GROUPS             EXYNOS4_IRQ_GPIO1_NR_GROUPS
+#define IRQ_GPIO2_NR_GROUPS             EXYNOS4_IRQ_GPIO2_NR_GROUPS
+
+/* For EXYNOS5 SoCs */
+
+#define EXYNOS5_IRQ_MDMA0               IRQ_SPI(33)
+#define EXYNOS5_IRQ_PDMA0               IRQ_SPI(34)
+#define EXYNOS5_IRQ_PDMA1               IRQ_SPI(35)
+#define EXYNOS5_IRQ_TIMER0_VIC          IRQ_SPI(36)
+#define EXYNOS5_IRQ_TIMER1_VIC          IRQ_SPI(37)
+#define EXYNOS5_IRQ_TIMER2_VIC          IRQ_SPI(38)
+#define EXYNOS5_IRQ_TIMER3_VIC          IRQ_SPI(39)
+#define EXYNOS5_IRQ_TIMER4_VIC          IRQ_SPI(40)
+#define EXYNOS5_IRQ_RTIC                IRQ_SPI(41)
+#define EXYNOS5_IRQ_WDT                 IRQ_SPI(42)
+#define EXYNOS5_IRQ_RTC_ALARM           IRQ_SPI(43)
+#define EXYNOS5_IRQ_RTC_TIC             IRQ_SPI(44)
+#define EXYNOS5_IRQ_GPIO_XB             IRQ_SPI(45)
+#define EXYNOS5_IRQ_GPIO_XA             IRQ_SPI(46)
+#define EXYNOS5_IRQ_GPIO                IRQ_SPI(47)
+#define EXYNOS5_IRQ_IEM_IEC             IRQ_SPI(48)
+#define EXYNOS5_IRQ_IEM_APC             IRQ_SPI(49)
+#define EXYNOS5_IRQ_GPIO_C2C            IRQ_SPI(50)
+#define EXYNOS5_IRQ_UART0               IRQ_SPI(51)
+#define EXYNOS5_IRQ_UART1               IRQ_SPI(52)
+#define EXYNOS5_IRQ_UART2               IRQ_SPI(53)
+#define EXYNOS5_IRQ_UART3               IRQ_SPI(54)
+#define EXYNOS5_IRQ_UART4               IRQ_SPI(55)
+#define EXYNOS5_IRQ_IIC                 IRQ_SPI(56)
+#define EXYNOS5_IRQ_IIC1                IRQ_SPI(57)
+#define EXYNOS5_IRQ_IIC2                IRQ_SPI(58)
+#define EXYNOS5_IRQ_IIC3                IRQ_SPI(59)
+#define EXYNOS5_IRQ_IIC4                IRQ_SPI(60)
+#define EXYNOS5_IRQ_IIC5                IRQ_SPI(61)
+#define EXYNOS5_IRQ_IIC6                IRQ_SPI(62)
+#define EXYNOS5_IRQ_IIC7                IRQ_SPI(63)
+#define EXYNOS5_IRQ_IIC_HDMIPHY         IRQ_SPI(64)
+#define EXYNOS5_IRQ_TMU                 IRQ_SPI(65)
+#define EXYNOS5_IRQ_FIQ_0               IRQ_SPI(66)
+#define EXYNOS5_IRQ_FIQ_1               IRQ_SPI(67)
+#define EXYNOS5_IRQ_SPI0                IRQ_SPI(68)
+#define EXYNOS5_IRQ_SPI1                IRQ_SPI(69)
+#define EXYNOS5_IRQ_SPI2                IRQ_SPI(70)
+#define EXYNOS5_IRQ_USB_HOST            IRQ_SPI(71)
+#define EXYNOS5_IRQ_USB3_DRD            IRQ_SPI(72)
+#define EXYNOS5_IRQ_MIPI_HSI            IRQ_SPI(73)
+#define EXYNOS5_IRQ_USB_HSOTG           IRQ_SPI(74)
+#define EXYNOS5_IRQ_HSMMC0              IRQ_SPI(75)
+#define EXYNOS5_IRQ_HSMMC1              IRQ_SPI(76)
+#define EXYNOS5_IRQ_HSMMC2              IRQ_SPI(77)
+#define EXYNOS5_IRQ_HSMMC3              IRQ_SPI(78)
+#define EXYNOS5_IRQ_MIPICSI0            IRQ_SPI(79)
+#define EXYNOS5_IRQ_MIPICSI1            IRQ_SPI(80)
+#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT   IRQ_SPI(81)
+#define EXYNOS5_IRQ_MIPIDSI0            IRQ_SPI(82)
+#define EXYNOS5_IRQ_ROTATOR             IRQ_SPI(84)
+#define EXYNOS5_IRQ_GSC0                IRQ_SPI(85)
+#define EXYNOS5_IRQ_GSC1                IRQ_SPI(86)
+#define EXYNOS5_IRQ_GSC2                IRQ_SPI(87)
+#define EXYNOS5_IRQ_GSC3                IRQ_SPI(88)
+#define EXYNOS5_IRQ_JPEG                IRQ_SPI(89)
+#define EXYNOS5_IRQ_EFNFCON_DMA         IRQ_SPI(90)
+#define EXYNOS5_IRQ_2D                  IRQ_SPI(91)
+#define EXYNOS5_IRQ_SFMC0               IRQ_SPI(92)
+#define EXYNOS5_IRQ_SFMC1               IRQ_SPI(93)
+#define EXYNOS5_IRQ_MIXER               IRQ_SPI(94)
+#define EXYNOS5_IRQ_HDMI                IRQ_SPI(95)
+#define EXYNOS5_IRQ_MFC                 IRQ_SPI(96)
+#define EXYNOS5_IRQ_AUDIO_SS            IRQ_SPI(97)
+#define EXYNOS5_IRQ_I2S0                IRQ_SPI(98)
+#define EXYNOS5_IRQ_I2S1                IRQ_SPI(99)
+#define EXYNOS5_IRQ_I2S2                IRQ_SPI(100)
+#define EXYNOS5_IRQ_AC97                IRQ_SPI(101)
+#define EXYNOS5_IRQ_PCM0                IRQ_SPI(102)
+#define EXYNOS5_IRQ_PCM1                IRQ_SPI(103)
+#define EXYNOS5_IRQ_PCM2                IRQ_SPI(104)
+#define EXYNOS5_IRQ_SPDIF               IRQ_SPI(105)
+#define EXYNOS5_IRQ_ADC0                IRQ_SPI(106)
+
+#define EXYNOS5_IRQ_SATA_PHY            IRQ_SPI(108)
+#define EXYNOS5_IRQ_SATA_PMEMREQ        IRQ_SPI(109)
+#define EXYNOS5_IRQ_CAM_C               IRQ_SPI(110)
+#define EXYNOS5_IRQ_EAGLE_PMU           IRQ_SPI(111)
+#define EXYNOS5_IRQ_INTFEEDCTRL_SSS     IRQ_SPI(112)
+#define EXYNOS5_IRQ_DP1_INTP1           IRQ_SPI(113)
+#define EXYNOS5_IRQ_CEC                 IRQ_SPI(114)
+#define EXYNOS5_IRQ_SATA                IRQ_SPI(115)
+#define EXYNOS5_IRQ_NFCON               IRQ_SPI(116)
+
+#define EXYNOS5_IRQ_MMC44               IRQ_SPI(123)
+#define EXYNOS5_IRQ_MDMA1               IRQ_SPI(124)
+#define EXYNOS5_IRQ_FIMC_LITE0          IRQ_SPI(125)
+#define EXYNOS5_IRQ_FIMC_LITE1          IRQ_SPI(126)
+#define EXYNOS5_IRQ_RP_TIMER            IRQ_SPI(127)
+
+#define EXYNOS5_IRQ_PMU                 COMBINER_IRQ(1, 2)
+#define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(1, 6)
+
+#define EXYNOS5_IRQ_SYSMMU_GSC0_0       COMBINER_IRQ(2, 0)
+#define EXYNOS5_IRQ_SYSMMU_GSC0_1       COMBINER_IRQ(2, 1)
+#define EXYNOS5_IRQ_SYSMMU_GSC1_0       COMBINER_IRQ(2, 2)
+#define EXYNOS5_IRQ_SYSMMU_GSC1_1       COMBINER_IRQ(2, 3)
+#define EXYNOS5_IRQ_SYSMMU_GSC2_0       COMBINER_IRQ(2, 4)
+#define EXYNOS5_IRQ_SYSMMU_GSC2_1       COMBINER_IRQ(2, 5)
+#define EXYNOS5_IRQ_SYSMMU_GSC3_0       COMBINER_IRQ(2, 6)
+#define EXYNOS5_IRQ_SYSMMU_GSC3_1       COMBINER_IRQ(2, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_FIMD1_0      COMBINER_IRQ(3, 2)
+#define EXYNOS5_IRQ_SYSMMU_FIMD1_1      COMBINER_IRQ(3, 3)
+#define EXYNOS5_IRQ_SYSMMU_LITE0_0      COMBINER_IRQ(3, 4)
+#define EXYNOS5_IRQ_SYSMMU_LITE0_1      COMBINER_IRQ(3, 5)
+#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
+#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0    COMBINER_IRQ(4, 0)
+#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1    COMBINER_IRQ(4, 1)
+#define EXYNOS5_IRQ_SYSMMU_JPEG_0       COMBINER_IRQ(4, 2)
+#define EXYNOS5_IRQ_SYSMMU_JPEG_1       COMBINER_IRQ(4, 3)
+
+#define EXYNOS5_IRQ_SYSMMU_FD_0         COMBINER_IRQ(5, 0)
+#define EXYNOS5_IRQ_SYSMMU_FD_1         COMBINER_IRQ(5, 1)
+#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
+#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
+#define EXYNOS5_IRQ_SYSMMU_MCUISP_0     COMBINER_IRQ(5, 4)
+#define EXYNOS5_IRQ_SYSMMU_MCUISP_1     COMBINER_IRQ(5, 5)
+#define EXYNOS5_IRQ_SYSMMU_3DNR_0       COMBINER_IRQ(5, 6)
+#define EXYNOS5_IRQ_SYSMMU_3DNR_1       COMBINER_IRQ(5, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ARM_0        COMBINER_IRQ(6, 0)
+#define EXYNOS5_IRQ_SYSMMU_ARM_1        COMBINER_IRQ(6, 1)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_0      COMBINER_IRQ(6, 2)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_1      COMBINER_IRQ(6, 3)
+#define EXYNOS5_IRQ_SYSMMU_RTIC_0       COMBINER_IRQ(6, 4)
+#define EXYNOS5_IRQ_SYSMMU_RTIC_1       COMBINER_IRQ(6, 5)
+#define EXYNOS5_IRQ_SYSMMU_SSS_0        COMBINER_IRQ(6, 6)
+#define EXYNOS5_IRQ_SYSMMU_SSS_1        COMBINER_IRQ(6, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_MDMA0_0      COMBINER_IRQ(7, 0)
+#define EXYNOS5_IRQ_SYSMMU_MDMA0_1      COMBINER_IRQ(7, 1)
+#define EXYNOS5_IRQ_SYSMMU_MDMA1_0      COMBINER_IRQ(7, 2)
+#define EXYNOS5_IRQ_SYSMMU_MDMA1_1      COMBINER_IRQ(7, 3)
+#define EXYNOS5_IRQ_SYSMMU_TV_0         COMBINER_IRQ(7, 4)
+#define EXYNOS5_IRQ_SYSMMU_TV_1         COMBINER_IRQ(7, 5)
+#define EXYNOS5_IRQ_SYSMMU_GPSX_0       COMBINER_IRQ(7, 6)
+#define EXYNOS5_IRQ_SYSMMU_GPSX_1       COMBINER_IRQ(7, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_0      COMBINER_IRQ(8, 5)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_1      COMBINER_IRQ(8, 6)
+
+#define EXYNOS5_IRQ_SYSMMU_DIS1_0       COMBINER_IRQ(9, 4)
+#define EXYNOS5_IRQ_SYSMMU_DIS1_1       COMBINER_IRQ(9, 5)
+
+#define EXYNOS5_IRQ_DP                  COMBINER_IRQ(10, 3)
+#define EXYNOS5_IRQ_SYSMMU_DIS0_0       COMBINER_IRQ(10, 4)
+#define EXYNOS5_IRQ_SYSMMU_DIS0_1       COMBINER_IRQ(10, 5)
+#define EXYNOS5_IRQ_SYSMMU_ISP_0        COMBINER_IRQ(10, 6)
+#define EXYNOS5_IRQ_SYSMMU_ISP_1        COMBINER_IRQ(10, 7)
+
+#define EXYNOS5_IRQ_SYSMMU_ODC_0        COMBINER_IRQ(11, 0)
+#define EXYNOS5_IRQ_SYSMMU_ODC_1        COMBINER_IRQ(11, 1)
+#define EXYNOS5_IRQ_SYSMMU_DRC_0        COMBINER_IRQ(11, 6)
+#define EXYNOS5_IRQ_SYSMMU_DRC_1        COMBINER_IRQ(11, 7)
+
+#define EXYNOS5_IRQ_FIMD1_FIFO          COMBINER_IRQ(18, 4)
+#define EXYNOS5_IRQ_FIMD1_VSYNC         COMBINER_IRQ(18, 5)
+#define EXYNOS5_IRQ_FIMD1_SYSTEM        COMBINER_IRQ(18, 6)
+
+#define EXYNOS5_IRQ_EINT0               COMBINER_IRQ(23, 0)
+#define EXYNOS5_IRQ_MCT_L0              COMBINER_IRQ(23, 1)
+#define EXYNOS5_IRQ_MCT_L1              COMBINER_IRQ(23, 2)
+#define EXYNOS5_IRQ_MCT_G0              COMBINER_IRQ(23, 3)
+#define EXYNOS5_IRQ_MCT_G1              COMBINER_IRQ(23, 4)
+#define EXYNOS5_IRQ_MCT_G2              COMBINER_IRQ(23, 5)
+#define EXYNOS5_IRQ_MCT_G3              COMBINER_IRQ(23, 6)
+
+#define EXYNOS5_IRQ_EINT1               COMBINER_IRQ(24, 0)
+#define EXYNOS5_IRQ_SYSMMU_LITE1_0      COMBINER_IRQ(24, 1)
+#define EXYNOS5_IRQ_SYSMMU_LITE1_1      COMBINER_IRQ(24, 2)
+#define EXYNOS5_IRQ_SYSMMU_2D_0         COMBINER_IRQ(24, 5)
+#define EXYNOS5_IRQ_SYSMMU_2D_1         COMBINER_IRQ(24, 6)
+
+#define EXYNOS5_IRQ_EINT2               COMBINER_IRQ(25, 0)
+#define EXYNOS5_IRQ_EINT3               COMBINER_IRQ(25, 1)
+
+#define EXYNOS5_IRQ_EINT4               COMBINER_IRQ(26, 0)
+#define EXYNOS5_IRQ_EINT5               COMBINER_IRQ(26, 1)
+
+#define EXYNOS5_IRQ_EINT6               COMBINER_IRQ(27, 0)
+#define EXYNOS5_IRQ_EINT7               COMBINER_IRQ(27, 1)
+
+#define EXYNOS5_IRQ_EINT8               COMBINER_IRQ(28, 0)
+#define EXYNOS5_IRQ_EINT9               COMBINER_IRQ(28, 1)
+
+#define EXYNOS5_IRQ_EINT10              COMBINER_IRQ(29, 0)
+#define EXYNOS5_IRQ_EINT11              COMBINER_IRQ(29, 1)
+
+#define EXYNOS5_IRQ_EINT12              COMBINER_IRQ(30, 0)
+#define EXYNOS5_IRQ_EINT13              COMBINER_IRQ(30, 1)
+
+#define EXYNOS5_IRQ_EINT14              COMBINER_IRQ(31, 0)
+#define EXYNOS5_IRQ_EINT15              COMBINER_IRQ(31, 1)
+
+#define EXYNOS5_MAX_COMBINER_NR         32
+
+#define EXYNOS5_IRQ_GPIO1_NR_GROUPS     13
+#define EXYNOS5_IRQ_GPIO2_NR_GROUPS     9
+#define EXYNOS5_IRQ_GPIO3_NR_GROUPS     5
+#define EXYNOS5_IRQ_GPIO4_NR_GROUPS     1
+
+#define MAX_COMBINER_NR                 (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
+                                        EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
+
+#define S5P_EINT_BASE1                  COMBINER_IRQ(MAX_COMBINER_NR, 0)
+#define S5P_EINT_BASE2                  (S5P_EINT_BASE1 + 16)
+#define S5P_GPIOINT_BASE                (S5P_EINT_BASE1 + 32)
+#define IRQ_GPIO_END                    (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
+#define IRQ_TIMER_BASE                  (IRQ_GPIO_END + 64)
 
 /* Set the default NR_IRQS */
-#define NR_IRQS                 (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+
+#define NR_IRQS                         (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
 
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 54307b09813a..024d38ff1718 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -25,6 +25,7 @@
 
 #define EXYNOS4_PA_SYSRAM0              0x02025000
 #define EXYNOS4_PA_SYSRAM1              0x02020000
+#define EXYNOS5_PA_SYSRAM               0x02020000
 
 #define EXYNOS4_PA_FIMC0                0x11800000
 #define EXYNOS4_PA_FIMC1                0x11810000
@@ -48,14 +49,23 @@
 #define EXYNOS4_PA_ONENAND              0x0C000000
 #define EXYNOS4_PA_ONENAND_DMA          0x0C600000
 
-#define EXYNOS4_PA_CHIPID               0x10000000
+#define EXYNOS_PA_CHIPID                0x10000000
 
 #define EXYNOS4_PA_SYSCON               0x10010000
+#define EXYNOS5_PA_SYSCON               0x10050100
+
 #define EXYNOS4_PA_PMU                  0x10020000
+#define EXYNOS5_PA_PMU                  0x10040000
+
 #define EXYNOS4_PA_CMU                  0x10030000
+#define EXYNOS5_PA_CMU                  0x10010000
 
 #define EXYNOS4_PA_SYSTIMER             0x10050000
+#define EXYNOS5_PA_SYSTIMER             0x101C0000
+
 #define EXYNOS4_PA_WATCHDOG             0x10060000
+#define EXYNOS5_PA_WATCHDOG             0x101D0000
+
 #define EXYNOS4_PA_RTC                  0x10070000
 
 #define EXYNOS4_PA_KEYPAD               0x100A0000
@@ -64,9 +74,12 @@
 #define EXYNOS4_PA_DMC1                 0x10410000
 
 #define EXYNOS4_PA_COMBINER             0x10440000
+#define EXYNOS5_PA_COMBINER             0x10440000
 
 #define EXYNOS4_PA_GIC_CPU              0x10480000
 #define EXYNOS4_PA_GIC_DIST             0x10490000
+#define EXYNOS5_PA_GIC_CPU              0x10480000
+#define EXYNOS5_PA_GIC_DIST             0x10490000
 
 #define EXYNOS4_PA_COREPERI             0x10500000
 #define EXYNOS4_PA_TWD                  0x10500600
@@ -97,7 +110,6 @@
 #define EXYNOS4_PA_SPI1                 0x13930000
 #define EXYNOS4_PA_SPI2                 0x13940000
 
-
 #define EXYNOS4_PA_GPIO1                0x11400000
 #define EXYNOS4_PA_GPIO2                0x11000000
 #define EXYNOS4_PA_GPIO3                0x03860000
@@ -119,6 +131,7 @@
 #define EXYNOS4_PA_SATAPHY_CTRL         0x126B0000
 
 #define EXYNOS4_PA_SROMC                0x12570000
+#define EXYNOS5_PA_SROMC                0x12250000
 
 #define EXYNOS4_PA_EHCI                 0x12580000
 #define EXYNOS4_PA_OHCI                 0x12590000
@@ -126,6 +139,7 @@
 #define EXYNOS4_PA_MFC                  0x13400000
 
 #define EXYNOS4_PA_UART                 0x13800000
+#define EXYNOS5_PA_UART                 0x12C00000
 
 #define EXYNOS4_PA_VP                   0x12C00000
 #define EXYNOS4_PA_MIXER                0x12C10000
@@ -134,6 +148,7 @@
 #define EXYNOS4_PA_IIC_HDMIPHY          0x138E0000
 
 #define EXYNOS4_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
+#define EXYNOS5_PA_IIC(x)               (0x12C60000 + ((x) * 0x10000))
 
 #define EXYNOS4_PA_ADC                  0x13910000
 #define EXYNOS4_PA_ADC1                 0x13911000
@@ -143,8 +158,10 @@
 #define EXYNOS4_PA_SPDIF                0x139B0000
 
 #define EXYNOS4_PA_TIMER                0x139D0000
+#define EXYNOS5_PA_TIMER                0x12DD0000
 
 #define EXYNOS4_PA_SDRAM                0x40000000
+#define EXYNOS5_PA_SDRAM                0x40000000
 
 /* Compatibiltiy Defines */
 
@@ -162,7 +179,6 @@
 #define S3C_PA_IIC7                     EXYNOS4_PA_IIC(7)
 #define S3C_PA_RTC                      EXYNOS4_PA_RTC
 #define S3C_PA_WDT                      EXYNOS4_PA_WATCHDOG
-#define S3C_PA_UART                     EXYNOS4_PA_UART
 #define S3C_PA_SPI0                     EXYNOS4_PA_SPI0
 #define S3C_PA_SPI1                     EXYNOS4_PA_SPI1
 #define S3C_PA_SPI2                     EXYNOS4_PA_SPI2
@@ -193,15 +209,18 @@
 
 /* Compatibility UART */
 
-#define S3C_VA_UARTx(x)                 (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+#define EXYNOS4_PA_UART0                0x13800000
+#define EXYNOS4_PA_UART1                0x13810000
+#define EXYNOS4_PA_UART2                0x13820000
+#define EXYNOS4_PA_UART3                0x13830000
+#define EXYNOS4_SZ_UART                 SZ_256
 
-#define S5P_PA_UART(x)                  (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_PA_UART0                    S5P_PA_UART(0)
-#define S5P_PA_UART1                    S5P_PA_UART(1)
-#define S5P_PA_UART2                    S5P_PA_UART(2)
-#define S5P_PA_UART3                    S5P_PA_UART(3)
-#define S5P_PA_UART4                    S5P_PA_UART(4)
+#define EXYNOS5_PA_UART0                0x12C00000
+#define EXYNOS5_PA_UART1                0x12C10000
+#define EXYNOS5_PA_UART2                0x12C20000
+#define EXYNOS5_PA_UART3                0x12C30000
+#define EXYNOS5_SZ_UART                 SZ_256
 
-#define S5P_SZ_UART                     SZ_256
+#define S3C_VA_UARTx(x)                 (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index 1e4abd64a547..e141c1fd68d8 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -253,6 +253,68 @@
 #define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT          (0)
 #define EXYNOS4_CLKDIV_CAM1_JPEG_MASK           (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
 
+/* For EXYNOS5250 */
+
+#define EXYNOS5_APLL_CON0                       EXYNOS_CLKREG(0x00100)
+#define EXYNOS5_CLKSRC_CPU                      EXYNOS_CLKREG(0x00200)
+#define EXYNOS5_CLKDIV_CPU0                     EXYNOS_CLKREG(0x00500)
+#define EXYNOS5_MPLL_CON0                       EXYNOS_CLKREG(0x04100)
+#define EXYNOS5_CLKSRC_CORE1                    EXYNOS_CLKREG(0x04204)
+
+#define EXYNOS5_CLKGATE_IP_CORE                 EXYNOS_CLKREG(0x04900)
+
+#define EXYNOS5_CLKDIV_ACP                      EXYNOS_CLKREG(0x08500)
+
+#define EXYNOS5_CLKSRC_TOP2                     EXYNOS_CLKREG(0x10218)
+#define EXYNOS5_EPLL_CON0                       EXYNOS_CLKREG(0x10130)
+#define EXYNOS5_EPLL_CON1                       EXYNOS_CLKREG(0x10134)
+#define EXYNOS5_VPLL_CON0                       EXYNOS_CLKREG(0x10140)
+#define EXYNOS5_VPLL_CON1                       EXYNOS_CLKREG(0x10144)
+#define EXYNOS5_CPLL_CON0                       EXYNOS_CLKREG(0x10120)
+
+#define EXYNOS5_CLKSRC_TOP0                     EXYNOS_CLKREG(0x10210)
+#define EXYNOS5_CLKSRC_TOP3                     EXYNOS_CLKREG(0x1021C)
+#define EXYNOS5_CLKSRC_GSCL                     EXYNOS_CLKREG(0x10220)
+#define EXYNOS5_CLKSRC_DISP1_0                  EXYNOS_CLKREG(0x1022C)
+#define EXYNOS5_CLKSRC_FSYS                     EXYNOS_CLKREG(0x10244)
+#define EXYNOS5_CLKSRC_PERIC0                   EXYNOS_CLKREG(0x10250)
+
+#define EXYNOS5_CLKSRC_MASK_TOP                 EXYNOS_CLKREG(0x10310)
+#define EXYNOS5_CLKSRC_MASK_GSCL                EXYNOS_CLKREG(0x10320)
+#define EXYNOS5_CLKSRC_MASK_DISP1_0             EXYNOS_CLKREG(0x1032C)
+#define EXYNOS5_CLKSRC_MASK_FSYS                EXYNOS_CLKREG(0x10340)
+#define EXYNOS5_CLKSRC_MASK_PERIC0              EXYNOS_CLKREG(0x10350)
+
+#define EXYNOS5_CLKDIV_TOP0                     EXYNOS_CLKREG(0x10510)
+#define EXYNOS5_CLKDIV_TOP1                     EXYNOS_CLKREG(0x10514)
+#define EXYNOS5_CLKDIV_GSCL                     EXYNOS_CLKREG(0x10520)
+#define EXYNOS5_CLKDIV_DISP1_0                  EXYNOS_CLKREG(0x1052C)
+#define EXYNOS5_CLKDIV_GEN                      EXYNOS_CLKREG(0x1053C)
+#define EXYNOS5_CLKDIV_FSYS0                    EXYNOS_CLKREG(0x10548)
+#define EXYNOS5_CLKDIV_FSYS1                    EXYNOS_CLKREG(0x1054C)
+#define EXYNOS5_CLKDIV_FSYS2                    EXYNOS_CLKREG(0x10550)
+#define EXYNOS5_CLKDIV_FSYS3                    EXYNOS_CLKREG(0x10554)
+#define EXYNOS5_CLKDIV_PERIC0                   EXYNOS_CLKREG(0x10558)
+
+#define EXYNOS5_CLKGATE_IP_ACP                  EXYNOS_CLKREG(0x08800)
+#define EXYNOS5_CLKGATE_IP_GSCL                 EXYNOS_CLKREG(0x10920)
+#define EXYNOS5_CLKGATE_IP_DISP1                EXYNOS_CLKREG(0x10928)
+#define EXYNOS5_CLKGATE_IP_MFC                  EXYNOS_CLKREG(0x1092C)
+#define EXYNOS5_CLKGATE_IP_GEN                  EXYNOS_CLKREG(0x10934)
+#define EXYNOS5_CLKGATE_IP_FSYS                 EXYNOS_CLKREG(0x10944)
+#define EXYNOS5_CLKGATE_IP_GPS                  EXYNOS_CLKREG(0x1094C)
+#define EXYNOS5_CLKGATE_IP_PERIC                EXYNOS_CLKREG(0x10950)
+#define EXYNOS5_CLKGATE_IP_PERIS                EXYNOS_CLKREG(0x10960)
+#define EXYNOS5_CLKGATE_BLOCK                   EXYNOS_CLKREG(0x10980)
+
+#define EXYNOS5_BPLL_CON0                       EXYNOS_CLKREG(0x20110)
+#define EXYNOS5_CLKSRC_CDREX                    EXYNOS_CLKREG(0x20200)
+#define EXYNOS5_CLKDIV_CDREX                    EXYNOS_CLKREG(0x20500)
+
+#define EXYNOS5_EPLL_LOCK                       EXYNOS_CLKREG(0x10030)
+
+#define EXYNOS5_EPLLCON0_LOCKED_SHIFT           (29)
+
 /* Compatibility defines and inclusion */
 
 #include <mach/regs-pmu.h>
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
index 1401b21663a5..e4b5b60dcb85 100644
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ b/arch/arm/mach-exynos/include/mach/regs-gpio.h
@@ -16,6 +16,15 @@
 #include <mach/map.h>
 #include <mach/irqs.h>
 
+#define EINT_REG_NR(x)                  (EINT_OFFSET(x) >> 3)
+#define EINT_CON(b, x)                  (b + 0xE00 + (EINT_REG_NR(x) * 4))
+#define EINT_FLTCON(b, x)               (b + 0xE80 + (EINT_REG_NR(x) * 4))
+#define EINT_MASK(b, x)                 (b + 0xF00 + (EINT_REG_NR(x) * 4))
+#define EINT_PEND(b, x)                 (b + 0xF40 + (EINT_REG_NR(x) * 4))
+
+#define EINT_OFFSET_BIT(x)              (1 << (EINT_OFFSET(x) & 0x7))
+
+/* compatibility for plat-s5p/irq-pm.c */
 #define EXYNOS4_EINT40CON               (S5P_VA_GPIO2 + 0xE00)
 #define S5P_EINT_CON(x)                 (EXYNOS4_EINT40CON + ((x) * 0x4))
 
@@ -28,15 +37,4 @@
 #define EXYNOS4_EINT40PEND              (S5P_VA_GPIO2 + 0xF40)
 #define S5P_EINT_PEND(x)                (EXYNOS4_EINT40PEND + ((x) * 0x4))
 
-#define EINT_REG_NR(x)                  (EINT_OFFSET(x) >> 3)
-
-#define eint_irq_to_bit(irq)            (1 << (EINT_OFFSET(irq) & 0x7))
-
-#define EINT_MODE                       S3C_GPIO_SFN(0xf)
-
-#define EINT_GPIO_0(x)                  EXYNOS4_GPX0(x)
-#define EINT_GPIO_1(x)                  EXYNOS4_GPX1(x)
-#define EINT_GPIO_2(x)                  EXYNOS4_GPX2(x)
-#define EINT_GPIO_3(x)                  EXYNOS4_GPX3(x)
-
 #endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4fff8e938fec..4c53f38b5a9e 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -31,6 +31,7 @@
 #define S5P_USE_STANDBYWFE_ISP_ARM              (1 << 26)
 
 #define S5P_SWRESET                             S5P_PMUREG(0x0400)
+#define EXYNOS_SWRESET                          S5P_PMUREG(0x0400)
 
 #define S5P_WAKEUP_STAT                         S5P_PMUREG(0x0600)
 #define S5P_EINT_WAKEUP_MASK                    S5P_PMUREG(0x0604)
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 21d97bcd9acb..493f4f365ddf 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -1,9 +1,8 @@
-/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
- * EXYNOS4 - uncompress code
+ * EXYNOS - uncompress code
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -13,12 +12,20 @@
 #ifndef __ASM_ARCH_UNCOMPRESS_H
 #define __ASM_ARCH_UNCOMPRESS_H __FILE__
 
+#include <asm/mach-types.h>
+
 #include <mach/map.h>
+
+volatile u8 *uart_base;
+
 #include <plat/uncompress.h>
 
 static void arch_detect_cpu(void)
 {
-        /* we do not need to do any cpu detection here at the moment. */
+        if (machine_is_smdk5250())
+                uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
+        else
+                uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
 
         /*
          * For preventing FIFO overrun or infinite loop of UART console,