diff options
Diffstat (limited to 'arch/arm/mach-at91/include')
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91_pmc.h | 14 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91cap9.h | 122 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91cap9_matrix.h | 137 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h | 10 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/board.h | 6 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/cpu.h | 21 | ||||
-rw-r--r-- | arch/arm/mach-at91/include/mach/hardware.h | 4 |
7 files changed, 11 insertions, 303 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index e46f93e34aab..dbdd6ae473d5 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h | |||
@@ -23,10 +23,8 @@ | |||
23 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ | 23 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ |
24 | #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ | 24 | #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ |
25 | #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ | 25 | #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ |
26 | #define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */ | ||
27 | #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ | 26 | #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ |
28 | #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ | 27 | #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ |
29 | #define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ | ||
30 | #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ | 28 | #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ |
31 | #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ | 29 | #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ |
32 | #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ | 30 | #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ |
@@ -40,7 +38,7 @@ | |||
40 | #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ | 38 | #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ |
41 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ | 39 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ |
42 | 40 | ||
43 | #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */ | 41 | #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9] */ |
44 | #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ | 42 | #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ |
45 | #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ | 43 | #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ |
46 | #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ | 44 | #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ |
@@ -48,7 +46,7 @@ | |||
48 | 46 | ||
49 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ | 47 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ |
50 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ | 48 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ |
51 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ | 49 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x] */ |
52 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ | 50 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ |
53 | 51 | ||
54 | #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ | 52 | #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ |
@@ -87,7 +85,7 @@ | |||
87 | #define AT91RM9200_PMC_MDIV_2 (1 << 8) | 85 | #define AT91RM9200_PMC_MDIV_2 (1 << 8) |
88 | #define AT91RM9200_PMC_MDIV_3 (2 << 8) | 86 | #define AT91RM9200_PMC_MDIV_3 (2 << 8) |
89 | #define AT91RM9200_PMC_MDIV_4 (3 << 8) | 87 | #define AT91RM9200_PMC_MDIV_4 (3 << 8) |
90 | #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ | 88 | #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */ |
91 | #define AT91SAM9_PMC_MDIV_2 (1 << 8) | 89 | #define AT91SAM9_PMC_MDIV_2 (1 << 8) |
92 | #define AT91SAM9_PMC_MDIV_4 (2 << 8) | 90 | #define AT91SAM9_PMC_MDIV_4 (2 << 8) |
93 | #define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ | 91 | #define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ |
@@ -117,17 +115,15 @@ | |||
117 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ | 115 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ |
118 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ | 116 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ |
119 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ | 117 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ |
120 | #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */ | 118 | #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */ |
121 | #define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ | ||
122 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ | 119 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ |
123 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ | 120 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ |
124 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ | 121 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ |
125 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ | 122 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ |
126 | #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ | 123 | #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ |
127 | 124 | ||
128 | #define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ | 125 | #define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Write Protect Mode Register [some SAM9] */ |
129 | #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ | 126 | #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ |
130 | 127 | ||
131 | #define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ | ||
132 | 128 | ||
133 | #endif | 129 | #endif |
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h deleted file mode 100644 index 61d952902f2b..000000000000 --- a/arch/arm/mach-at91/include/mach/at91cap9.h +++ /dev/null | |||
@@ -1,122 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-at91/include/mach/at91cap9.h | ||
3 | * | ||
4 | * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> | ||
5 | * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> | ||
6 | * Copyright (C) 2007 Atmel Corporation. | ||
7 | * | ||
8 | * Common definitions. | ||
9 | * Based on AT91CAP9 datasheet revision B (Preliminary). | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License as published by | ||
13 | * the Free Software Foundation; either version 2 of the License, or | ||
14 | * (at your option) any later version. | ||
15 | */ | ||
16 | |||
17 | #ifndef AT91CAP9_H | ||
18 | #define AT91CAP9_H | ||
19 | |||
20 | /* | ||
21 | * Peripheral identifiers/interrupts. | ||
22 | */ | ||
23 | #define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */ | ||
24 | #define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */ | ||
25 | #define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */ | ||
26 | #define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */ | ||
27 | #define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */ | ||
28 | #define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */ | ||
29 | #define AT91CAP9_ID_US0 8 /* USART 0 */ | ||
30 | #define AT91CAP9_ID_US1 9 /* USART 1 */ | ||
31 | #define AT91CAP9_ID_US2 10 /* USART 2 */ | ||
32 | #define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */ | ||
33 | #define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */ | ||
34 | #define AT91CAP9_ID_CAN 13 /* CAN */ | ||
35 | #define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */ | ||
36 | #define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */ | ||
37 | #define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */ | ||
38 | #define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */ | ||
39 | #define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */ | ||
40 | #define AT91CAP9_ID_AC97C 19 /* AC97 Controller */ | ||
41 | #define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */ | ||
42 | #define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */ | ||
43 | #define AT91CAP9_ID_EMAC 22 /* Ethernet */ | ||
44 | #define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */ | ||
45 | #define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */ | ||
46 | #define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */ | ||
47 | #define AT91CAP9_ID_LCDC 26 /* LCD Controller */ | ||
48 | #define AT91CAP9_ID_DMA 27 /* DMA Controller */ | ||
49 | #define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */ | ||
50 | #define AT91CAP9_ID_UHP 29 /* USB Host Port */ | ||
51 | #define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ | ||
52 | #define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ | ||
53 | |||
54 | /* | ||
55 | * User Peripheral physical base addresses. | ||
56 | */ | ||
57 | #define AT91CAP9_BASE_UDPHS 0xfff78000 | ||
58 | #define AT91CAP9_BASE_TCB0 0xfff7c000 | ||
59 | #define AT91CAP9_BASE_TC0 0xfff7c000 | ||
60 | #define AT91CAP9_BASE_TC1 0xfff7c040 | ||
61 | #define AT91CAP9_BASE_TC2 0xfff7c080 | ||
62 | #define AT91CAP9_BASE_MCI0 0xfff80000 | ||
63 | #define AT91CAP9_BASE_MCI1 0xfff84000 | ||
64 | #define AT91CAP9_BASE_TWI 0xfff88000 | ||
65 | #define AT91CAP9_BASE_US0 0xfff8c000 | ||
66 | #define AT91CAP9_BASE_US1 0xfff90000 | ||
67 | #define AT91CAP9_BASE_US2 0xfff94000 | ||
68 | #define AT91CAP9_BASE_SSC0 0xfff98000 | ||
69 | #define AT91CAP9_BASE_SSC1 0xfff9c000 | ||
70 | #define AT91CAP9_BASE_AC97C 0xfffa0000 | ||
71 | #define AT91CAP9_BASE_SPI0 0xfffa4000 | ||
72 | #define AT91CAP9_BASE_SPI1 0xfffa8000 | ||
73 | #define AT91CAP9_BASE_CAN 0xfffac000 | ||
74 | #define AT91CAP9_BASE_PWMC 0xfffb8000 | ||
75 | #define AT91CAP9_BASE_EMAC 0xfffbc000 | ||
76 | #define AT91CAP9_BASE_ADC 0xfffc0000 | ||
77 | #define AT91CAP9_BASE_ISI 0xfffc4000 | ||
78 | |||
79 | /* | ||
80 | * System Peripherals (offset from AT91_BASE_SYS) | ||
81 | */ | ||
82 | #define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) | ||
83 | #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) | ||
84 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) | ||
85 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
86 | #define AT91_GPBR (cpu_is_at91cap9_revB() ? \ | ||
87 | (0xfffffd50 - AT91_BASE_SYS) : \ | ||
88 | (0xfffffd60 - AT91_BASE_SYS)) | ||
89 | |||
90 | #define AT91CAP9_BASE_ECC 0xffffe200 | ||
91 | #define AT91CAP9_BASE_DMA 0xffffec00 | ||
92 | #define AT91CAP9_BASE_SMC 0xffffe800 | ||
93 | #define AT91CAP9_BASE_DBGU AT91_BASE_DBGU1 | ||
94 | #define AT91CAP9_BASE_PIOA 0xfffff200 | ||
95 | #define AT91CAP9_BASE_PIOB 0xfffff400 | ||
96 | #define AT91CAP9_BASE_PIOC 0xfffff600 | ||
97 | #define AT91CAP9_BASE_PIOD 0xfffff800 | ||
98 | #define AT91CAP9_BASE_RSTC 0xfffffd00 | ||
99 | #define AT91CAP9_BASE_SHDWC 0xfffffd10 | ||
100 | #define AT91CAP9_BASE_RTT 0xfffffd20 | ||
101 | #define AT91CAP9_BASE_PIT 0xfffffd30 | ||
102 | #define AT91CAP9_BASE_WDT 0xfffffd40 | ||
103 | |||
104 | #define AT91_USART0 AT91CAP9_BASE_US0 | ||
105 | #define AT91_USART1 AT91CAP9_BASE_US1 | ||
106 | #define AT91_USART2 AT91CAP9_BASE_US2 | ||
107 | |||
108 | |||
109 | /* | ||
110 | * Internal Memory. | ||
111 | */ | ||
112 | #define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */ | ||
113 | #define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */ | ||
114 | |||
115 | #define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */ | ||
116 | #define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */ | ||
117 | |||
118 | #define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */ | ||
119 | #define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */ | ||
120 | #define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */ | ||
121 | |||
122 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_matrix.h b/arch/arm/mach-at91/include/mach/at91cap9_matrix.h deleted file mode 100644 index 4b9d4aff4b4f..000000000000 --- a/arch/arm/mach-at91/include/mach/at91cap9_matrix.h +++ /dev/null | |||
@@ -1,137 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-at91/include/mach/at91cap9_matrix.h | ||
3 | * | ||
4 | * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> | ||
5 | * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> | ||
6 | * Copyright (C) 2006 Atmel Corporation. | ||
7 | * | ||
8 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
9 | * Based on AT91CAP9 datasheet revision B (Preliminary). | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License as published by | ||
13 | * the Free Software Foundation; either version 2 of the License, or | ||
14 | * (at your option) any later version. | ||
15 | */ | ||
16 | |||
17 | #ifndef AT91CAP9_MATRIX_H | ||
18 | #define AT91CAP9_MATRIX_H | ||
19 | |||
20 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
21 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
22 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
23 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
24 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
25 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ | ||
26 | #define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ | ||
27 | #define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ | ||
28 | #define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ | ||
29 | #define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ | ||
30 | #define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ | ||
31 | #define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ | ||
32 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
33 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
34 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
35 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
36 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
37 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
38 | |||
39 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
40 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
41 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
42 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
43 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
44 | #define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ | ||
45 | #define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ | ||
46 | #define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ | ||
47 | #define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */ | ||
48 | #define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */ | ||
49 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
50 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
51 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
52 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
53 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
54 | #define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ | ||
55 | #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ | ||
56 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | ||
57 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | ||
58 | |||
59 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
60 | #define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ | ||
61 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
62 | #define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ | ||
63 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
64 | #define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ | ||
65 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
66 | #define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ | ||
67 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
68 | #define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ | ||
69 | #define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ | ||
70 | #define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ | ||
71 | #define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ | ||
72 | #define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ | ||
73 | #define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ | ||
74 | #define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ | ||
75 | #define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */ | ||
76 | #define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */ | ||
77 | #define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */ | ||
78 | #define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */ | ||
79 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
80 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
81 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
82 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
83 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
84 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
85 | #define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ | ||
86 | #define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ | ||
87 | #define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ | ||
88 | #define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ | ||
89 | #define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ | ||
90 | #define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ | ||
91 | |||
92 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
93 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
94 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
95 | #define AT91_MATRIX_RCB2 (1 << 2) | ||
96 | #define AT91_MATRIX_RCB3 (1 << 3) | ||
97 | #define AT91_MATRIX_RCB4 (1 << 4) | ||
98 | #define AT91_MATRIX_RCB5 (1 << 5) | ||
99 | #define AT91_MATRIX_RCB6 (1 << 6) | ||
100 | #define AT91_MATRIX_RCB7 (1 << 7) | ||
101 | #define AT91_MATRIX_RCB8 (1 << 8) | ||
102 | #define AT91_MATRIX_RCB9 (1 << 9) | ||
103 | #define AT91_MATRIX_RCB10 (1 << 10) | ||
104 | #define AT91_MATRIX_RCB11 (1 << 11) | ||
105 | |||
106 | #define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */ | ||
107 | #define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */ | ||
108 | |||
109 | #define AT91_MATRIX_UDPHS (AT91_MATRIX + 0x118) /* USBHS Special Function Register [AT91CAP9 only] */ | ||
110 | #define AT91_MATRIX_SELECT_UDPHS (0 << 31) /* select High Speed UDP */ | ||
111 | #define AT91_MATRIX_SELECT_UDP (1 << 31) /* select standard UDP */ | ||
112 | #define AT91_MATRIX_UDPHS_BYPASS_LOCK (1 << 30) /* bypass lock bit */ | ||
113 | |||
114 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */ | ||
115 | #define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
116 | #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) | ||
117 | #define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1) | ||
118 | #define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
119 | #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) | ||
120 | #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
121 | #define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
122 | #define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) | ||
123 | #define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4) | ||
124 | #define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
125 | #define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) | ||
126 | #define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5) | ||
127 | #define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
128 | #define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */ | ||
129 | #define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
130 | #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) | ||
131 | #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) | ||
132 | |||
133 | #define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */ | ||
134 | #define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */ | ||
135 | #define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */ | ||
136 | |||
137 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h index e2f8da8ce5bc..5d4a9f846584 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h | |||
@@ -59,7 +59,6 @@ | |||
59 | #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ | 59 | #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ |
60 | #define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ | 60 | #define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ |
61 | #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ | 61 | #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ |
62 | #define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ | ||
63 | #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */ | 62 | #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */ |
64 | #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ | 63 | #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ |
65 | 64 | ||
@@ -76,7 +75,6 @@ | |||
76 | #define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ | 75 | #define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ |
77 | 76 | ||
78 | #define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ | 77 | #define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ |
79 | #define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */ | ||
80 | #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ | 78 | #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ |
81 | #define AT91_DDRSDRC_LPCB_DISABLE 0 | 79 | #define AT91_DDRSDRC_LPCB_DISABLE 0 |
82 | #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 | 80 | #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 |
@@ -94,11 +92,9 @@ | |||
94 | #define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ | 92 | #define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ |
95 | 93 | ||
96 | #define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ | 94 | #define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ |
97 | #define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */ | ||
98 | #define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ | 95 | #define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ |
99 | #define AT91_DDRSDRC_MD_SDR 0 | 96 | #define AT91_DDRSDRC_MD_SDR 0 |
100 | #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 | 97 | #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 |
101 | #define AT91CAP9_DDRSDRC_MD_DDR 2 | ||
102 | #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 | 98 | #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 |
103 | #define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ | 99 | #define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ |
104 | #define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ | 100 | #define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ |
@@ -106,16 +102,10 @@ | |||
106 | #define AT91_DDRSDRC_DBW_16BITS (1 << 4) | 102 | #define AT91_DDRSDRC_DBW_16BITS (1 << 4) |
107 | 103 | ||
108 | #define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ | 104 | #define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ |
109 | #define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */ | ||
110 | #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ | 105 | #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ |
111 | #define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ | 106 | #define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ |
112 | #define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ | 107 | #define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ |
113 | #define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */ | ||
114 | #define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */ | ||
115 | #define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */ | ||
116 | #define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ | 108 | #define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ |
117 | #define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ | ||
118 | #define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ | ||
119 | 109 | ||
120 | #define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */ | 110 | #define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */ |
121 | #define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ | 111 | #define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ |
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h index 3b33f07b1e11..dc8d6d4f17cf 100644 --- a/arch/arm/mach-at91/include/mach/board.h +++ b/arch/arm/mach-at91/include/mach/board.h | |||
@@ -107,6 +107,8 @@ struct atmel_nand_data { | |||
107 | u8 ale; /* address line number connected to ALE */ | 107 | u8 ale; /* address line number connected to ALE */ |
108 | u8 cle; /* address line number connected to CLE */ | 108 | u8 cle; /* address line number connected to CLE */ |
109 | u8 bus_width_16; /* buswidth is 16 bit */ | 109 | u8 bus_width_16; /* buswidth is 16 bit */ |
110 | u8 correction_cap; /* PMECC correction capability */ | ||
111 | u16 sector_size; /* Sector size for PMECC */ | ||
110 | struct mtd_partition *parts; | 112 | struct mtd_partition *parts; |
111 | unsigned int num_parts; | 113 | unsigned int num_parts; |
112 | }; | 114 | }; |
@@ -179,7 +181,9 @@ extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data); | |||
179 | extern void __init at91_add_device_ac97(struct ac97c_platform_data *data); | 181 | extern void __init at91_add_device_ac97(struct ac97c_platform_data *data); |
180 | 182 | ||
181 | /* ISI */ | 183 | /* ISI */ |
182 | extern void __init at91_add_device_isi(void); | 184 | struct isi_platform_data; |
185 | extern void __init at91_add_device_isi(struct isi_platform_data *data, | ||
186 | bool use_pck_as_mck); | ||
183 | 187 | ||
184 | /* Touchscreen Controller */ | 188 | /* Touchscreen Controller */ |
185 | struct at91_tsadcc_data { | 189 | struct at91_tsadcc_data { |
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index f6ce936dba2b..0118c3338552 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h | |||
@@ -25,7 +25,6 @@ | |||
25 | #define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */ | 25 | #define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */ |
26 | #define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ | 26 | #define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ |
27 | #define ARCH_ID_AT91SAM9X5 0x819a05a0 | 27 | #define ARCH_ID_AT91SAM9X5 0x819a05a0 |
28 | #define ARCH_ID_AT91CAP9 0x039A03A0 | ||
29 | 28 | ||
30 | #define ARCH_ID_AT91SAM9XE128 0x329973a0 | 29 | #define ARCH_ID_AT91SAM9XE128 0x329973a0 |
31 | #define ARCH_ID_AT91SAM9XE256 0x329a93a0 | 30 | #define ARCH_ID_AT91SAM9XE256 0x329a93a0 |
@@ -51,10 +50,6 @@ | |||
51 | #define ARCH_FAMILY_AT91SAM9 0x01900000 | 50 | #define ARCH_FAMILY_AT91SAM9 0x01900000 |
52 | #define ARCH_FAMILY_AT91SAM9XE 0x02900000 | 51 | #define ARCH_FAMILY_AT91SAM9XE 0x02900000 |
53 | 52 | ||
54 | /* PMC revision */ | ||
55 | #define ARCH_REVISION_CAP9_B 0x399 | ||
56 | #define ARCH_REVISION_CAP9_C 0x601 | ||
57 | |||
58 | /* RM9200 type */ | 53 | /* RM9200 type */ |
59 | #define ARCH_REVISON_9200_BGA (0 << 0) | 54 | #define ARCH_REVISON_9200_BGA (0 << 0) |
60 | #define ARCH_REVISON_9200_PQFP (1 << 0) | 55 | #define ARCH_REVISON_9200_PQFP (1 << 0) |
@@ -63,9 +58,6 @@ enum at91_soc_type { | |||
63 | /* 920T */ | 58 | /* 920T */ |
64 | AT91_SOC_RM9200, | 59 | AT91_SOC_RM9200, |
65 | 60 | ||
66 | /* CAP */ | ||
67 | AT91_SOC_CAP9, | ||
68 | |||
69 | /* SAM92xx */ | 61 | /* SAM92xx */ |
70 | AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263, | 62 | AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263, |
71 | 63 | ||
@@ -86,9 +78,6 @@ enum at91_soc_subtype { | |||
86 | /* RM9200 */ | 78 | /* RM9200 */ |
87 | AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP, | 79 | AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP, |
88 | 80 | ||
89 | /* CAP9 */ | ||
90 | AT91_SOC_CAP9_REV_B, AT91_SOC_CAP9_REV_C, | ||
91 | |||
92 | /* SAM9260 */ | 81 | /* SAM9260 */ |
93 | AT91_SOC_SAM9XE, | 82 | AT91_SOC_SAM9XE, |
94 | 83 | ||
@@ -195,16 +184,6 @@ static inline int at91_soc_is_detected(void) | |||
195 | #define cpu_is_at91sam9x25() (0) | 184 | #define cpu_is_at91sam9x25() (0) |
196 | #endif | 185 | #endif |
197 | 186 | ||
198 | #ifdef CONFIG_ARCH_AT91CAP9 | ||
199 | #define cpu_is_at91cap9() (at91_soc_initdata.type == AT91_SOC_CAP9) | ||
200 | #define cpu_is_at91cap9_revB() (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_B) | ||
201 | #define cpu_is_at91cap9_revC() (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_C) | ||
202 | #else | ||
203 | #define cpu_is_at91cap9() (0) | ||
204 | #define cpu_is_at91cap9_revB() (0) | ||
205 | #define cpu_is_at91cap9_revC() (0) | ||
206 | #endif | ||
207 | |||
208 | /* | 187 | /* |
209 | * Since this is ARM, we will never run on any AVR32 CPU. But these | 188 | * Since this is ARM, we will never run on any AVR32 CPU. But these |
210 | * definitions may reduce clutter in common drivers. | 189 | * definitions may reduce clutter in common drivers. |
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index 2d0e4e998566..c213f28628c0 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h | |||
@@ -19,7 +19,7 @@ | |||
19 | /* DBGU base */ | 19 | /* DBGU base */ |
20 | /* rm9200, 9260/9g20, 9261/9g10, 9rl */ | 20 | /* rm9200, 9260/9g20, 9261/9g10, 9rl */ |
21 | #define AT91_BASE_DBGU0 0xfffff200 | 21 | #define AT91_BASE_DBGU0 0xfffff200 |
22 | /* 9263, 9g45, cap9 */ | 22 | /* 9263, 9g45 */ |
23 | #define AT91_BASE_DBGU1 0xffffee00 | 23 | #define AT91_BASE_DBGU1 0xffffee00 |
24 | 24 | ||
25 | #if defined(CONFIG_ARCH_AT91RM9200) | 25 | #if defined(CONFIG_ARCH_AT91RM9200) |
@@ -34,8 +34,6 @@ | |||
34 | #include <mach/at91sam9rl.h> | 34 | #include <mach/at91sam9rl.h> |
35 | #elif defined(CONFIG_ARCH_AT91SAM9G45) | 35 | #elif defined(CONFIG_ARCH_AT91SAM9G45) |
36 | #include <mach/at91sam9g45.h> | 36 | #include <mach/at91sam9g45.h> |
37 | #elif defined(CONFIG_ARCH_AT91CAP9) | ||
38 | #include <mach/at91cap9.h> | ||
39 | #elif defined(CONFIG_ARCH_AT91X40) | 37 | #elif defined(CONFIG_ARCH_AT91X40) |
40 | #include <mach/at91x40.h> | 38 | #include <mach/at91x40.h> |
41 | #else | 39 | #else |