diff options
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h')
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h index e2f8da8ce5bc..5d4a9f846584 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h | |||
@@ -59,7 +59,6 @@ | |||
59 | #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ | 59 | #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ |
60 | #define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ | 60 | #define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ |
61 | #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ | 61 | #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ |
62 | #define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ | ||
63 | #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */ | 62 | #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */ |
64 | #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ | 63 | #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ |
65 | 64 | ||
@@ -76,7 +75,6 @@ | |||
76 | #define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ | 75 | #define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ |
77 | 76 | ||
78 | #define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ | 77 | #define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ |
79 | #define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */ | ||
80 | #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ | 78 | #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ |
81 | #define AT91_DDRSDRC_LPCB_DISABLE 0 | 79 | #define AT91_DDRSDRC_LPCB_DISABLE 0 |
82 | #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 | 80 | #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 |
@@ -94,11 +92,9 @@ | |||
94 | #define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ | 92 | #define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ |
95 | 93 | ||
96 | #define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ | 94 | #define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ |
97 | #define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */ | ||
98 | #define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ | 95 | #define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ |
99 | #define AT91_DDRSDRC_MD_SDR 0 | 96 | #define AT91_DDRSDRC_MD_SDR 0 |
100 | #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 | 97 | #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 |
101 | #define AT91CAP9_DDRSDRC_MD_DDR 2 | ||
102 | #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 | 98 | #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 |
103 | #define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ | 99 | #define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ |
104 | #define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ | 100 | #define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ |
@@ -106,16 +102,10 @@ | |||
106 | #define AT91_DDRSDRC_DBW_16BITS (1 << 4) | 102 | #define AT91_DDRSDRC_DBW_16BITS (1 << 4) |
107 | 103 | ||
108 | #define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ | 104 | #define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ |
109 | #define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */ | ||
110 | #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ | 105 | #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ |
111 | #define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ | 106 | #define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ |
112 | #define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ | 107 | #define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ |
113 | #define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */ | ||
114 | #define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */ | ||
115 | #define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */ | ||
116 | #define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ | 108 | #define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ |
117 | #define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ | ||
118 | #define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ | ||
119 | 109 | ||
120 | #define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */ | 110 | #define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */ |
121 | #define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ | 111 | #define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ |