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Diffstat (limited to 'arch/arm/mach-at91/at91sam926x_time.c')
-rw-r--r--arch/arm/mach-at91/at91sam926x_time.c294
1 files changed, 0 insertions, 294 deletions
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
deleted file mode 100644
index 0a9e2fc8f796..000000000000
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ /dev/null
@@ -1,294 +0,0 @@
1/*
2 * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
3 *
4 * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
5 * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
6 * Converted to ClockSource/ClockEvents by David Brownell.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/interrupt.h>
13#include <linux/irq.h>
14#include <linux/kernel.h>
15#include <linux/clk.h>
16#include <linux/clockchips.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20
21#include <asm/mach/time.h>
22#include <mach/hardware.h>
23
24#define AT91_PIT_MR 0x00 /* Mode Register */
25#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
26#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
27#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
28
29#define AT91_PIT_SR 0x04 /* Status Register */
30#define AT91_PIT_PITS (1 << 0) /* Timer Status */
31
32#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
33#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
34#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
35#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
36
37#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
38#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
39
40static u32 pit_cycle; /* write-once */
41static u32 pit_cnt; /* access only w/system irq blocked */
42static void __iomem *pit_base_addr __read_mostly;
43static struct clk *mck;
44
45static inline unsigned int pit_read(unsigned int reg_offset)
46{
47 return __raw_readl(pit_base_addr + reg_offset);
48}
49
50static inline void pit_write(unsigned int reg_offset, unsigned long value)
51{
52 __raw_writel(value, pit_base_addr + reg_offset);
53}
54
55/*
56 * Clocksource: just a monotonic counter of MCK/16 cycles.
57 * We don't care whether or not PIT irqs are enabled.
58 */
59static cycle_t read_pit_clk(struct clocksource *cs)
60{
61 unsigned long flags;
62 u32 elapsed;
63 u32 t;
64
65 raw_local_irq_save(flags);
66 elapsed = pit_cnt;
67 t = pit_read(AT91_PIT_PIIR);
68 raw_local_irq_restore(flags);
69
70 elapsed += PIT_PICNT(t) * pit_cycle;
71 elapsed += PIT_CPIV(t);
72 return elapsed;
73}
74
75static struct clocksource pit_clk = {
76 .name = "pit",
77 .rating = 175,
78 .read = read_pit_clk,
79 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
80};
81
82
83/*
84 * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
85 */
86static void
87pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
88{
89 switch (mode) {
90 case CLOCK_EVT_MODE_PERIODIC:
91 /* update clocksource counter */
92 pit_cnt += pit_cycle * PIT_PICNT(pit_read(AT91_PIT_PIVR));
93 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
94 | AT91_PIT_PITIEN);
95 break;
96 case CLOCK_EVT_MODE_ONESHOT:
97 BUG();
98 /* FALLTHROUGH */
99 case CLOCK_EVT_MODE_SHUTDOWN:
100 case CLOCK_EVT_MODE_UNUSED:
101 /* disable irq, leaving the clocksource active */
102 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
103 break;
104 case CLOCK_EVT_MODE_RESUME:
105 break;
106 }
107}
108
109static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
110{
111 /* Disable timer */
112 pit_write(AT91_PIT_MR, 0);
113}
114
115static void at91sam926x_pit_reset(void)
116{
117 /* Disable timer and irqs */
118 pit_write(AT91_PIT_MR, 0);
119
120 /* Clear any pending interrupts, wait for PIT to stop counting */
121 while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0)
122 cpu_relax();
123
124 /* Start PIT but don't enable IRQ */
125 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
126}
127
128static void at91sam926x_pit_resume(struct clock_event_device *cedev)
129{
130 at91sam926x_pit_reset();
131}
132
133static struct clock_event_device pit_clkevt = {
134 .name = "pit",
135 .features = CLOCK_EVT_FEAT_PERIODIC,
136 .shift = 32,
137 .rating = 100,
138 .set_mode = pit_clkevt_mode,
139 .suspend = at91sam926x_pit_suspend,
140 .resume = at91sam926x_pit_resume,
141};
142
143
144/*
145 * IRQ handler for the timer.
146 */
147static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
148{
149 /*
150 * irqs should be disabled here, but as the irq is shared they are only
151 * guaranteed to be off if the timer irq is registered first.
152 */
153 WARN_ON_ONCE(!irqs_disabled());
154
155 /* The PIT interrupt may be disabled, and is shared */
156 if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
157 && (pit_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
158 unsigned nr_ticks;
159
160 /* Get number of ticks performed before irq, and ack it */
161 nr_ticks = PIT_PICNT(pit_read(AT91_PIT_PIVR));
162 do {
163 pit_cnt += pit_cycle;
164 pit_clkevt.event_handler(&pit_clkevt);
165 nr_ticks--;
166 } while (nr_ticks);
167
168 return IRQ_HANDLED;
169 }
170
171 return IRQ_NONE;
172}
173
174static struct irqaction at91sam926x_pit_irq = {
175 .name = "at91_tick",
176 .flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
177 .handler = at91sam926x_pit_interrupt,
178 .irq = NR_IRQS_LEGACY + AT91_ID_SYS,
179};
180
181#ifdef CONFIG_OF
182static struct of_device_id pit_timer_ids[] = {
183 { .compatible = "atmel,at91sam9260-pit" },
184 { /* sentinel */ }
185};
186
187static int __init of_at91sam926x_pit_init(void)
188{
189 struct device_node *np;
190 int ret;
191
192 np = of_find_matching_node(NULL, pit_timer_ids);
193 if (!np)
194 goto err;
195
196 pit_base_addr = of_iomap(np, 0);
197 if (!pit_base_addr)
198 goto node_err;
199
200 mck = of_clk_get(np, 0);
201
202 /* Get the interrupts property */
203 ret = irq_of_parse_and_map(np, 0);
204 if (!ret) {
205 pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
206 if (!IS_ERR(mck))
207 clk_put(mck);
208 goto ioremap_err;
209 }
210 at91sam926x_pit_irq.irq = ret;
211
212 of_node_put(np);
213
214 return 0;
215
216ioremap_err:
217 iounmap(pit_base_addr);
218node_err:
219 of_node_put(np);
220err:
221 return -EINVAL;
222}
223#else
224static int __init of_at91sam926x_pit_init(void)
225{
226 return -EINVAL;
227}
228#endif
229
230/*
231 * Set up both clocksource and clockevent support.
232 */
233void __init at91sam926x_pit_init(void)
234{
235 unsigned long pit_rate;
236 unsigned bits;
237 int ret;
238
239 mck = ERR_PTR(-ENOENT);
240
241 /* For device tree enabled device: initialize here */
242 of_at91sam926x_pit_init();
243
244 /*
245 * Use our actual MCK to figure out how many MCK/16 ticks per
246 * 1/HZ period (instead of a compile-time constant LATCH).
247 */
248 if (IS_ERR(mck))
249 mck = clk_get(NULL, "mck");
250
251 if (IS_ERR(mck))
252 panic("AT91: PIT: Unable to get mck clk\n");
253 pit_rate = clk_get_rate(mck) / 16;
254 pit_cycle = (pit_rate + HZ/2) / HZ;
255 WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
256
257 /* Initialize and enable the timer */
258 at91sam926x_pit_reset();
259
260 /*
261 * Register clocksource. The high order bits of PIV are unused,
262 * so this isn't a 32-bit counter unless we get clockevent irqs.
263 */
264 bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
265 pit_clk.mask = CLOCKSOURCE_MASK(bits);
266 clocksource_register_hz(&pit_clk, pit_rate);
267
268 /* Set up irq handler */
269 ret = setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
270 if (ret)
271 pr_crit("AT91: PIT: Unable to setup IRQ\n");
272
273 /* Set up and register clockevents */
274 pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
275 pit_clkevt.cpumask = cpumask_of(0);
276 clockevents_register_device(&pit_clkevt);
277}
278
279void __init at91sam926x_ioremap_pit(u32 addr)
280{
281#if defined(CONFIG_OF)
282 struct device_node *np =
283 of_find_matching_node(NULL, pit_timer_ids);
284
285 if (np) {
286 of_node_put(np);
287 return;
288 }
289#endif
290 pit_base_addr = ioremap(addr, 16);
291
292 if (!pit_base_addr)
293 panic("Impossible to ioremap PIT\n");
294}
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