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-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c1538
1 files changed, 0 insertions, 1538 deletions
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
deleted file mode 100644
index cef0e2f57068..000000000000
--- a/arch/arm/mach-at91/at91sam9263_devices.c
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@@ -1,1538 +0,0 @@
1/*
2 * arch/arm/mach-at91/at91sam9263_devices.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17#include <linux/platform_device.h>
18#include <linux/i2c-gpio.h>
19
20#include <linux/fb.h>
21#include <video/atmel_lcdc.h>
22
23#include <mach/at91sam9263.h>
24#include <mach/at91sam9263_matrix.h>
25#include <mach/at91_matrix.h>
26#include <mach/at91sam9_smc.h>
27#include <mach/hardware.h>
28
29#include "board.h"
30#include "generic.h"
31#include "gpio.h"
32
33
34/* --------------------------------------------------------------------
35 * USB Host
36 * -------------------------------------------------------------------- */
37
38#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
39static u64 ohci_dmamask = DMA_BIT_MASK(32);
40static struct at91_usbh_data usbh_data;
41
42static struct resource usbh_resources[] = {
43 [0] = {
44 .start = AT91SAM9263_UHP_BASE,
45 .end = AT91SAM9263_UHP_BASE + SZ_1M - 1,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP,
50 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55static struct platform_device at91_usbh_device = {
56 .name = "at91_ohci",
57 .id = -1,
58 .dev = {
59 .dma_mask = &ohci_dmamask,
60 .coherent_dma_mask = DMA_BIT_MASK(32),
61 .platform_data = &usbh_data,
62 },
63 .resource = usbh_resources,
64 .num_resources = ARRAY_SIZE(usbh_resources),
65};
66
67void __init at91_add_device_usbh(struct at91_usbh_data *data)
68{
69 int i;
70
71 if (!data)
72 return;
73
74 /* Enable VBus control for UHP ports */
75 for (i = 0; i < data->ports; i++) {
76 if (gpio_is_valid(data->vbus_pin[i]))
77 at91_set_gpio_output(data->vbus_pin[i],
78 data->vbus_pin_active_low[i]);
79 }
80
81 /* Enable overcurrent notification */
82 for (i = 0; i < data->ports; i++) {
83 if (gpio_is_valid(data->overcurrent_pin[i]))
84 at91_set_gpio_input(data->overcurrent_pin[i], 1);
85 }
86
87 usbh_data = *data;
88 platform_device_register(&at91_usbh_device);
89}
90#else
91void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
92#endif
93
94
95/* --------------------------------------------------------------------
96 * USB Device (Gadget)
97 * -------------------------------------------------------------------- */
98
99#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
100static struct at91_udc_data udc_data;
101
102static struct resource udc_resources[] = {
103 [0] = {
104 .start = AT91SAM9263_BASE_UDP,
105 .end = AT91SAM9263_BASE_UDP + SZ_16K - 1,
106 .flags = IORESOURCE_MEM,
107 },
108 [1] = {
109 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP,
110 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP,
111 .flags = IORESOURCE_IRQ,
112 },
113};
114
115static struct platform_device at91_udc_device = {
116 .name = "at91_udc",
117 .id = -1,
118 .dev = {
119 .platform_data = &udc_data,
120 },
121 .resource = udc_resources,
122 .num_resources = ARRAY_SIZE(udc_resources),
123};
124
125void __init at91_add_device_udc(struct at91_udc_data *data)
126{
127 if (!data)
128 return;
129
130 if (gpio_is_valid(data->vbus_pin)) {
131 at91_set_gpio_input(data->vbus_pin, 0);
132 at91_set_deglitch(data->vbus_pin, 1);
133 }
134
135 /* Pullup pin is handled internally by USB device peripheral */
136
137 udc_data = *data;
138 platform_device_register(&at91_udc_device);
139}
140#else
141void __init at91_add_device_udc(struct at91_udc_data *data) {}
142#endif
143
144
145/* --------------------------------------------------------------------
146 * Ethernet
147 * -------------------------------------------------------------------- */
148
149#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
150static u64 eth_dmamask = DMA_BIT_MASK(32);
151static struct macb_platform_data eth_data;
152
153static struct resource eth_resources[] = {
154 [0] = {
155 .start = AT91SAM9263_BASE_EMAC,
156 .end = AT91SAM9263_BASE_EMAC + SZ_16K - 1,
157 .flags = IORESOURCE_MEM,
158 },
159 [1] = {
160 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC,
161 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC,
162 .flags = IORESOURCE_IRQ,
163 },
164};
165
166static struct platform_device at91sam9263_eth_device = {
167 .name = "macb",
168 .id = -1,
169 .dev = {
170 .dma_mask = &eth_dmamask,
171 .coherent_dma_mask = DMA_BIT_MASK(32),
172 .platform_data = &eth_data,
173 },
174 .resource = eth_resources,
175 .num_resources = ARRAY_SIZE(eth_resources),
176};
177
178void __init at91_add_device_eth(struct macb_platform_data *data)
179{
180 if (!data)
181 return;
182
183 if (gpio_is_valid(data->phy_irq_pin)) {
184 at91_set_gpio_input(data->phy_irq_pin, 0);
185 at91_set_deglitch(data->phy_irq_pin, 1);
186 }
187
188 /* Pins used for MII and RMII */
189 at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
190 at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
191 at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
192 at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
193 at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
194 at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
195 at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
196 at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
197 at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
198 at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
199
200 if (!data->is_rmii) {
201 at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
202 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
203 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
204 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
205 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
206 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
207 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
208 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
209 }
210
211 eth_data = *data;
212 platform_device_register(&at91sam9263_eth_device);
213}
214#else
215void __init at91_add_device_eth(struct macb_platform_data *data) {}
216#endif
217
218
219/* --------------------------------------------------------------------
220 * MMC / SD
221 * -------------------------------------------------------------------- */
222
223#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
224static u64 mmc_dmamask = DMA_BIT_MASK(32);
225static struct mci_platform_data mmc0_data, mmc1_data;
226
227static struct resource mmc0_resources[] = {
228 [0] = {
229 .start = AT91SAM9263_BASE_MCI0,
230 .end = AT91SAM9263_BASE_MCI0 + SZ_16K - 1,
231 .flags = IORESOURCE_MEM,
232 },
233 [1] = {
234 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0,
235 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0,
236 .flags = IORESOURCE_IRQ,
237 },
238};
239
240static struct platform_device at91sam9263_mmc0_device = {
241 .name = "atmel_mci",
242 .id = 0,
243 .dev = {
244 .dma_mask = &mmc_dmamask,
245 .coherent_dma_mask = DMA_BIT_MASK(32),
246 .platform_data = &mmc0_data,
247 },
248 .resource = mmc0_resources,
249 .num_resources = ARRAY_SIZE(mmc0_resources),
250};
251
252static struct resource mmc1_resources[] = {
253 [0] = {
254 .start = AT91SAM9263_BASE_MCI1,
255 .end = AT91SAM9263_BASE_MCI1 + SZ_16K - 1,
256 .flags = IORESOURCE_MEM,
257 },
258 [1] = {
259 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1,
260 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1,
261 .flags = IORESOURCE_IRQ,
262 },
263};
264
265static struct platform_device at91sam9263_mmc1_device = {
266 .name = "atmel_mci",
267 .id = 1,
268 .dev = {
269 .dma_mask = &mmc_dmamask,
270 .coherent_dma_mask = DMA_BIT_MASK(32),
271 .platform_data = &mmc1_data,
272 },
273 .resource = mmc1_resources,
274 .num_resources = ARRAY_SIZE(mmc1_resources),
275};
276
277void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
278{
279 unsigned int i;
280 unsigned int slot_count = 0;
281
282 if (!data)
283 return;
284
285 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
286
287 if (!data->slot[i].bus_width)
288 continue;
289
290 /* input/irq */
291 if (gpio_is_valid(data->slot[i].detect_pin)) {
292 at91_set_gpio_input(data->slot[i].detect_pin,
293 1);
294 at91_set_deglitch(data->slot[i].detect_pin,
295 1);
296 }
297 if (gpio_is_valid(data->slot[i].wp_pin))
298 at91_set_gpio_input(data->slot[i].wp_pin, 1);
299
300 if (mmc_id == 0) { /* MCI0 */
301 switch (i) {
302 case 0: /* slot A */
303 /* CMD */
304 at91_set_A_periph(AT91_PIN_PA1, 1);
305 /* DAT0, maybe DAT1..DAT3 */
306 at91_set_A_periph(AT91_PIN_PA0, 1);
307 if (data->slot[i].bus_width == 4) {
308 at91_set_A_periph(AT91_PIN_PA3, 1);
309 at91_set_A_periph(AT91_PIN_PA4, 1);
310 at91_set_A_periph(AT91_PIN_PA5, 1);
311 }
312 slot_count++;
313 break;
314 case 1: /* slot B */
315 /* CMD */
316 at91_set_A_periph(AT91_PIN_PA16, 1);
317 /* DAT0, maybe DAT1..DAT3 */
318 at91_set_A_periph(AT91_PIN_PA17, 1);
319 if (data->slot[i].bus_width == 4) {
320 at91_set_A_periph(AT91_PIN_PA18, 1);
321 at91_set_A_periph(AT91_PIN_PA19, 1);
322 at91_set_A_periph(AT91_PIN_PA20, 1);
323 }
324 slot_count++;
325 break;
326 default:
327 printk(KERN_ERR
328 "AT91: SD/MMC slot %d not available\n", i);
329 break;
330 }
331 if (slot_count) {
332 /* CLK */
333 at91_set_A_periph(AT91_PIN_PA12, 0);
334
335 mmc0_data = *data;
336 platform_device_register(&at91sam9263_mmc0_device);
337 }
338 } else if (mmc_id == 1) { /* MCI1 */
339 switch (i) {
340 case 0: /* slot A */
341 /* CMD */
342 at91_set_A_periph(AT91_PIN_PA7, 1);
343 /* DAT0, maybe DAT1..DAT3 */
344 at91_set_A_periph(AT91_PIN_PA8, 1);
345 if (data->slot[i].bus_width == 4) {
346 at91_set_A_periph(AT91_PIN_PA9, 1);
347 at91_set_A_periph(AT91_PIN_PA10, 1);
348 at91_set_A_periph(AT91_PIN_PA11, 1);
349 }
350 slot_count++;
351 break;
352 case 1: /* slot B */
353 /* CMD */
354 at91_set_A_periph(AT91_PIN_PA21, 1);
355 /* DAT0, maybe DAT1..DAT3 */
356 at91_set_A_periph(AT91_PIN_PA22, 1);
357 if (data->slot[i].bus_width == 4) {
358 at91_set_A_periph(AT91_PIN_PA23, 1);
359 at91_set_A_periph(AT91_PIN_PA24, 1);
360 at91_set_A_periph(AT91_PIN_PA25, 1);
361 }
362 slot_count++;
363 break;
364 default:
365 printk(KERN_ERR
366 "AT91: SD/MMC slot %d not available\n", i);
367 break;
368 }
369 if (slot_count) {
370 /* CLK */
371 at91_set_A_periph(AT91_PIN_PA6, 0);
372
373 mmc1_data = *data;
374 platform_device_register(&at91sam9263_mmc1_device);
375 }
376 }
377 }
378}
379#else
380void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
381#endif
382
383/* --------------------------------------------------------------------
384 * Compact Flash (PCMCIA or IDE)
385 * -------------------------------------------------------------------- */
386
387#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
388 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
389
390static struct at91_cf_data cf0_data;
391
392static struct resource cf0_resources[] = {
393 [0] = {
394 .start = AT91_CHIPSELECT_4,
395 .end = AT91_CHIPSELECT_4 + SZ_256M - 1,
396 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
397 }
398};
399
400static struct platform_device cf0_device = {
401 .id = 0,
402 .dev = {
403 .platform_data = &cf0_data,
404 },
405 .resource = cf0_resources,
406 .num_resources = ARRAY_SIZE(cf0_resources),
407};
408
409static struct at91_cf_data cf1_data;
410
411static struct resource cf1_resources[] = {
412 [0] = {
413 .start = AT91_CHIPSELECT_5,
414 .end = AT91_CHIPSELECT_5 + SZ_256M - 1,
415 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
416 }
417};
418
419static struct platform_device cf1_device = {
420 .id = 1,
421 .dev = {
422 .platform_data = &cf1_data,
423 },
424 .resource = cf1_resources,
425 .num_resources = ARRAY_SIZE(cf1_resources),
426};
427
428void __init at91_add_device_cf(struct at91_cf_data *data)
429{
430 unsigned long ebi0_csa;
431 struct platform_device *pdev;
432
433 if (!data)
434 return;
435
436 /*
437 * assign CS4 or CS5 to SMC with Compact Flash logic support,
438 * we assume SMC timings are configured by board code,
439 * except True IDE where timings are controlled by driver
440 */
441 ebi0_csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
442 switch (data->chipselect) {
443 case 4:
444 at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
445 ebi0_csa |= AT91_MATRIX_EBI0_CS4A_SMC_CF1;
446 cf0_data = *data;
447 pdev = &cf0_device;
448 break;
449 case 5:
450 at91_set_A_periph(AT91_PIN_PD7, 0); /* EBI0_NCS5/CFCS1 */
451 ebi0_csa |= AT91_MATRIX_EBI0_CS5A_SMC_CF2;
452 cf1_data = *data;
453 pdev = &cf1_device;
454 break;
455 default:
456 printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
457 data->chipselect);
458 return;
459 }
460 at91_matrix_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
461
462 if (gpio_is_valid(data->det_pin)) {
463 at91_set_gpio_input(data->det_pin, 1);
464 at91_set_deglitch(data->det_pin, 1);
465 }
466
467 if (gpio_is_valid(data->irq_pin)) {
468 at91_set_gpio_input(data->irq_pin, 1);
469 at91_set_deglitch(data->irq_pin, 1);
470 }
471
472 if (gpio_is_valid(data->vcc_pin))
473 /* initially off */
474 at91_set_gpio_output(data->vcc_pin, 0);
475
476 /* enable EBI controlled pins */
477 at91_set_A_periph(AT91_PIN_PD5, 1); /* NWAIT */
478 at91_set_A_periph(AT91_PIN_PD8, 0); /* CFCE1 */
479 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */
480 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
481
482 pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "pata_at91" : "at91_cf";
483 platform_device_register(pdev);
484}
485#else
486void __init at91_add_device_cf(struct at91_cf_data *data) {}
487#endif
488
489/* --------------------------------------------------------------------
490 * NAND / SmartMedia
491 * -------------------------------------------------------------------- */
492
493#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
494static struct atmel_nand_data nand_data;
495
496#define NAND_BASE AT91_CHIPSELECT_3
497
498static struct resource nand_resources[] = {
499 [0] = {
500 .start = NAND_BASE,
501 .end = NAND_BASE + SZ_256M - 1,
502 .flags = IORESOURCE_MEM,
503 },
504 [1] = {
505 .start = AT91SAM9263_BASE_ECC0,
506 .end = AT91SAM9263_BASE_ECC0 + SZ_512 - 1,
507 .flags = IORESOURCE_MEM,
508 }
509};
510
511static struct platform_device at91sam9263_nand_device = {
512 .name = "atmel_nand",
513 .id = -1,
514 .dev = {
515 .platform_data = &nand_data,
516 },
517 .resource = nand_resources,
518 .num_resources = ARRAY_SIZE(nand_resources),
519};
520
521void __init at91_add_device_nand(struct atmel_nand_data *data)
522{
523 unsigned long csa;
524
525 if (!data)
526 return;
527
528 csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
529 at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
530
531 /* enable pin */
532 if (gpio_is_valid(data->enable_pin))
533 at91_set_gpio_output(data->enable_pin, 1);
534
535 /* ready/busy pin */
536 if (gpio_is_valid(data->rdy_pin))
537 at91_set_gpio_input(data->rdy_pin, 1);
538
539 /* card detect pin */
540 if (gpio_is_valid(data->det_pin))
541 at91_set_gpio_input(data->det_pin, 1);
542
543 nand_data = *data;
544 platform_device_register(&at91sam9263_nand_device);
545}
546#else
547void __init at91_add_device_nand(struct atmel_nand_data *data) {}
548#endif
549
550
551/* --------------------------------------------------------------------
552 * TWI (i2c)
553 * -------------------------------------------------------------------- */
554
555/*
556 * Prefer the GPIO code since the TWI controller isn't robust
557 * (gets overruns and underruns under load) and can only issue
558 * repeated STARTs in one scenario (the driver doesn't yet handle them).
559 */
560#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
561
562static struct i2c_gpio_platform_data pdata = {
563 .sda_pin = AT91_PIN_PB4,
564 .sda_is_open_drain = 1,
565 .scl_pin = AT91_PIN_PB5,
566 .scl_is_open_drain = 1,
567 .udelay = 2, /* ~100 kHz */
568};
569
570static struct platform_device at91sam9263_twi_device = {
571 .name = "i2c-gpio",
572 .id = 0,
573 .dev.platform_data = &pdata,
574};
575
576void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
577{
578 at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */
579 at91_set_multi_drive(AT91_PIN_PB4, 1);
580
581 at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */
582 at91_set_multi_drive(AT91_PIN_PB5, 1);
583
584 i2c_register_board_info(0, devices, nr_devices);
585 platform_device_register(&at91sam9263_twi_device);
586}
587
588#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
589
590static struct resource twi_resources[] = {
591 [0] = {
592 .start = AT91SAM9263_BASE_TWI,
593 .end = AT91SAM9263_BASE_TWI + SZ_16K - 1,
594 .flags = IORESOURCE_MEM,
595 },
596 [1] = {
597 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI,
598 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI,
599 .flags = IORESOURCE_IRQ,
600 },
601};
602
603static struct platform_device at91sam9263_twi_device = {
604 .name = "i2c-at91sam9260",
605 .id = 0,
606 .resource = twi_resources,
607 .num_resources = ARRAY_SIZE(twi_resources),
608};
609
610void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
611{
612 /* pins used for TWI interface */
613 at91_set_A_periph(AT91_PIN_PB4, 0); /* TWD */
614 at91_set_multi_drive(AT91_PIN_PB4, 1);
615
616 at91_set_A_periph(AT91_PIN_PB5, 0); /* TWCK */
617 at91_set_multi_drive(AT91_PIN_PB5, 1);
618
619 i2c_register_board_info(0, devices, nr_devices);
620 platform_device_register(&at91sam9263_twi_device);
621}
622#else
623void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
624#endif
625
626
627/* --------------------------------------------------------------------
628 * SPI
629 * -------------------------------------------------------------------- */
630
631#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
632static u64 spi_dmamask = DMA_BIT_MASK(32);
633
634static struct resource spi0_resources[] = {
635 [0] = {
636 .start = AT91SAM9263_BASE_SPI0,
637 .end = AT91SAM9263_BASE_SPI0 + SZ_16K - 1,
638 .flags = IORESOURCE_MEM,
639 },
640 [1] = {
641 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0,
642 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0,
643 .flags = IORESOURCE_IRQ,
644 },
645};
646
647static struct platform_device at91sam9263_spi0_device = {
648 .name = "atmel_spi",
649 .id = 0,
650 .dev = {
651 .dma_mask = &spi_dmamask,
652 .coherent_dma_mask = DMA_BIT_MASK(32),
653 },
654 .resource = spi0_resources,
655 .num_resources = ARRAY_SIZE(spi0_resources),
656};
657
658static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PB11 };
659
660static struct resource spi1_resources[] = {
661 [0] = {
662 .start = AT91SAM9263_BASE_SPI1,
663 .end = AT91SAM9263_BASE_SPI1 + SZ_16K - 1,
664 .flags = IORESOURCE_MEM,
665 },
666 [1] = {
667 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1,
668 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1,
669 .flags = IORESOURCE_IRQ,
670 },
671};
672
673static struct platform_device at91sam9263_spi1_device = {
674 .name = "atmel_spi",
675 .id = 1,
676 .dev = {
677 .dma_mask = &spi_dmamask,
678 .coherent_dma_mask = DMA_BIT_MASK(32),
679 },
680 .resource = spi1_resources,
681 .num_resources = ARRAY_SIZE(spi1_resources),
682};
683
684static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
685
686void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
687{
688 int i;
689 unsigned long cs_pin;
690 short enable_spi0 = 0;
691 short enable_spi1 = 0;
692
693 /* Choose SPI chip-selects */
694 for (i = 0; i < nr_devices; i++) {
695 if (devices[i].controller_data)
696 cs_pin = (unsigned long) devices[i].controller_data;
697 else if (devices[i].bus_num == 0)
698 cs_pin = spi0_standard_cs[devices[i].chip_select];
699 else
700 cs_pin = spi1_standard_cs[devices[i].chip_select];
701
702 if (!gpio_is_valid(cs_pin))
703 continue;
704
705 if (devices[i].bus_num == 0)
706 enable_spi0 = 1;
707 else
708 enable_spi1 = 1;
709
710 /* enable chip-select pin */
711 at91_set_gpio_output(cs_pin, 1);
712
713 /* pass chip-select pin to driver */
714 devices[i].controller_data = (void *) cs_pin;
715 }
716
717 spi_register_board_info(devices, nr_devices);
718
719 /* Configure SPI bus(es) */
720 if (enable_spi0) {
721 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
722 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
723 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
724
725 platform_device_register(&at91sam9263_spi0_device);
726 }
727 if (enable_spi1) {
728 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
729 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
730 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
731
732 platform_device_register(&at91sam9263_spi1_device);
733 }
734}
735#else
736void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
737#endif
738
739
740/* --------------------------------------------------------------------
741 * AC97
742 * -------------------------------------------------------------------- */
743
744#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
745static u64 ac97_dmamask = DMA_BIT_MASK(32);
746static struct ac97c_platform_data ac97_data;
747
748static struct resource ac97_resources[] = {
749 [0] = {
750 .start = AT91SAM9263_BASE_AC97C,
751 .end = AT91SAM9263_BASE_AC97C + SZ_16K - 1,
752 .flags = IORESOURCE_MEM,
753 },
754 [1] = {
755 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C,
756 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C,
757 .flags = IORESOURCE_IRQ,
758 },
759};
760
761static struct platform_device at91sam9263_ac97_device = {
762 .name = "atmel_ac97c",
763 .id = 0,
764 .dev = {
765 .dma_mask = &ac97_dmamask,
766 .coherent_dma_mask = DMA_BIT_MASK(32),
767 .platform_data = &ac97_data,
768 },
769 .resource = ac97_resources,
770 .num_resources = ARRAY_SIZE(ac97_resources),
771};
772
773void __init at91_add_device_ac97(struct ac97c_platform_data *data)
774{
775 if (!data)
776 return;
777
778 at91_set_A_periph(AT91_PIN_PB0, 0); /* AC97FS */
779 at91_set_A_periph(AT91_PIN_PB1, 0); /* AC97CK */
780 at91_set_A_periph(AT91_PIN_PB2, 0); /* AC97TX */
781 at91_set_A_periph(AT91_PIN_PB3, 0); /* AC97RX */
782
783 /* reset */
784 if (gpio_is_valid(data->reset_pin))
785 at91_set_gpio_output(data->reset_pin, 0);
786
787 ac97_data = *data;
788 platform_device_register(&at91sam9263_ac97_device);
789}
790#else
791void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
792#endif
793
794/* --------------------------------------------------------------------
795 * CAN Controller
796 * -------------------------------------------------------------------- */
797
798#if defined(CONFIG_CAN_AT91) || defined(CONFIG_CAN_AT91_MODULE)
799static struct resource can_resources[] = {
800 [0] = {
801 .start = AT91SAM9263_BASE_CAN,
802 .end = AT91SAM9263_BASE_CAN + SZ_16K - 1,
803 .flags = IORESOURCE_MEM,
804 },
805 [1] = {
806 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN,
807 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN,
808 .flags = IORESOURCE_IRQ,
809 },
810};
811
812static struct platform_device at91sam9263_can_device = {
813 .name = "at91_can",
814 .id = -1,
815 .resource = can_resources,
816 .num_resources = ARRAY_SIZE(can_resources),
817};
818
819void __init at91_add_device_can(struct at91_can_data *data)
820{
821 at91_set_A_periph(AT91_PIN_PA13, 0); /* CANTX */
822 at91_set_A_periph(AT91_PIN_PA14, 0); /* CANRX */
823 at91sam9263_can_device.dev.platform_data = data;
824
825 platform_device_register(&at91sam9263_can_device);
826}
827#else
828void __init at91_add_device_can(struct at91_can_data *data) {}
829#endif
830
831/* --------------------------------------------------------------------
832 * LCD Controller
833 * -------------------------------------------------------------------- */
834
835#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
836static u64 lcdc_dmamask = DMA_BIT_MASK(32);
837static struct atmel_lcdfb_pdata lcdc_data;
838
839static struct resource lcdc_resources[] = {
840 [0] = {
841 .start = AT91SAM9263_LCDC_BASE,
842 .end = AT91SAM9263_LCDC_BASE + SZ_4K - 1,
843 .flags = IORESOURCE_MEM,
844 },
845 [1] = {
846 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC,
847 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC,
848 .flags = IORESOURCE_IRQ,
849 },
850};
851
852static struct platform_device at91_lcdc_device = {
853 .name = "at91sam9263-lcdfb",
854 .id = 0,
855 .dev = {
856 .dma_mask = &lcdc_dmamask,
857 .coherent_dma_mask = DMA_BIT_MASK(32),
858 .platform_data = &lcdc_data,
859 },
860 .resource = lcdc_resources,
861 .num_resources = ARRAY_SIZE(lcdc_resources),
862};
863
864void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data)
865{
866 if (!data)
867 return;
868
869 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
870 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
871 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
872 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
873 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
874 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
875 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
876 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
877 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
878 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
879 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
880 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
881 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
882 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
883 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
884 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
885 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
886 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
887 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
888 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
889 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
890 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
891
892 lcdc_data = *data;
893 platform_device_register(&at91_lcdc_device);
894}
895#else
896void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {}
897#endif
898
899
900/* --------------------------------------------------------------------
901 * Image Sensor Interface
902 * -------------------------------------------------------------------- */
903
904#if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE)
905
906struct resource isi_resources[] = {
907 [0] = {
908 .start = AT91SAM9263_BASE_ISI,
909 .end = AT91SAM9263_BASE_ISI + SZ_16K - 1,
910 .flags = IORESOURCE_MEM,
911 },
912 [1] = {
913 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI,
914 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI,
915 .flags = IORESOURCE_IRQ,
916 },
917};
918
919static struct platform_device at91sam9263_isi_device = {
920 .name = "at91_isi",
921 .id = -1,
922 .resource = isi_resources,
923 .num_resources = ARRAY_SIZE(isi_resources),
924};
925
926void __init at91_add_device_isi(struct isi_platform_data *data,
927 bool use_pck_as_mck)
928{
929 at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */
930 at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */
931 at91_set_A_periph(AT91_PIN_PE2, 0); /* ISI_D2 */
932 at91_set_A_periph(AT91_PIN_PE3, 0); /* ISI_D3 */
933 at91_set_A_periph(AT91_PIN_PE4, 0); /* ISI_D4 */
934 at91_set_A_periph(AT91_PIN_PE5, 0); /* ISI_D5 */
935 at91_set_A_periph(AT91_PIN_PE6, 0); /* ISI_D6 */
936 at91_set_A_periph(AT91_PIN_PE7, 0); /* ISI_D7 */
937 at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */
938 at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */
939 at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */
940 at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */
941 at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */
942 at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */
943 at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */
944
945 if (use_pck_as_mck) {
946 at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
947
948 /* TODO: register the PCK for ISI_MCK and set its parent */
949 }
950}
951#else
952void __init at91_add_device_isi(struct isi_platform_data *data,
953 bool use_pck_as_mck) {}
954#endif
955
956
957/* --------------------------------------------------------------------
958 * Timer/Counter block
959 * -------------------------------------------------------------------- */
960
961#ifdef CONFIG_ATMEL_TCLIB
962
963static struct resource tcb_resources[] = {
964 [0] = {
965 .start = AT91SAM9263_BASE_TCB0,
966 .end = AT91SAM9263_BASE_TCB0 + SZ_16K - 1,
967 .flags = IORESOURCE_MEM,
968 },
969 [1] = {
970 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB,
971 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB,
972 .flags = IORESOURCE_IRQ,
973 },
974};
975
976static struct platform_device at91sam9263_tcb_device = {
977 .name = "atmel_tcb",
978 .id = 0,
979 .resource = tcb_resources,
980 .num_resources = ARRAY_SIZE(tcb_resources),
981};
982
983#if defined(CONFIG_OF)
984static struct of_device_id tcb_ids[] = {
985 { .compatible = "atmel,at91rm9200-tcb" },
986 { /*sentinel*/ }
987};
988#endif
989
990static void __init at91_add_device_tc(void)
991{
992#if defined(CONFIG_OF)
993 struct device_node *np;
994
995 np = of_find_matching_node(NULL, tcb_ids);
996 if (np) {
997 of_node_put(np);
998 return;
999 }
1000#endif
1001
1002 platform_device_register(&at91sam9263_tcb_device);
1003}
1004#else
1005static void __init at91_add_device_tc(void) { }
1006#endif
1007
1008
1009/* --------------------------------------------------------------------
1010 * RTT
1011 * -------------------------------------------------------------------- */
1012
1013static struct resource rtt0_resources[] = {
1014 {
1015 .start = AT91SAM9263_BASE_RTT0,
1016 .end = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
1017 .flags = IORESOURCE_MEM,
1018 }, {
1019 .flags = IORESOURCE_MEM,
1020 }, {
1021 .flags = IORESOURCE_IRQ,
1022 }
1023};
1024
1025static struct platform_device at91sam9263_rtt0_device = {
1026 .name = "at91_rtt",
1027 .id = 0,
1028 .resource = rtt0_resources,
1029};
1030
1031static struct resource rtt1_resources[] = {
1032 {
1033 .start = AT91SAM9263_BASE_RTT1,
1034 .end = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
1035 .flags = IORESOURCE_MEM,
1036 }, {
1037 .flags = IORESOURCE_MEM,
1038 }, {
1039 .flags = IORESOURCE_IRQ,
1040 }
1041};
1042
1043static struct platform_device at91sam9263_rtt1_device = {
1044 .name = "at91_rtt",
1045 .id = 1,
1046 .resource = rtt1_resources,
1047};
1048
1049#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
1050static void __init at91_add_device_rtt_rtc(void)
1051{
1052 struct platform_device *pdev;
1053 struct resource *r;
1054
1055 switch (CONFIG_RTC_DRV_AT91SAM9_RTT) {
1056 case 0:
1057 /*
1058 * The second resource is needed only for the chosen RTT:
1059 * GPBR will serve as the storage for RTC time offset
1060 */
1061 at91sam9263_rtt0_device.num_resources = 3;
1062 at91sam9263_rtt1_device.num_resources = 1;
1063 pdev = &at91sam9263_rtt0_device;
1064 r = rtt0_resources;
1065 break;
1066 case 1:
1067 at91sam9263_rtt0_device.num_resources = 1;
1068 at91sam9263_rtt1_device.num_resources = 3;
1069 pdev = &at91sam9263_rtt1_device;
1070 r = rtt1_resources;
1071 break;
1072 default:
1073 pr_err("at91sam9263: only supports 2 RTT (%d)\n",
1074 CONFIG_RTC_DRV_AT91SAM9_RTT);
1075 return;
1076 }
1077
1078 pdev->name = "rtc-at91sam9";
1079 r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1080 r[1].end = r[1].start + 3;
1081 r[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
1082 r[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
1083}
1084#else
1085static void __init at91_add_device_rtt_rtc(void)
1086{
1087 /* Only one resource is needed: RTT not used as RTC */
1088 at91sam9263_rtt0_device.num_resources = 1;
1089 at91sam9263_rtt1_device.num_resources = 1;
1090}
1091#endif
1092
1093static void __init at91_add_device_rtt(void)
1094{
1095 at91_add_device_rtt_rtc();
1096 platform_device_register(&at91sam9263_rtt0_device);
1097 platform_device_register(&at91sam9263_rtt1_device);
1098}
1099
1100
1101/* --------------------------------------------------------------------
1102 * Watchdog
1103 * -------------------------------------------------------------------- */
1104
1105#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1106static struct resource wdt_resources[] = {
1107 {
1108 .start = AT91SAM9263_BASE_WDT,
1109 .end = AT91SAM9263_BASE_WDT + SZ_16 - 1,
1110 .flags = IORESOURCE_MEM,
1111 }
1112};
1113
1114static struct platform_device at91sam9263_wdt_device = {
1115 .name = "at91_wdt",
1116 .id = -1,
1117 .resource = wdt_resources,
1118 .num_resources = ARRAY_SIZE(wdt_resources),
1119};
1120
1121static void __init at91_add_device_watchdog(void)
1122{
1123 platform_device_register(&at91sam9263_wdt_device);
1124}
1125#else
1126static void __init at91_add_device_watchdog(void) {}
1127#endif
1128
1129
1130/* --------------------------------------------------------------------
1131 * PWM
1132 * --------------------------------------------------------------------*/
1133
1134#if IS_ENABLED(CONFIG_PWM_ATMEL)
1135static struct resource pwm_resources[] = {
1136 [0] = {
1137 .start = AT91SAM9263_BASE_PWMC,
1138 .end = AT91SAM9263_BASE_PWMC + SZ_16K - 1,
1139 .flags = IORESOURCE_MEM,
1140 },
1141 [1] = {
1142 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC,
1143 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC,
1144 .flags = IORESOURCE_IRQ,
1145 },
1146};
1147
1148static struct platform_device at91sam9263_pwm0_device = {
1149 .name = "at91sam9rl-pwm",
1150 .id = -1,
1151 .resource = pwm_resources,
1152 .num_resources = ARRAY_SIZE(pwm_resources),
1153};
1154
1155void __init at91_add_device_pwm(u32 mask)
1156{
1157 if (mask & (1 << AT91_PWM0))
1158 at91_set_B_periph(AT91_PIN_PB7, 1); /* enable PWM0 */
1159
1160 if (mask & (1 << AT91_PWM1))
1161 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */
1162
1163 if (mask & (1 << AT91_PWM2))
1164 at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */
1165
1166 if (mask & (1 << AT91_PWM3))
1167 at91_set_B_periph(AT91_PIN_PB29, 1); /* enable PWM3 */
1168
1169 platform_device_register(&at91sam9263_pwm0_device);
1170}
1171#else
1172void __init at91_add_device_pwm(u32 mask) {}
1173#endif
1174
1175
1176/* --------------------------------------------------------------------
1177 * SSC -- Synchronous Serial Controller
1178 * -------------------------------------------------------------------- */
1179
1180#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1181static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1182
1183static struct resource ssc0_resources[] = {
1184 [0] = {
1185 .start = AT91SAM9263_BASE_SSC0,
1186 .end = AT91SAM9263_BASE_SSC0 + SZ_16K - 1,
1187 .flags = IORESOURCE_MEM,
1188 },
1189 [1] = {
1190 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0,
1191 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0,
1192 .flags = IORESOURCE_IRQ,
1193 },
1194};
1195
1196static struct platform_device at91sam9263_ssc0_device = {
1197 .name = "at91rm9200_ssc",
1198 .id = 0,
1199 .dev = {
1200 .dma_mask = &ssc0_dmamask,
1201 .coherent_dma_mask = DMA_BIT_MASK(32),
1202 },
1203 .resource = ssc0_resources,
1204 .num_resources = ARRAY_SIZE(ssc0_resources),
1205};
1206
1207static inline void configure_ssc0_pins(unsigned pins)
1208{
1209 if (pins & ATMEL_SSC_TF)
1210 at91_set_B_periph(AT91_PIN_PB0, 1);
1211 if (pins & ATMEL_SSC_TK)
1212 at91_set_B_periph(AT91_PIN_PB1, 1);
1213 if (pins & ATMEL_SSC_TD)
1214 at91_set_B_periph(AT91_PIN_PB2, 1);
1215 if (pins & ATMEL_SSC_RD)
1216 at91_set_B_periph(AT91_PIN_PB3, 1);
1217 if (pins & ATMEL_SSC_RK)
1218 at91_set_B_periph(AT91_PIN_PB4, 1);
1219 if (pins & ATMEL_SSC_RF)
1220 at91_set_B_periph(AT91_PIN_PB5, 1);
1221}
1222
1223static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1224
1225static struct resource ssc1_resources[] = {
1226 [0] = {
1227 .start = AT91SAM9263_BASE_SSC1,
1228 .end = AT91SAM9263_BASE_SSC1 + SZ_16K - 1,
1229 .flags = IORESOURCE_MEM,
1230 },
1231 [1] = {
1232 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1,
1233 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1,
1234 .flags = IORESOURCE_IRQ,
1235 },
1236};
1237
1238static struct platform_device at91sam9263_ssc1_device = {
1239 .name = "at91rm9200_ssc",
1240 .id = 1,
1241 .dev = {
1242 .dma_mask = &ssc1_dmamask,
1243 .coherent_dma_mask = DMA_BIT_MASK(32),
1244 },
1245 .resource = ssc1_resources,
1246 .num_resources = ARRAY_SIZE(ssc1_resources),
1247};
1248
1249static inline void configure_ssc1_pins(unsigned pins)
1250{
1251 if (pins & ATMEL_SSC_TF)
1252 at91_set_A_periph(AT91_PIN_PB6, 1);
1253 if (pins & ATMEL_SSC_TK)
1254 at91_set_A_periph(AT91_PIN_PB7, 1);
1255 if (pins & ATMEL_SSC_TD)
1256 at91_set_A_periph(AT91_PIN_PB8, 1);
1257 if (pins & ATMEL_SSC_RD)
1258 at91_set_A_periph(AT91_PIN_PB9, 1);
1259 if (pins & ATMEL_SSC_RK)
1260 at91_set_A_periph(AT91_PIN_PB10, 1);
1261 if (pins & ATMEL_SSC_RF)
1262 at91_set_A_periph(AT91_PIN_PB11, 1);
1263}
1264
1265/*
1266 * SSC controllers are accessed through library code, instead of any
1267 * kind of all-singing/all-dancing driver. For example one could be
1268 * used by a particular I2S audio codec's driver, while another one
1269 * on the same system might be used by a custom data capture driver.
1270 */
1271void __init at91_add_device_ssc(unsigned id, unsigned pins)
1272{
1273 struct platform_device *pdev;
1274
1275 /*
1276 * NOTE: caller is responsible for passing information matching
1277 * "pins" to whatever will be using each particular controller.
1278 */
1279 switch (id) {
1280 case AT91SAM9263_ID_SSC0:
1281 pdev = &at91sam9263_ssc0_device;
1282 configure_ssc0_pins(pins);
1283 break;
1284 case AT91SAM9263_ID_SSC1:
1285 pdev = &at91sam9263_ssc1_device;
1286 configure_ssc1_pins(pins);
1287 break;
1288 default:
1289 return;
1290 }
1291
1292 platform_device_register(pdev);
1293}
1294
1295#else
1296void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1297#endif
1298
1299
1300/* --------------------------------------------------------------------
1301 * UART
1302 * -------------------------------------------------------------------- */
1303
1304#if defined(CONFIG_SERIAL_ATMEL)
1305
1306static struct resource dbgu_resources[] = {
1307 [0] = {
1308 .start = AT91SAM9263_BASE_DBGU,
1309 .end = AT91SAM9263_BASE_DBGU + SZ_512 - 1,
1310 .flags = IORESOURCE_MEM,
1311 },
1312 [1] = {
1313 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
1314 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
1315 .flags = IORESOURCE_IRQ,
1316 },
1317};
1318
1319static struct atmel_uart_data dbgu_data = {
1320 .use_dma_tx = 0,
1321 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
1322};
1323
1324static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1325
1326static struct platform_device at91sam9263_dbgu_device = {
1327 .name = "atmel_usart",
1328 .id = 0,
1329 .dev = {
1330 .dma_mask = &dbgu_dmamask,
1331 .coherent_dma_mask = DMA_BIT_MASK(32),
1332 .platform_data = &dbgu_data,
1333 },
1334 .resource = dbgu_resources,
1335 .num_resources = ARRAY_SIZE(dbgu_resources),
1336};
1337
1338static inline void configure_dbgu_pins(void)
1339{
1340 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
1341 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
1342}
1343
1344static struct resource uart0_resources[] = {
1345 [0] = {
1346 .start = AT91SAM9263_BASE_US0,
1347 .end = AT91SAM9263_BASE_US0 + SZ_16K - 1,
1348 .flags = IORESOURCE_MEM,
1349 },
1350 [1] = {
1351 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US0,
1352 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US0,
1353 .flags = IORESOURCE_IRQ,
1354 },
1355};
1356
1357static struct atmel_uart_data uart0_data = {
1358 .use_dma_tx = 1,
1359 .use_dma_rx = 1,
1360};
1361
1362static u64 uart0_dmamask = DMA_BIT_MASK(32);
1363
1364static struct platform_device at91sam9263_uart0_device = {
1365 .name = "atmel_usart",
1366 .id = 1,
1367 .dev = {
1368 .dma_mask = &uart0_dmamask,
1369 .coherent_dma_mask = DMA_BIT_MASK(32),
1370 .platform_data = &uart0_data,
1371 },
1372 .resource = uart0_resources,
1373 .num_resources = ARRAY_SIZE(uart0_resources),
1374};
1375
1376static inline void configure_usart0_pins(unsigned pins)
1377{
1378 at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
1379 at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
1380
1381 if (pins & ATMEL_UART_RTS)
1382 at91_set_A_periph(AT91_PIN_PA28, 0); /* RTS0 */
1383 if (pins & ATMEL_UART_CTS)
1384 at91_set_A_periph(AT91_PIN_PA29, 0); /* CTS0 */
1385}
1386
1387static struct resource uart1_resources[] = {
1388 [0] = {
1389 .start = AT91SAM9263_BASE_US1,
1390 .end = AT91SAM9263_BASE_US1 + SZ_16K - 1,
1391 .flags = IORESOURCE_MEM,
1392 },
1393 [1] = {
1394 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US1,
1395 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US1,
1396 .flags = IORESOURCE_IRQ,
1397 },
1398};
1399
1400static struct atmel_uart_data uart1_data = {
1401 .use_dma_tx = 1,
1402 .use_dma_rx = 1,
1403};
1404
1405static u64 uart1_dmamask = DMA_BIT_MASK(32);
1406
1407static struct platform_device at91sam9263_uart1_device = {
1408 .name = "atmel_usart",
1409 .id = 2,
1410 .dev = {
1411 .dma_mask = &uart1_dmamask,
1412 .coherent_dma_mask = DMA_BIT_MASK(32),
1413 .platform_data = &uart1_data,
1414 },
1415 .resource = uart1_resources,
1416 .num_resources = ARRAY_SIZE(uart1_resources),
1417};
1418
1419static inline void configure_usart1_pins(unsigned pins)
1420{
1421 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
1422 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
1423
1424 if (pins & ATMEL_UART_RTS)
1425 at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */
1426 if (pins & ATMEL_UART_CTS)
1427 at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
1428}
1429
1430static struct resource uart2_resources[] = {
1431 [0] = {
1432 .start = AT91SAM9263_BASE_US2,
1433 .end = AT91SAM9263_BASE_US2 + SZ_16K - 1,
1434 .flags = IORESOURCE_MEM,
1435 },
1436 [1] = {
1437 .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US2,
1438 .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US2,
1439 .flags = IORESOURCE_IRQ,
1440 },
1441};
1442
1443static struct atmel_uart_data uart2_data = {
1444 .use_dma_tx = 1,
1445 .use_dma_rx = 1,
1446};
1447
1448static u64 uart2_dmamask = DMA_BIT_MASK(32);
1449
1450static struct platform_device at91sam9263_uart2_device = {
1451 .name = "atmel_usart",
1452 .id = 3,
1453 .dev = {
1454 .dma_mask = &uart2_dmamask,
1455 .coherent_dma_mask = DMA_BIT_MASK(32),
1456 .platform_data = &uart2_data,
1457 },
1458 .resource = uart2_resources,
1459 .num_resources = ARRAY_SIZE(uart2_resources),
1460};
1461
1462static inline void configure_usart2_pins(unsigned pins)
1463{
1464 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
1465 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
1466
1467 if (pins & ATMEL_UART_RTS)
1468 at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */
1469 if (pins & ATMEL_UART_CTS)
1470 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
1471}
1472
1473static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1474
1475void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1476{
1477 struct platform_device *pdev;
1478 struct atmel_uart_data *pdata;
1479
1480 switch (id) {
1481 case 0: /* DBGU */
1482 pdev = &at91sam9263_dbgu_device;
1483 configure_dbgu_pins();
1484 break;
1485 case AT91SAM9263_ID_US0:
1486 pdev = &at91sam9263_uart0_device;
1487 configure_usart0_pins(pins);
1488 break;
1489 case AT91SAM9263_ID_US1:
1490 pdev = &at91sam9263_uart1_device;
1491 configure_usart1_pins(pins);
1492 break;
1493 case AT91SAM9263_ID_US2:
1494 pdev = &at91sam9263_uart2_device;
1495 configure_usart2_pins(pins);
1496 break;
1497 default:
1498 return;
1499 }
1500 pdata = pdev->dev.platform_data;
1501 pdata->num = portnr; /* update to mapped ID */
1502
1503 if (portnr < ATMEL_MAX_UART)
1504 at91_uarts[portnr] = pdev;
1505}
1506
1507void __init at91_add_device_serial(void)
1508{
1509 int i;
1510
1511 for (i = 0; i < ATMEL_MAX_UART; i++) {
1512 if (at91_uarts[i])
1513 platform_device_register(at91_uarts[i]);
1514 }
1515}
1516#else
1517void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1518void __init at91_add_device_serial(void) {}
1519#endif
1520
1521
1522/* -------------------------------------------------------------------- */
1523/*
1524 * These devices are always present and don't need any board-specific
1525 * setup.
1526 */
1527static int __init at91_add_standard_devices(void)
1528{
1529 if (of_have_populated_dt())
1530 return 0;
1531
1532 at91_add_device_rtt();
1533 at91_add_device_watchdog();
1534 at91_add_device_tc();
1535 return 0;
1536}
1537
1538arch_initcall(at91_add_standard_devices);
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 13:55:33 -0400