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-rw-r--r--arch/arm/boot/dts/ecx-common.dtsi8
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi4
-rw-r--r--arch/arm/boot/dts/integrator.dtsi5
-rw-r--r--arch/arm/boot/dts/integratorap.dts5
-rw-r--r--arch/arm/boot/dts/integratorcp.dts4
-rw-r--r--arch/arm/boot/dts/keystone-clocks.dtsi821
-rw-r--r--arch/arm/boot/dts/keystone.dts63
-rw-r--r--arch/arm/boot/dts/r7s72100.dtsi36
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi41
9 files changed, 981 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
index e8559b753c9d..bc22557d7a6a 100644
--- a/arch/arm/boot/dts/ecx-common.dtsi
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -19,6 +19,14 @@
19 bootargs = "console=ttyAMA0"; 19 bootargs = "console=ttyAMA0";
20 }; 20 };
21 21
22 psci {
23 compatible = "arm,psci";
24 method = "smc";
25 cpu_suspend = <0x84000002>;
26 cpu_off = <0x84000004>;
27 cpu_on = <0x84000006>;
28 };
29
22 soc { 30 soc {
23 #address-cells = <1>; 31 #address-cells = <1>;
24 #size-cells = <1>; 32 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c46651e4d966..177d9e791a01 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -380,7 +380,9 @@
380 }; 380 };
381 381
382 anatop: anatop@020c8000 { 382 anatop: anatop@020c8000 {
383 compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus"; 383 compatible = "fsl,imx6sl-anatop",
384 "fsl,imx6q-anatop",
385 "syscon", "simple-bus";
384 reg = <0x020c8000 0x1000>; 386 reg = <0x020c8000 0x1000>;
385 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; 387 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
386 388
diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi
index 813b91d7bea2..0f06f8687b0b 100644
--- a/arch/arm/boot/dts/integrator.dtsi
+++ b/arch/arm/boot/dts/integrator.dtsi
@@ -5,6 +5,11 @@
5/include/ "skeleton.dtsi" 5/include/ "skeleton.dtsi"
6 6
7/ { 7/ {
8 core-module@10000000 {
9 compatible = "arm,core-module-integrator";
10 reg = <0x10000000 0x200>;
11 };
12
8 timer@13000000 { 13 timer@13000000 {
9 reg = <0x13000000 0x100>; 14 reg = <0x13000000 0x100>;
10 interrupt-parent = <&pic>; 15 interrupt-parent = <&pic>;
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index b6b82eca8d1e..e6be9315ff0a 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -19,8 +19,11 @@
19 }; 19 };
20 20
21 syscon { 21 syscon {
22 /* AP system controller registers */ 22 compatible = "arm,integrator-ap-syscon";
23 reg = <0x11000000 0x100>; 23 reg = <0x11000000 0x100>;
24 interrupt-parent = <&pic>;
25 /* These are the logical module IRQs */
26 interrupts = <9>, <10>, <11>, <12>;
24 }; 27 };
25 28
26 timer0: timer@13000000 { 29 timer0: timer@13000000 {
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index 72693a69f830..7deb3a3182b4 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -13,8 +13,8 @@
13 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; 13 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
14 }; 14 };
15 15
16 cpcon { 16 syscon {
17 /* CP controller registers */ 17 compatible = "arm,integrator-cp-syscon";
18 reg = <0xcb000000 0x100>; 18 reg = <0xcb000000 0x100>;
19 }; 19 };
20 20
diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi
new file mode 100644
index 000000000000..d6713b113258
--- /dev/null
+++ b/arch/arm/boot/dts/keystone-clocks.dtsi
@@ -0,0 +1,821 @@
1/*
2 * Device Tree Source for Keystone 2 clock tree
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11clocks {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges;
15
16 refclkmain: refclkmain {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <122880000>;
20 clock-output-names = "refclk-main";
21 };
22
23 mainpllclk: mainpllclk@2310110 {
24 #clock-cells = <0>;
25 compatible = "ti,keystone,main-pll-clock";
26 clocks = <&refclkmain>;
27 reg = <0x02620350 4>, <0x02310110 4>;
28 reg-names = "control", "multiplier";
29 fixed-postdiv = <2>;
30 };
31
32 papllclk: papllclk@2620358 {
33 #clock-cells = <0>;
34 compatible = "ti,keystone,pll-clock";
35 clocks = <&refclkmain>;
36 clock-output-names = "pa-pll-clk";
37 reg = <0x02620358 4>;
38 reg-names = "control";
39 fixed-postdiv = <6>;
40 };
41
42 ddr3allclk: ddr3apllclk@2620360 {
43 #clock-cells = <0>;
44 compatible = "ti,keystone,pll-clock";
45 clocks = <&refclkmain>;
46 clock-output-names = "ddr-3a-pll-clk";
47 reg = <0x02620360 4>;
48 reg-names = "control";
49 fixed-postdiv = <6>;
50 };
51
52 ddr3bllclk: ddr3bpllclk@2620368 {
53 #clock-cells = <0>;
54 compatible = "ti,keystone,pll-clock";
55 clocks = <&refclkmain>;
56 clock-output-names = "ddr-3b-pll-clk";
57 reg = <0x02620368 4>;
58 reg-names = "control";
59 fixed-postdiv = <6>;
60 };
61
62 armpllclk: armpllclk@2620370 {
63 #clock-cells = <0>;
64 compatible = "ti,keystone,pll-clock";
65 clocks = <&refclkmain>;
66 clock-output-names = "arm-pll-clk";
67 reg = <0x02620370 4>;
68 reg-names = "control";
69 fixed-postdiv = <6>;
70 };
71
72 mainmuxclk: mainmuxclk@2310108 {
73 #clock-cells = <0>;
74 compatible = "ti,keystone,pll-mux-clock";
75 clocks = <&mainpllclk>, <&refclkmain>;
76 reg = <0x02310108 4>;
77 bit-shift = <23>;
78 bit-mask = <1>;
79 clock-output-names = "mainmuxclk";
80 };
81
82 chipclk1: chipclk1 {
83 #clock-cells = <0>;
84 compatible = "fixed-factor-clock";
85 clocks = <&mainmuxclk>;
86 clock-div = <1>;
87 clock-mult = <1>;
88 clock-output-names = "chipclk1";
89 };
90
91 chipclk1rstiso: chipclk1rstiso {
92 #clock-cells = <0>;
93 compatible = "fixed-factor-clock";
94 clocks = <&mainmuxclk>;
95 clock-div = <1>;
96 clock-mult = <1>;
97 clock-output-names = "chipclk1rstiso";
98 };
99
100 gemtraceclk: gemtraceclk@2310120 {
101 #clock-cells = <0>;
102 compatible = "ti,keystone,pll-divider-clock";
103 clocks = <&mainmuxclk>;
104 reg = <0x02310120 4>;
105 bit-shift = <0>;
106 bit-mask = <8>;
107 clock-output-names = "gemtraceclk";
108 };
109
110 chipstmxptclk: chipstmxptclk {
111 #clock-cells = <0>;
112 compatible = "ti,keystone,pll-divider-clock";
113 clocks = <&mainmuxclk>;
114 reg = <0x02310164 4>;
115 bit-shift = <0>;
116 bit-mask = <8>;
117 clock-output-names = "chipstmxptclk";
118 };
119
120 chipclk12: chipclk12 {
121 #clock-cells = <0>;
122 compatible = "fixed-factor-clock";
123 clocks = <&chipclk1>;
124 clock-div = <2>;
125 clock-mult = <1>;
126 clock-output-names = "chipclk12";
127 };
128
129 chipclk13: chipclk13 {
130 #clock-cells = <0>;
131 compatible = "fixed-factor-clock";
132 clocks = <&chipclk1>;
133 clock-div = <3>;
134 clock-mult = <1>;
135 clock-output-names = "chipclk13";
136 };
137
138 chipclk14: chipclk14 {
139 #clock-cells = <0>;
140 compatible = "fixed-factor-clock";
141 clocks = <&chipclk1>;
142 clock-div = <4>;
143 clock-mult = <1>;
144 clock-output-names = "chipclk14";
145 };
146
147 chipclk16: chipclk16 {
148 #clock-cells = <0>;
149 compatible = "fixed-factor-clock";
150 clocks = <&chipclk1>;
151 clock-div = <6>;
152 clock-mult = <1>;
153 clock-output-names = "chipclk16";
154 };
155
156 chipclk112: chipclk112 {
157 #clock-cells = <0>;
158 compatible = "fixed-factor-clock";
159 clocks = <&chipclk1>;
160 clock-div = <12>;
161 clock-mult = <1>;
162 clock-output-names = "chipclk112";
163 };
164
165 chipclk124: chipclk124 {
166 #clock-cells = <0>;
167 compatible = "fixed-factor-clock";
168 clocks = <&chipclk1>;
169 clock-div = <24>;
170 clock-mult = <1>;
171 clock-output-names = "chipclk114";
172 };
173
174 chipclk1rstiso13: chipclk1rstiso13 {
175 #clock-cells = <0>;
176 compatible = "fixed-factor-clock";
177 clocks = <&chipclk1rstiso>;
178 clock-div = <3>;
179 clock-mult = <1>;
180 clock-output-names = "chipclk1rstiso13";
181 };
182
183 chipclk1rstiso14: chipclk1rstiso14 {
184 #clock-cells = <0>;
185 compatible = "fixed-factor-clock";
186 clocks = <&chipclk1rstiso>;
187 clock-div = <4>;
188 clock-mult = <1>;
189 clock-output-names = "chipclk1rstiso14";
190 };
191
192 chipclk1rstiso16: chipclk1rstiso16 {
193 #clock-cells = <0>;
194 compatible = "fixed-factor-clock";
195 clocks = <&chipclk1rstiso>;
196 clock-div = <6>;
197 clock-mult = <1>;
198 clock-output-names = "chipclk1rstiso16";
199 };
200
201 chipclk1rstiso112: chipclk1rstiso112 {
202 #clock-cells = <0>;
203 compatible = "fixed-factor-clock";
204 clocks = <&chipclk1rstiso>;
205 clock-div = <12>;
206 clock-mult = <1>;
207 clock-output-names = "chipclk1rstiso112";
208 };
209
210 clkmodrst0: clkmodrst0 {
211 #clock-cells = <0>;
212 compatible = "ti,keystone,psc-clock";
213 clocks = <&chipclk16>;
214 clock-output-names = "modrst0";
215 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
216 reg-names = "control", "domain";
217 domain-id = <0>;
218 };
219
220
221 clkusb: clkusb {
222 #clock-cells = <0>;
223 compatible = "ti,keystone,psc-clock";
224 clocks = <&chipclk16>;
225 clock-output-names = "usb";
226 reg = <0x02350008 0xb00>, <0x02350000 0x400>;
227 reg-names = "control", "domain";
228 domain-id = <0>;
229 };
230
231 clkaemifspi: clkaemifspi {
232 #clock-cells = <0>;
233 compatible = "ti,keystone,psc-clock";
234 clocks = <&chipclk16>;
235 clock-output-names = "aemif-spi";
236 reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
237 reg-names = "control", "domain";
238 domain-id = <0>;
239 };
240
241
242 clkdebugsstrc: clkdebugsstrc {
243 #clock-cells = <0>;
244 compatible = "ti,keystone,psc-clock";
245 clocks = <&chipclk13>;
246 clock-output-names = "debugss-trc";
247 reg = <0x02350014 0xb00>, <0x02350000 0x400>;
248 reg-names = "control", "domain";
249 domain-id = <0>;
250 };
251
252 clktetbtrc: clktetbtrc {
253 #clock-cells = <0>;
254 compatible = "ti,keystone,psc-clock";
255 clocks = <&chipclk13>;
256 clock-output-names = "tetb-trc";
257 reg = <0x02350018 0xb00>, <0x02350004 0x400>;
258 reg-names = "control", "domain";
259 domain-id = <1>;
260 };
261
262 clkpa: clkpa {
263 #clock-cells = <0>;
264 compatible = "ti,keystone,psc-clock";
265 clocks = <&chipclk16>;
266 clock-output-names = "pa";
267 reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
268 reg-names = "control", "domain";
269 domain-id = <2>;
270 };
271
272 clkcpgmac: clkcpgmac {
273 #clock-cells = <0>;
274 compatible = "ti,keystone,psc-clock";
275 clocks = <&clkpa>;
276 clock-output-names = "cpgmac";
277 reg = <0x02350020 0xb00>, <0x02350008 0x400>;
278 reg-names = "control", "domain";
279 domain-id = <2>;
280 };
281
282 clksa: clksa {
283 #clock-cells = <0>;
284 compatible = "ti,keystone,psc-clock";
285 clocks = <&clkpa>;
286 clock-output-names = "sa";
287 reg = <0x02350024 0xb00>, <0x02350008 0x400>;
288 reg-names = "control", "domain";
289 domain-id = <2>;
290 };
291
292 clkpcie: clkpcie {
293 #clock-cells = <0>;
294 compatible = "ti,keystone,psc-clock";
295 clocks = <&chipclk12>;
296 clock-output-names = "pcie";
297 reg = <0x02350028 0xb00>, <0x0235000c 0x400>;
298 reg-names = "control", "domain";
299 domain-id = <3>;
300 };
301
302 clksrio: clksrio {
303 #clock-cells = <0>;
304 compatible = "ti,keystone,psc-clock";
305 clocks = <&chipclk1rstiso13>;
306 clock-output-names = "srio";
307 reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
308 reg-names = "control", "domain";
309 domain-id = <4>;
310 };
311
312 clkhyperlink0: clkhyperlink0 {
313 #clock-cells = <0>;
314 compatible = "ti,keystone,psc-clock";
315 clocks = <&chipclk12>;
316 clock-output-names = "hyperlink-0";
317 reg = <0x02350030 0xb00>, <0x02350014 0x400>;
318 reg-names = "control", "domain";
319 domain-id = <5>;
320 };
321
322 clksr: clksr {
323 #clock-cells = <0>;
324 compatible = "ti,keystone,psc-clock";
325 clocks = <&chipclk1rstiso112>;
326 clock-output-names = "sr";
327 reg = <0x02350034 0xb00>, <0x02350018 0x400>;
328 reg-names = "control", "domain";
329 domain-id = <6>;
330 };
331
332 clkmsmcsram: clkmsmcsram {
333 #clock-cells = <0>;
334 compatible = "ti,keystone,psc-clock";
335 clocks = <&chipclk1>;
336 clock-output-names = "msmcsram";
337 reg = <0x02350038 0xb00>, <0x0235001c 0x400>;
338 reg-names = "control", "domain";
339 domain-id = <7>;
340 };
341
342 clkgem0: clkgem0 {
343 #clock-cells = <0>;
344 compatible = "ti,keystone,psc-clock";
345 clocks = <&chipclk1>;
346 clock-output-names = "gem0";
347 reg = <0x0235003c 0xb00>, <0x02350020 0x400>;
348 reg-names = "control", "domain";
349 domain-id = <8>;
350 };
351
352 clkgem1: clkgem1 {
353 #clock-cells = <0>;
354 compatible = "ti,keystone,psc-clock";
355 clocks = <&chipclk1>;
356 clock-output-names = "gem1";
357 reg = <0x02350040 0xb00>, <0x02350024 0x400>;
358 reg-names = "control", "domain";
359 domain-id = <9>;
360 };
361
362 clkgem2: clkgem2 {
363 #clock-cells = <0>;
364 compatible = "ti,keystone,psc-clock";
365 clocks = <&chipclk1>;
366 clock-output-names = "gem2";
367 reg = <0x02350044 0xb00>, <0x02350028 0x400>;
368 reg-names = "control", "domain";
369 domain-id = <10>;
370 };
371
372 clkgem3: clkgem3 {
373 #clock-cells = <0>;
374 compatible = "ti,keystone,psc-clock";
375 clocks = <&chipclk1>;
376 clock-output-names = "gem3";
377 reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
378 reg-names = "control", "domain";
379 domain-id = <11>;
380 };
381
382 clkgem4: clkgem4 {
383 #clock-cells = <0>;
384 compatible = "ti,keystone,psc-clock";
385 clocks = <&chipclk1>;
386 clock-output-names = "gem4";
387 reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
388 reg-names = "control", "domain";
389 domain-id = <12>;
390 };
391
392 clkgem5: clkgem5 {
393 #clock-cells = <0>;
394 compatible = "ti,keystone,psc-clock";
395 clocks = <&chipclk1>;
396 clock-output-names = "gem5";
397 reg = <0x02350050 0xb00>, <0x02350034 0x400>;
398 reg-names = "control", "domain";
399 domain-id = <13>;
400 };
401
402 clkgem6: clkgem6 {
403 #clock-cells = <0>;
404 compatible = "ti,keystone,psc-clock";
405 clocks = <&chipclk1>;
406 clock-output-names = "gem6";
407 reg = <0x02350054 0xb00>, <0x02350038 0x400>;
408 reg-names = "control", "domain";
409 domain-id = <14>;
410 };
411
412 clkgem7: clkgem7 {
413 #clock-cells = <0>;
414 compatible = "ti,keystone,psc-clock";
415 clocks = <&chipclk1>;
416 clock-output-names = "gem7";
417 reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
418 reg-names = "control", "domain";
419 domain-id = <15>;
420 };
421
422 clkddr30: clkddr30 {
423 #clock-cells = <0>;
424 compatible = "ti,keystone,psc-clock";
425 clocks = <&chipclk12>;
426 clock-output-names = "ddr3-0";
427 reg = <0x0235005c 0xb00>, <0x02350040 0x400>;
428 reg-names = "control", "domain";
429 domain-id = <16>;
430 };
431
432 clkddr31: clkddr31 {
433 #clock-cells = <0>;
434 compatible = "ti,keystone,psc-clock";
435 clocks = <&chipclk13>;
436 clock-output-names = "ddr3-1";
437 reg = <0x02350060 0xb00>, <0x02350040 0x400>;
438 reg-names = "control", "domain";
439 domain-id = <16>;
440 };
441
442 clktac: clktac {
443 #clock-cells = <0>;
444 compatible = "ti,keystone,psc-clock";
445 clocks = <&chipclk13>;
446 clock-output-names = "tac";
447 reg = <0x02350064 0xb00>, <0x02350044 0x400>;
448 reg-names = "control", "domain";
449 domain-id = <17>;
450 };
451
452 clkrac01: clktac01 {
453 #clock-cells = <0>;
454 compatible = "ti,keystone,psc-clock";
455 clocks = <&chipclk13>;
456 clock-output-names = "rac-01";
457 reg = <0x02350068 0xb00>, <0x02350044 0x400>;
458 reg-names = "control", "domain";
459 domain-id = <17>;
460 };
461
462 clkrac23: clktac23 {
463 #clock-cells = <0>;
464 compatible = "ti,keystone,psc-clock";
465 clocks = <&chipclk13>;
466 clock-output-names = "rac-23";
467 reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
468 reg-names = "control", "domain";
469 domain-id = <18>;
470 };
471
472 clkfftc0: clkfftc0 {
473 #clock-cells = <0>;
474 compatible = "ti,keystone,psc-clock";
475 clocks = <&chipclk13>;
476 clock-output-names = "fftc-0";
477 reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
478 reg-names = "control", "domain";
479 domain-id = <19>;
480 };
481
482 clkfftc1: clkfftc1 {
483 #clock-cells = <0>;
484 compatible = "ti,keystone,psc-clock";
485 clocks = <&chipclk13>;
486 clock-output-names = "fftc-1";
487 reg = <0x02350074 0xb00>, <0x023504c0 0x400>;
488 reg-names = "control", "domain";
489 domain-id = <19>;
490 };
491
492 clkfftc2: clkfftc2 {
493 #clock-cells = <0>;
494 compatible = "ti,keystone,psc-clock";
495 clocks = <&chipclk13>;
496 clock-output-names = "fftc-2";
497 reg = <0x02350078 0xb00>, <0x02350050 0x400>;
498 reg-names = "control", "domain";
499 domain-id = <20>;
500 };
501
502 clkfftc3: clkfftc3 {
503 #clock-cells = <0>;
504 compatible = "ti,keystone,psc-clock";
505 clocks = <&chipclk13>;
506 clock-output-names = "fftc-3";
507 reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
508 reg-names = "control", "domain";
509 domain-id = <20>;
510 };
511
512 clkfftc4: clkfftc4 {
513 #clock-cells = <0>;
514 compatible = "ti,keystone,psc-clock";
515 clocks = <&chipclk13>;
516 clock-output-names = "fftc-4";
517 reg = <0x02350080 0xb00>, <0x02350050 0x400>;
518 reg-names = "control", "domain";
519 domain-id = <20>;
520 };
521
522 clkfftc5: clkfftc5 {
523 #clock-cells = <0>;
524 compatible = "ti,keystone,psc-clock";
525 clocks = <&chipclk13>;
526 clock-output-names = "fftc-5";
527 reg = <0x02350084 0xb00>, <0x02350050 0x400>;
528 reg-names = "control", "domain";
529 domain-id = <20>;
530 };
531
532 clkaif: clkaif {
533 #clock-cells = <0>;
534 compatible = "ti,keystone,psc-clock";
535 clocks = <&chipclk13>;
536 clock-output-names = "aif";
537 reg = <0x02350088 0xb00>, <0x02350054 0x400>;
538 reg-names = "control", "domain";
539 domain-id = <21>;
540 };
541
542 clktcp3d0: clktcp3d0 {
543 #clock-cells = <0>;
544 compatible = "ti,keystone,psc-clock";
545 clocks = <&chipclk13>;
546 clock-output-names = "tcp3d-0";
547 reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
548 reg-names = "control", "domain";
549 domain-id = <22>;
550 };
551
552 clktcp3d1: clktcp3d1 {
553 #clock-cells = <0>;
554 compatible = "ti,keystone,psc-clock";
555 clocks = <&chipclk13>;
556 clock-output-names = "tcp3d-1";
557 reg = <0x02350090 0xb00>, <0x02350058 0x400>;
558 reg-names = "control", "domain";
559 domain-id = <22>;
560 };
561
562 clktcp3d2: clktcp3d2 {
563 #clock-cells = <0>;
564 compatible = "ti,keystone,psc-clock";
565 clocks = <&chipclk13>;
566 clock-output-names = "tcp3d-2";
567 reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
568 reg-names = "control", "domain";
569 domain-id = <23>;
570 };
571
572 clktcp3d3: clktcp3d3 {
573 #clock-cells = <0>;
574 compatible = "ti,keystone,psc-clock";
575 clocks = <&chipclk13>;
576 clock-output-names = "tcp3d-3";
577 reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
578 reg-names = "control", "domain";
579 domain-id = <23>;
580 };
581
582 clkvcp0: clkvcp0 {
583 #clock-cells = <0>;
584 compatible = "ti,keystone,psc-clock";
585 clocks = <&chipclk13>;
586 clock-output-names = "vcp-0";
587 reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
588 reg-names = "control", "domain";
589 domain-id = <24>;
590 };
591
592 clkvcp1: clkvcp1 {
593 #clock-cells = <0>;
594 compatible = "ti,keystone,psc-clock";
595 clocks = <&chipclk13>;
596 clock-output-names = "vcp-1";
597 reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
598 reg-names = "control", "domain";
599 domain-id = <24>;
600 };
601
602 clkvcp2: clkvcp2 {
603 #clock-cells = <0>;
604 compatible = "ti,keystone,psc-clock";
605 clocks = <&chipclk13>;
606 clock-output-names = "vcp-2";
607 reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
608 reg-names = "control", "domain";
609 domain-id = <24>;
610 };
611
612 clkvcp3: clkvcp3 {
613 #clock-cells = <0>;
614 compatible = "ti,keystone,psc-clock";
615 clocks = <&chipclk13>;
616 clock-output-names = "vcp-3";
617 reg = <0x0235000a8 0xb00>, <0x02350060 0x400>;
618 reg-names = "control", "domain";
619 domain-id = <24>;
620 };
621
622 clkvcp4: clkvcp4 {
623 #clock-cells = <0>;
624 compatible = "ti,keystone,psc-clock";
625 clocks = <&chipclk13>;
626 clock-output-names = "vcp-4";
627 reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
628 reg-names = "control", "domain";
629 domain-id = <25>;
630 };
631
632 clkvcp5: clkvcp5 {
633 #clock-cells = <0>;
634 compatible = "ti,keystone,psc-clock";
635 clocks = <&chipclk13>;
636 clock-output-names = "vcp-5";
637 reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
638 reg-names = "control", "domain";
639 domain-id = <25>;
640 };
641
642 clkvcp6: clkvcp6 {
643 #clock-cells = <0>;
644 compatible = "ti,keystone,psc-clock";
645 clocks = <&chipclk13>;
646 clock-output-names = "vcp-6";
647 reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
648 reg-names = "control", "domain";
649 domain-id = <25>;
650 };
651
652 clkvcp7: clkvcp7 {
653 #clock-cells = <0>;
654 compatible = "ti,keystone,psc-clock";
655 clocks = <&chipclk13>;
656 clock-output-names = "vcp-7";
657 reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
658 reg-names = "control", "domain";
659 domain-id = <25>;
660 };
661
662 clkbcp: clkbcp {
663 #clock-cells = <0>;
664 compatible = "ti,keystone,psc-clock";
665 clocks = <&chipclk13>;
666 clock-output-names = "bcp";
667 reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
668 reg-names = "control", "domain";
669 domain-id = <26>;
670 };
671
672 clkdxb: clkdxb {
673 #clock-cells = <0>;
674 compatible = "ti,keystone,psc-clock";
675 clocks = <&chipclk13>;
676 clock-output-names = "dxb";
677 reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
678 reg-names = "control", "domain";
679 domain-id = <27>;
680 };
681
682 clkhyperlink1: clkhyperlink1 {
683 #clock-cells = <0>;
684 compatible = "ti,keystone,psc-clock";
685 clocks = <&chipclk12>;
686 clock-output-names = "hyperlink-1";
687 reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
688 reg-names = "control", "domain";
689 domain-id = <28>;
690 };
691
692 clkxge: clkxge {
693 #clock-cells = <0>;
694 compatible = "ti,keystone,psc-clock";
695 clocks = <&chipclk13>;
696 clock-output-names = "xge";
697 reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
698 reg-names = "control", "domain";
699 domain-id = <29>;
700 };
701
702 clkwdtimer0: clkwdtimer0 {
703 #clock-cells = <0>;
704 compatible = "ti,keystone,psc-clock";
705 clocks = <&clkmodrst0>;
706 clock-output-names = "timer0";
707 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
708 reg-names = "control", "domain";
709 domain-id = <0>;
710 };
711
712 clkwdtimer1: clkwdtimer1 {
713 #clock-cells = <0>;
714 compatible = "ti,keystone,psc-clock";
715 clocks = <&clkmodrst0>;
716 clock-output-names = "timer1";
717 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
718 reg-names = "control", "domain";
719 domain-id = <0>;
720 };
721
722 clkwdtimer2: clkwdtimer2 {
723 #clock-cells = <0>;
724 compatible = "ti,keystone,psc-clock";
725 clocks = <&clkmodrst0>;
726 clock-output-names = "timer2";
727 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
728 reg-names = "control", "domain";
729 domain-id = <0>;
730 };
731
732 clkwdtimer3: clkwdtimer3 {
733 #clock-cells = <0>;
734 compatible = "ti,keystone,psc-clock";
735 clocks = <&clkmodrst0>;
736 clock-output-names = "timer3";
737 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
738 reg-names = "control", "domain";
739 domain-id = <0>;
740 };
741
742 clkuart0: clkuart0 {
743 #clock-cells = <0>;
744 compatible = "ti,keystone,psc-clock";
745 clocks = <&clkmodrst0>;
746 clock-output-names = "uart0";
747 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
748 reg-names = "control", "domain";
749 domain-id = <0>;
750 };
751
752 clkuart1: clkuart1 {
753 #clock-cells = <0>;
754 compatible = "ti,keystone,psc-clock";
755 clocks = <&clkmodrst0>;
756 clock-output-names = "uart1";
757 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
758 reg-names = "control", "domain";
759 domain-id = <0>;
760 };
761
762 clkaemif: clkaemif {
763 #clock-cells = <0>;
764 compatible = "ti,keystone,psc-clock";
765 clocks = <&clkaemifspi>;
766 clock-output-names = "aemif";
767 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
768 reg-names = "control", "domain";
769 domain-id = <0>;
770 };
771
772 clkusim: clkusim {
773 #clock-cells = <0>;
774 compatible = "ti,keystone,psc-clock";
775 clocks = <&clkmodrst0>;
776 clock-output-names = "usim";
777 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
778 reg-names = "control", "domain";
779 domain-id = <0>;
780 };
781
782 clki2c: clki2c {
783 #clock-cells = <0>;
784 compatible = "ti,keystone,psc-clock";
785 clocks = <&clkmodrst0>;
786 clock-output-names = "i2c";
787 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
788 reg-names = "control", "domain";
789 domain-id = <0>;
790 };
791
792 clkspi: clkspi {
793 #clock-cells = <0>;
794 compatible = "ti,keystone,psc-clock";
795 clocks = <&clkaemifspi>;
796 clock-output-names = "spi";
797 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
798 reg-names = "control", "domain";
799 domain-id = <0>;
800 };
801
802 clkgpio: clkgpio {
803 #clock-cells = <0>;
804 compatible = "ti,keystone,psc-clock";
805 clocks = <&clkmodrst0>;
806 clock-output-names = "gpio";
807 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
808 reg-names = "control", "domain";
809 domain-id = <0>;
810 };
811
812 clkkeymgr: clkkeymgr {
813 #clock-cells = <0>;
814 compatible = "ti,keystone,psc-clock";
815 clocks = <&clkmodrst0>;
816 clock-output-names = "keymgr";
817 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
818 reg-names = "control", "domain";
819 domain-id = <0>;
820 };
821};
diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts
index a68e34bbecb2..100bdf52b847 100644
--- a/arch/arm/boot/dts/keystone.dts
+++ b/arch/arm/boot/dts/keystone.dts
@@ -100,13 +100,15 @@
100 reg = <0x023100e8 4>; /* pll reset control reg */ 100 reg = <0x023100e8 4>; /* pll reset control reg */
101 }; 101 };
102 102
103 /include/ "keystone-clocks.dtsi"
104
103 uart0: serial@02530c00 { 105 uart0: serial@02530c00 {
104 compatible = "ns16550a"; 106 compatible = "ns16550a";
105 current-speed = <115200>; 107 current-speed = <115200>;
106 reg-shift = <2>; 108 reg-shift = <2>;
107 reg-io-width = <4>; 109 reg-io-width = <4>;
108 reg = <0x02530c00 0x100>; 110 reg = <0x02530c00 0x100>;
109 clock-frequency = <133120000>; 111 clocks = <&clkuart0>;
110 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 112 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
111 }; 113 };
112 114
@@ -116,9 +118,66 @@
116 reg-shift = <2>; 118 reg-shift = <2>;
117 reg-io-width = <4>; 119 reg-io-width = <4>;
118 reg = <0x02531000 0x100>; 120 reg = <0x02531000 0x100>;
119 clock-frequency = <133120000>; 121 clocks = <&clkuart1>;
120 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; 122 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
121 }; 123 };
122 124
125 i2c0: i2c@2530000 {
126 compatible = "ti,davinci-i2c";
127 reg = <0x02530000 0x400>;
128 clock-frequency = <100000>;
129 clocks = <&clki2c>;
130 interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
131 #address-cells = <1>;
132 #size-cells = <0>;
133
134 dtt@50 {
135 compatible = "at,24c1024";
136 reg = <0x50>;
137 };
138 };
139
140 i2c1: i2c@2530400 {
141 compatible = "ti,davinci-i2c";
142 reg = <0x02530400 0x400>;
143 clock-frequency = <100000>;
144 clocks = <&clki2c>;
145 interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
146 };
147
148 i2c2: i2c@2530800 {
149 compatible = "ti,davinci-i2c";
150 reg = <0x02530800 0x400>;
151 clock-frequency = <100000>;
152 clocks = <&clki2c>;
153 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
154 };
155
156 spi0: spi@21000400 {
157 compatible = "ti,dm6441-spi";
158 reg = <0x21000400 0x200>;
159 num-cs = <4>;
160 ti,davinci-spi-intr-line = <0>;
161 interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
162 clocks = <&clkspi>;
163 };
164
165 spi1: spi@21000600 {
166 compatible = "ti,dm6441-spi";
167 reg = <0x21000600 0x200>;
168 num-cs = <4>;
169 ti,davinci-spi-intr-line = <0>;
170 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
171 clocks = <&clkspi>;
172 };
173
174 spi2: spi@21000800 {
175 compatible = "ti,dm6441-spi";
176 reg = <0x21000800 0x200>;
177 num-cs = <4>;
178 ti,davinci-spi-intr-line = <0>;
179 interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
180 clocks = <&clkspi>;
181 };
123 }; 182 };
124}; 183};
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
new file mode 100644
index 000000000000..46b82aa7dc4e
--- /dev/null
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -0,0 +1,36 @@
1/*
2 * Device Tree Source for the r7s72100 SoC
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/ {
12 compatible = "renesas,r7s72100";
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 cpu@0 {
22 device_type = "cpu";
23 compatible = "arm,cortex-a9";
24 reg = <0>;
25 };
26 };
27
28 gic: interrupt-controller@e8201000 {
29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>;
31 #address-cells = <0>;
32 interrupt-controller;
33 reg = <0xe8201000 0x1000>,
34 <0xe8202000 0x1000>;
35 };
36};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
new file mode 100644
index 000000000000..bbed43bd9be9
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -0,0 +1,41 @@
1/*
2 * Device Tree Source for the r8a7791 SoC
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/ {
13 compatible = "renesas,r8a7791";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 device_type = "cpu";
24 compatible = "arm,cortex-a15";
25 reg = <0>;
26 clock-frequency = <1300000000>;
27 };
28 };
29
30 gic: interrupt-controller@f1001000 {
31 compatible = "arm,cortex-a15-gic";
32 #interrupt-cells = <3>;
33 #address-cells = <0>;
34 interrupt-controller;
35 reg = <0 0xf1001000 0 0x1000>,
36 <0 0xf1002000 0 0x1000>,
37 <0 0xf1004000 0 0x2000>,
38 <0 0xf1006000 0 0x2000>;
39 interrupts = <1 9 0xf04>;
40 };
41};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 14:36:03 -0400