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-rw-r--r--Documentation/clk.txt16
-rw-r--r--Documentation/devicetree/bindings/clock/bcm-kona-clock.txt116
-rw-r--r--Documentation/devicetree/bindings/clock/clock-bindings.txt9
-rw-r--r--Documentation/devicetree/bindings/clock/fixed-clock.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/hix5hd2-clock.txt31
-rw-r--r--Documentation/devicetree/bindings/clock/lsi,axm5516-clks.txt29
-rw-r--r--Documentation/devicetree/bindings/clock/mvebu-core-clock.txt8
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt41
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt27
11 files changed, 234 insertions, 46 deletions
diff --git a/Documentation/clk.txt b/Documentation/clk.txt
index c9c399af7c08..1fee72f4d331 100644
--- a/Documentation/clk.txt
+++ b/Documentation/clk.txt
@@ -68,21 +68,27 @@ the operations defined in clk.h:
68 int (*is_enabled)(struct clk_hw *hw); 68 int (*is_enabled)(struct clk_hw *hw);
69 unsigned long (*recalc_rate)(struct clk_hw *hw, 69 unsigned long (*recalc_rate)(struct clk_hw *hw,
70 unsigned long parent_rate); 70 unsigned long parent_rate);
71 long (*round_rate)(struct clk_hw *hw, unsigned long, 71 long (*round_rate)(struct clk_hw *hw,
72 unsigned long *); 72 unsigned long rate,
73 unsigned long *parent_rate);
73 long (*determine_rate)(struct clk_hw *hw, 74 long (*determine_rate)(struct clk_hw *hw,
74 unsigned long rate, 75 unsigned long rate,
75 unsigned long *best_parent_rate, 76 unsigned long *best_parent_rate,
76 struct clk **best_parent_clk); 77 struct clk **best_parent_clk);
77 int (*set_parent)(struct clk_hw *hw, u8 index); 78 int (*set_parent)(struct clk_hw *hw, u8 index);
78 u8 (*get_parent)(struct clk_hw *hw); 79 u8 (*get_parent)(struct clk_hw *hw);
79 int (*set_rate)(struct clk_hw *hw, unsigned long); 80 int (*set_rate)(struct clk_hw *hw,
81 unsigned long rate,
82 unsigned long parent_rate);
80 int (*set_rate_and_parent)(struct clk_hw *hw, 83 int (*set_rate_and_parent)(struct clk_hw *hw,
81 unsigned long rate, 84 unsigned long rate,
82 unsigned long parent_rate, u8 index); 85 unsigned long parent_rate,
86 u8 index);
83 unsigned long (*recalc_accuracy)(struct clk_hw *hw, 87 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
84 unsigned long parent_accuracy); 88 unsigned long parent_accuracy);
85 void (*init)(struct clk_hw *hw); 89 void (*init)(struct clk_hw *hw);
90 int (*debug_init)(struct clk_hw *hw,
91 struct dentry *dentry);
86 }; 92 };
87 93
88 Part 3 - hardware clk implementations 94 Part 3 - hardware clk implementations
diff --git a/Documentation/devicetree/bindings/clock/bcm-kona-clock.txt b/Documentation/devicetree/bindings/clock/bcm-kona-clock.txt
index 56d1f4961075..5286e260fcae 100644
--- a/Documentation/devicetree/bindings/clock/bcm-kona-clock.txt
+++ b/Documentation/devicetree/bindings/clock/bcm-kona-clock.txt
@@ -10,12 +10,12 @@ This binding uses the common clock binding:
10 10
11Required properties: 11Required properties:
12- compatible 12- compatible
13 Shall have one of the following values: 13 Shall have a value of the form "brcm,<model>-<which>-ccu",
14 - "brcm,bcm11351-root-ccu" 14 where <model> is a Broadcom SoC model number and <which> is
15 - "brcm,bcm11351-aon-ccu" 15 the name of a defined CCU. For example:
16 - "brcm,bcm11351-hub-ccu" 16 "brcm,bcm11351-root-ccu"
17 - "brcm,bcm11351-master-ccu" 17 The compatible strings used for each supported SoC family
18 - "brcm,bcm11351-slave-ccu" 18 are defined below.
19- reg 19- reg
20 Shall define the base and range of the address space 20 Shall define the base and range of the address space
21 containing clock control registers 21 containing clock control registers
@@ -26,12 +26,48 @@ Required properties:
26 Shall be an ordered list of strings defining the names of 26 Shall be an ordered list of strings defining the names of
27 the clocks provided by the CCU. 27 the clocks provided by the CCU.
28 28
29Device tree example:
30
31 slave_ccu: slave_ccu {
32 compatible = "brcm,bcm11351-slave-ccu";
33 reg = <0x3e011000 0x0f00>;
34 #clock-cells = <1>;
35 clock-output-names = "uartb",
36 "uartb2",
37 "uartb3",
38 "uartb4";
39 };
40
41 ref_crystal_clk: ref_crystal {
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <26000000>;
45 };
46
47 uart@3e002000 {
48 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
49 status = "disabled";
50 reg = <0x3e002000 0x1000>;
51 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
52 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
53 reg-shift = <2>;
54 reg-io-width = <4>;
55 };
56
57BCM281XX family
58---------------
59CCU compatible string values for SoCs in the BCM281XX family are:
60 "brcm,bcm11351-root-ccu"
61 "brcm,bcm11351-aon-ccu"
62 "brcm,bcm11351-hub-ccu"
63 "brcm,bcm11351-master-ccu"
64 "brcm,bcm11351-slave-ccu"
29 65
30BCM281XX family SoCs use Kona CCUs. The following table defines 66The following table defines the set of CCUs and clock specifiers for
31the set of CCUs and clock specifiers for BCM281XX clocks. When 67BCM281XX family clocks. When a clock consumer references a clocks,
32a clock consumer references a clocks, its symbolic specifier 68its symbolic specifier (rather than its numeric index value) should
33(rather than its numeric index value) should be used. These 69be used. These specifiers are defined in:
34specifiers are defined in "include/dt-bindings/clock/bcm281xx.h". 70 "include/dt-bindings/clock/bcm281xx.h"
35 71
36 CCU Clock Type Index Specifier 72 CCU Clock Type Index Specifier
37 --- ----- ---- ----- --------- 73 --- ----- ---- ----- ---------
@@ -64,30 +100,40 @@ specifiers are defined in "include/dt-bindings/clock/bcm281xx.h".
64 slave pwm peri 9 BCM281XX_SLAVE_CCU_PWM 100 slave pwm peri 9 BCM281XX_SLAVE_CCU_PWM
65 101
66 102
67Device tree example: 103BCM21664 family
104---------------
105CCU compatible string values for SoCs in the BCM21664 family are:
106 "brcm,bcm21664-root-ccu"
107 "brcm,bcm21664-aon-ccu"
108 "brcm,bcm21664-master-ccu"
109 "brcm,bcm21664-slave-ccu"
68 110
69 slave_ccu: slave_ccu { 111The following table defines the set of CCUs and clock specifiers for
70 compatible = "brcm,bcm11351-slave-ccu"; 112BCM21664 family clocks. When a clock consumer references a clocks,
71 reg = <0x3e011000 0x0f00>; 113its symbolic specifier (rather than its numeric index value) should
72 #clock-cells = <1>; 114be used. These specifiers are defined in:
73 clock-output-names = "uartb", 115 "include/dt-bindings/clock/bcm21664.h"
74 "uartb2",
75 "uartb3",
76 "uartb4";
77 };
78 116
79 ref_crystal_clk: ref_crystal { 117 CCU Clock Type Index Specifier
80 #clock-cells = <0>; 118 --- ----- ---- ----- ---------
81 compatible = "fixed-clock"; 119 root frac_1m peri 0 BCM21664_ROOT_CCU_FRAC_1M
82 clock-frequency = <26000000>;
83 };
84 120
85 uart@3e002000 { 121 aon hub_timer peri 0 BCM21664_AON_CCU_HUB_TIMER
86 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; 122
87 status = "disabled"; 123 master sdio1 peri 0 BCM21664_MASTER_CCU_SDIO1
88 reg = <0x3e002000 0x1000>; 124 master sdio2 peri 1 BCM21664_MASTER_CCU_SDIO2
89 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; 125 master sdio3 peri 2 BCM21664_MASTER_CCU_SDIO3
90 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 126 master sdio4 peri 3 BCM21664_MASTER_CCU_SDIO4
91 reg-shift = <2>; 127 master sdio1_sleep peri 4 BCM21664_MASTER_CCU_SDIO1_SLEEP
92 reg-io-width = <4>; 128 master sdio2_sleep peri 5 BCM21664_MASTER_CCU_SDIO2_SLEEP
93 }; 129 master sdio3_sleep peri 6 BCM21664_MASTER_CCU_SDIO3_SLEEP
130 master sdio4_sleep peri 7 BCM21664_MASTER_CCU_SDIO4_SLEEP
131
132 slave uartb peri 0 BCM21664_SLAVE_CCU_UARTB
133 slave uartb2 peri 1 BCM21664_SLAVE_CCU_UARTB2
134 slave uartb3 peri 2 BCM21664_SLAVE_CCU_UARTB3
135 slave uartb4 peri 3 BCM21664_SLAVE_CCU_UARTB4
136 slave bsc1 peri 4 BCM21664_SLAVE_CCU_BSC1
137 slave bsc2 peri 5 BCM21664_SLAVE_CCU_BSC2
138 slave bsc3 peri 6 BCM21664_SLAVE_CCU_BSC3
139 slave bsc4 peri 7 BCM21664_SLAVE_CCU_BSC4
diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt
index 700e7aac3717..f15787817d6b 100644
--- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
+++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -44,10 +44,9 @@ For example:
44 clocks by index. The names should reflect the clock output signal 44 clocks by index. The names should reflect the clock output signal
45 names for the device. 45 names for the device.
46 46
47clock-indices: If the identifyng number for the clocks in the node 47clock-indices: If the identifying number for the clocks in the node
48 is not linear from zero, then the this mapping allows 48 is not linear from zero, then this allows the mapping of
49 the mapping of identifiers into the clock-output-names 49 identifiers into the clock-output-names array.
50 array.
51 50
52For example, if we have two clocks <&oscillator 1> and <&oscillator 3>: 51For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
53 52
@@ -58,7 +57,7 @@ For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
58 clock-output-names = "clka", "clkb"; 57 clock-output-names = "clka", "clkb";
59 } 58 }
60 59
61 This ensures we do not have any empty nodes in clock-output-names 60 This ensures we do not have any empty strings in clock-output-names
62 61
63 62
64==Clock consumers== 63==Clock consumers==
diff --git a/Documentation/devicetree/bindings/clock/fixed-clock.txt b/Documentation/devicetree/bindings/clock/fixed-clock.txt
index 48ea0ad8ad46..0641a663ad69 100644
--- a/Documentation/devicetree/bindings/clock/fixed-clock.txt
+++ b/Documentation/devicetree/bindings/clock/fixed-clock.txt
@@ -12,7 +12,6 @@ Required properties:
12Optional properties: 12Optional properties:
13- clock-accuracy : accuracy of clock in ppb (parts per billion). 13- clock-accuracy : accuracy of clock in ppb (parts per billion).
14 Should be a single cell. 14 Should be a single cell.
15- gpios : From common gpio binding; gpio connection to clock enable pin.
16- clock-output-names : From common clock binding. 15- clock-output-names : From common clock binding.
17 16
18Example: 17Example:
diff --git a/Documentation/devicetree/bindings/clock/hix5hd2-clock.txt b/Documentation/devicetree/bindings/clock/hix5hd2-clock.txt
new file mode 100644
index 000000000000..7894a64887cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hix5hd2-clock.txt
@@ -0,0 +1,31 @@
1* Hisilicon Hix5hd2 Clock Controller
2
3The hix5hd2 clock controller generates and supplies clock to various
4controllers within the hix5hd2 SoC.
5
6Required Properties:
7
8- compatible: should be "hisilicon,hix5hd2-clock"
9- reg: Address and length of the register set
10- #clock-cells: Should be <1>
11
12Each clock is assigned an identifier and client nodes use this identifier
13to specify the clock which they consume.
14
15All these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>.
16
17Examples:
18 clock: clock@f8a22000 {
19 compatible = "hisilicon,hix5hd2-clock";
20 reg = <0xf8a22000 0x1000>;
21 #clock-cells = <1>;
22 };
23
24 uart0: uart@f8b00000 {
25 compatible = "arm,pl011", "arm,primecell";
26 reg = <0xf8b00000 0x1000>;
27 interrupts = <0 49 4>;
28 clocks = <&clock HIX5HD2_FIXED_83M>;
29 clock-names = "apb_pclk";
30 status = "disabled";
31 };
diff --git a/Documentation/devicetree/bindings/clock/lsi,axm5516-clks.txt b/Documentation/devicetree/bindings/clock/lsi,axm5516-clks.txt
new file mode 100644
index 000000000000..3ce97cfe999b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/lsi,axm5516-clks.txt
@@ -0,0 +1,29 @@
1AXM5516 clock driver bindings
2-----------------------------
3
4Required properties :
5- compatible : shall contain "lsi,axm5516-clks"
6- reg : shall contain base register location and length
7- #clock-cells : shall contain 1
8
9The consumer specifies the desired clock by having the clock ID in its "clocks"
10phandle cell. See <dt-bindings/clock/lsi,axxia-clock.h> for the list of
11supported clock IDs.
12
13Example:
14
15 clks: clock-controller@2010020000 {
16 compatible = "lsi,axm5516-clks";
17 #clock-cells = <1>;
18 reg = <0x20 0x10020000 0 0x20000>;
19 };
20
21 serial0: uart@2010080000 {
22 compatible = "arm,pl011", "arm,primecell";
23 reg = <0x20 0x10080000 0 0x1000>;
24 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
25 clocks = <&clks AXXIA_CLK_PER>;
26 clock-names = "apb_pclk";
27 };
28 };
29
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index 307a503c5db8..dc5ea5b22da9 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -29,6 +29,11 @@ The following is a list of provided IDs and clock names on Kirkwood and Dove:
29 2 = l2clk (L2 Cache clock derived from CPU0 clock) 29 2 = l2clk (L2 Cache clock derived from CPU0 clock)
30 3 = ddrclk (DDR controller clock derived from CPU0 clock) 30 3 = ddrclk (DDR controller clock derived from CPU0 clock)
31 31
32The following is a list of provided IDs and clock names on Orion5x:
33 0 = tclk (Internal Bus clock)
34 1 = cpuclk (CPU0 clock)
35 2 = ddrclk (DDR controller clock derived from CPU0 clock)
36
32Required properties: 37Required properties:
33- compatible : shall be one of the following: 38- compatible : shall be one of the following:
34 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks 39 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
@@ -38,6 +43,9 @@ Required properties:
38 "marvell,dove-core-clock" - for Dove SoC core clocks 43 "marvell,dove-core-clock" - for Dove SoC core clocks
39 "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) 44 "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
40 "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC 45 "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
46 "marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
47 "marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
48 "marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
41- reg : shall be the register address of the Sample-At-Reset (SAR) register 49- reg : shall be the register address of the Sample-At-Reset (SAR) register
42- #clock-cells : from common clock binding; shall be set to 1 50- #clock-cells : from common clock binding; shall be set to 1
43 51
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 767401f42871..7b7104e8cb1e 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -4,6 +4,7 @@ Qualcomm Global Clock & Reset Controller Binding
4Required properties : 4Required properties :
5- compatible : shall contain only one of the following: 5- compatible : shall contain only one of the following:
6 6
7 "qcom,gcc-apq8064"
7 "qcom,gcc-msm8660" 8 "qcom,gcc-msm8660"
8 "qcom,gcc-msm8960" 9 "qcom,gcc-msm8960"
9 "qcom,gcc-msm8974" 10 "qcom,gcc-msm8974"
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 02a25d99ca61..30df825d72ef 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -10,6 +10,7 @@ index in the group, from 0 to 31.
10Required Properties: 10Required Properties:
11 11
12 - compatible: Must be one of the following 12 - compatible: Must be one of the following
13 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
13 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks 14 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
14 - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks 15 - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
15 - "renesas,cpg-mstp-clock" for generic MSTP gate clocks 16 - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt
new file mode 100644
index 000000000000..2c03302f86ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt
@@ -0,0 +1,41 @@
1These bindings should be considered EXPERIMENTAL for now.
2
3* Renesas R8A7740 Clock Pulse Generator (CPG)
4
5The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs
6and several fixed ratio and variable ratio dividers.
7
8Required Properties:
9
10 - compatible: Must be "renesas,r8a7740-cpg-clocks"
11
12 - reg: Base address and length of the memory resource used by the CPG
13
14 - clocks: Reference to the three parent clocks
15 - #clock-cells: Must be 1
16 - clock-output-names: The names of the clocks. Supported clocks are
17 "system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b",
18 "m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp".
19
20 - renesas,mode: board-specific settings of the MD_CK* bits
21
22
23Example
24-------
25
26cpg_clocks: cpg_clocks@e6150000 {
27 compatible = "renesas,r8a7740-cpg-clocks";
28 reg = <0xe6150000 0x10000>;
29 clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
30 #clock-cells = <1>;
31 clock-output-names = "system", "pllc0", "pllc1",
32 "pllc2", "r",
33 "usb24s",
34 "i", "zg", "b", "m1", "hp",
35 "hpp", "usbp", "s", "zb", "m3",
36 "cp";
37};
38
39&cpg_clocks {
40 renesas,mode = <0x05>;
41};
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
new file mode 100644
index 000000000000..ed3c8cb12f4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
@@ -0,0 +1,27 @@
1* Renesas R8A7779 Clock Pulse Generator (CPG)
2
3The CPG generates core clocks for the R8A7779. It includes one PLL and
4several fixed ratio dividers
5
6Required Properties:
7
8 - compatible: Must be "renesas,r8a7779-cpg-clocks"
9 - reg: Base address and length of the memory resource used by the CPG
10
11 - clocks: Reference to the parent clock
12 - #clock-cells: Must be 1
13 - clock-output-names: The names of the clocks. Supported clocks are "plla",
14 "z", "zs", "s", "s1", "p", "b", "out".
15
16
17Example
18-------
19
20 cpg_clocks: cpg_clocks@ffc80000 {
21 compatible = "renesas,r8a7779-cpg-clocks";
22 reg = <0 0xffc80000 0 0x30>;
23 clocks = <&extal_clk>;
24 #clock-cells = <1>;
25 clock-output-names = "plla", "z", "zs", "s", "s1", "p",
26 "b", "out";
27 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-28 02:40:52 -0500