Merge remote-tracking branch 'linaro/clk-next' into clk-next

11 files changed, 234 insertions, 46 deletions

diff --git a/Documentation/clk.txt b/Documentation/clk.txt
index c9c399af7c08..1fee72f4d331 100644
--- a/Documentation/clk.txt
+++ b/Documentation/clk.txt
@@ -68,21 +68,27 @@ the operations defined in clk.h:
                 int             (*is_enabled)(struct clk_hw *hw);
                 unsigned long   (*recalc_rate)(struct clk_hw *hw,
                                                 unsigned long parent_rate);
-                long            (*round_rate)(struct clk_hw *hw, unsigned long,
-                                                unsigned long *);
+                long            (*round_rate)(struct clk_hw *hw,
+                                                unsigned long rate,
+                                                unsigned long *parent_rate);
                 long            (*determine_rate)(struct clk_hw *hw,
                                                 unsigned long rate,
                                                 unsigned long *best_parent_rate,
                                                 struct clk **best_parent_clk);
                 int             (*set_parent)(struct clk_hw *hw, u8 index);
                 u8              (*get_parent)(struct clk_hw *hw);
-                int             (*set_rate)(struct clk_hw *hw, unsigned long);
+                int             (*set_rate)(struct clk_hw *hw,
+                                            unsigned long rate,
+                                            unsigned long parent_rate);
                 int             (*set_rate_and_parent)(struct clk_hw *hw,
                                             unsigned long rate,
-                                            unsigned long parent_rate, u8 index);
+                                            unsigned long parent_rate,
+                                            u8 index);
                 unsigned long   (*recalc_accuracy)(struct clk_hw *hw,
-                                                   unsigned long parent_accuracy);
+                                                unsigned long parent_accuracy);
                 void            (*init)(struct clk_hw *hw);
+                int             (*debug_init)(struct clk_hw *hw,
+                                              struct dentry *dentry);
         };
 
         Part 3 - hardware clk implementations
diff --git a/Documentation/devicetree/bindings/clock/bcm-kona-clock.txt b/Documentation/devicetree/bindings/clock/bcm-kona-clock.txt
index 56d1f4961075..5286e260fcae 100644
--- a/Documentation/devicetree/bindings/clock/bcm-kona-clock.txt
+++ b/Documentation/devicetree/bindings/clock/bcm-kona-clock.txt
@@ -10,12 +10,12 @@ This binding uses the common clock binding:
 
 Required properties:
 - compatible
-        Shall have one of the following values:
-        - "brcm,bcm11351-root-ccu"
-        - "brcm,bcm11351-aon-ccu"
-        - "brcm,bcm11351-hub-ccu"
-        - "brcm,bcm11351-master-ccu"
-        - "brcm,bcm11351-slave-ccu"
+        Shall have a value of the form "brcm,<model>-<which>-ccu",
+        where <model> is a Broadcom SoC model number and <which> is
+        the name of a defined CCU.  For example:
+            "brcm,bcm11351-root-ccu"
+        The compatible strings used for each supported SoC family
+        are defined below.
 - reg
         Shall define the base and range of the address space
         containing clock control registers
@@ -26,12 +26,48 @@ Required properties:
         Shall be an ordered list of strings defining the names of
         the clocks provided by the CCU.
 
+Device tree example:
+
+        slave_ccu: slave_ccu {
+                compatible = "brcm,bcm11351-slave-ccu";
+                reg = <0x3e011000 0x0f00>;
+                #clock-cells = <1>;
+                clock-output-names = "uartb",
+                                     "uartb2",
+                                     "uartb3",
+                                     "uartb4";
+        };
+
+        ref_crystal_clk: ref_crystal {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        uart@3e002000 {
+                compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
+                status = "disabled";
+                reg = <0x3e002000 0x1000>;
+                clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
+                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+        };
+
+BCM281XX family
+---------------
+CCU compatible string values for SoCs in the BCM281XX family are:
+    "brcm,bcm11351-root-ccu"
+    "brcm,bcm11351-aon-ccu"
+    "brcm,bcm11351-hub-ccu"
+    "brcm,bcm11351-master-ccu"
+    "brcm,bcm11351-slave-ccu"
 
-BCM281XX family SoCs use Kona CCUs.  The following table defines
-the set of CCUs and clock specifiers for BCM281XX clocks.  When
-a clock consumer references a clocks, its symbolic specifier
-(rather than its numeric index value) should be used.  These
-specifiers are defined in "include/dt-bindings/clock/bcm281xx.h".
+The following table defines the set of CCUs and clock specifiers for
+BCM281XX family clocks.  When a clock consumer references a clocks,
+its symbolic specifier (rather than its numeric index value) should
+be used.  These specifiers are defined in:
+    "include/dt-bindings/clock/bcm281xx.h"
 
     CCU     Clock           Type    Index   Specifier
     ---     -----           ----    -----   ---------
@@ -64,30 +100,40 @@ specifiers are defined in "include/dt-bindings/clock/bcm281xx.h".
     slave   pwm             peri      9     BCM281XX_SLAVE_CCU_PWM
 
 
-Device tree example:
+BCM21664 family
+---------------
+CCU compatible string values for SoCs in the BCM21664 family are:
+    "brcm,bcm21664-root-ccu"
+    "brcm,bcm21664-aon-ccu"
+    "brcm,bcm21664-master-ccu"
+    "brcm,bcm21664-slave-ccu"
 
-        slave_ccu: slave_ccu {
-                compatible = "brcm,bcm11351-slave-ccu";
-                reg = <0x3e011000 0x0f00>;
-                #clock-cells = <1>;
-                clock-output-names = "uartb",
-                                     "uartb2",
-                                     "uartb3",
-                                     "uartb4";
-        };
+The following table defines the set of CCUs and clock specifiers for
+BCM21664 family clocks.  When a clock consumer references a clocks,
+its symbolic specifier (rather than its numeric index value) should
+be used.  These specifiers are defined in:
+    "include/dt-bindings/clock/bcm21664.h"
 
-        ref_crystal_clk: ref_crystal {
-                #clock-cells = <0>;
-                compatible = "fixed-clock";
-                clock-frequency = <26000000>;
-        };
+    CCU     Clock           Type    Index   Specifier
+    ---     -----           ----    -----   ---------
+    root    frac_1m         peri      0     BCM21664_ROOT_CCU_FRAC_1M
 
-        uart@3e002000 {
-                compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
-                status = "disabled";
-                reg = <0x3e002000 0x1000>;
-                clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
-                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-                reg-shift = <2>;
-                reg-io-width = <4>;
-        };
+    aon     hub_timer       peri      0     BCM21664_AON_CCU_HUB_TIMER
+
+    master  sdio1           peri      0     BCM21664_MASTER_CCU_SDIO1
+    master  sdio2           peri      1     BCM21664_MASTER_CCU_SDIO2
+    master  sdio3           peri      2     BCM21664_MASTER_CCU_SDIO3
+    master  sdio4           peri      3     BCM21664_MASTER_CCU_SDIO4
+    master  sdio1_sleep     peri      4     BCM21664_MASTER_CCU_SDIO1_SLEEP
+    master  sdio2_sleep     peri      5     BCM21664_MASTER_CCU_SDIO2_SLEEP
+    master  sdio3_sleep     peri      6     BCM21664_MASTER_CCU_SDIO3_SLEEP
+    master  sdio4_sleep     peri      7     BCM21664_MASTER_CCU_SDIO4_SLEEP
+
+    slave   uartb           peri      0     BCM21664_SLAVE_CCU_UARTB
+    slave   uartb2          peri      1     BCM21664_SLAVE_CCU_UARTB2
+    slave   uartb3          peri      2     BCM21664_SLAVE_CCU_UARTB3
+    slave   uartb4          peri      3     BCM21664_SLAVE_CCU_UARTB4
+    slave   bsc1            peri      4     BCM21664_SLAVE_CCU_BSC1
+    slave   bsc2            peri      5     BCM21664_SLAVE_CCU_BSC2
+    slave   bsc3            peri      6     BCM21664_SLAVE_CCU_BSC3
+    slave   bsc4            peri      7     BCM21664_SLAVE_CCU_BSC4
diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt
index 700e7aac3717..f15787817d6b 100644
--- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
+++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -44,10 +44,9 @@ For example:
   clocks by index. The names should reflect the clock output signal
   names for the device.
 
-clock-indices:     If the identifyng number for the clocks in the node
-                   is not linear from zero, then the this mapping allows
-                   the mapping of identifiers into the clock-output-names
-                   array.
+clock-indices:     If the identifying number for the clocks in the node
+                   is not linear from zero, then this allows the mapping of
+                   identifiers into the clock-output-names array.
 
 For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
 
@@ -58,7 +57,7 @@ For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
                 clock-output-names = "clka", "clkb";
         }
 
-        This ensures we do not have any empty nodes in clock-output-names
+        This ensures we do not have any empty strings in clock-output-names
 
 
 ==Clock consumers==
diff --git a/Documentation/devicetree/bindings/clock/fixed-clock.txt b/Documentation/devicetree/bindings/clock/fixed-clock.txt
index 48ea0ad8ad46..0641a663ad69 100644
--- a/Documentation/devicetree/bindings/clock/fixed-clock.txt
+++ b/Documentation/devicetree/bindings/clock/fixed-clock.txt
@@ -12,7 +12,6 @@ Required properties:
 Optional properties:
 - clock-accuracy : accuracy of clock in ppb (parts per billion).
                    Should be a single cell.
-- gpios : From common gpio binding; gpio connection to clock enable pin.
 - clock-output-names : From common clock binding.
 
 Example:
diff --git a/Documentation/devicetree/bindings/clock/hix5hd2-clock.txt b/Documentation/devicetree/bindings/clock/hix5hd2-clock.txt
new file mode 100644
index 000000000000..7894a64887cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hix5hd2-clock.txt
@@ -0,0 +1,31 @@
+* Hisilicon Hix5hd2 Clock Controller
+
+The hix5hd2 clock controller generates and supplies clock to various
+controllers within the hix5hd2 SoC.
+
+Required Properties:
+
+- compatible: should be "hisilicon,hix5hd2-clock"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>.
+
+Examples:
+        clock: clock@f8a22000 {
+                compatible = "hisilicon,hix5hd2-clock";
+                reg = <0xf8a22000 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        uart0: uart@f8b00000 {
+                compatible = "arm,pl011", "arm,primecell";
+                reg = <0xf8b00000 0x1000>;
+                interrupts = <0 49 4>;
+                clocks = <&clock HIX5HD2_FIXED_83M>;
+                clock-names = "apb_pclk";
+                status = "disabled";
+        };
diff --git a/Documentation/devicetree/bindings/clock/lsi,axm5516-clks.txt b/Documentation/devicetree/bindings/clock/lsi,axm5516-clks.txt
new file mode 100644
index 000000000000..3ce97cfe999b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/lsi,axm5516-clks.txt
@@ -0,0 +1,29 @@
+AXM5516 clock driver bindings
+-----------------------------
+
+Required properties :
+- compatible : shall contain "lsi,axm5516-clks"
+- reg : shall contain base register location and length
+- #clock-cells : shall contain 1
+
+The consumer specifies the desired clock by having the clock ID in its "clocks"
+phandle cell. See <dt-bindings/clock/lsi,axxia-clock.h> for the list of
+supported clock IDs.
+
+Example:
+
+        clks: clock-controller@2010020000 {
+                compatible = "lsi,axm5516-clks";
+                #clock-cells = <1>;
+                reg = <0x20 0x10020000 0 0x20000>;
+        };
+
+        serial0: uart@2010080000 {
+                compatible = "arm,pl011", "arm,primecell";
+                reg = <0x20 0x10080000 0 0x1000>;
+                interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clks AXXIA_CLK_PER>;
+                clock-names = "apb_pclk";
+        };
+                                                                                                                                                                                                                                                                };
+
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index 307a503c5db8..dc5ea5b22da9 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -29,6 +29,11 @@ The following is a list of provided IDs and clock names on Kirkwood and Dove:
  2 = l2clk  (L2 Cache clock derived from CPU0 clock)
  3 = ddrclk (DDR controller clock derived from CPU0 clock)
 
+The following is a list of provided IDs and clock names on Orion5x:
+ 0 = tclk   (Internal Bus clock)
+ 1 = cpuclk (CPU0 clock)
+ 2 = ddrclk (DDR controller clock derived from CPU0 clock)
+
 Required properties:
 - compatible : shall be one of the following:
         "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
@@ -38,6 +43,9 @@ Required properties:
         "marvell,dove-core-clock" - for Dove SoC core clocks
         "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
         "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
+        "marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
+        "marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
+        "marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
 - reg : shall be the register address of the Sample-At-Reset (SAR) register
 - #clock-cells : from common clock binding; shall be set to 1
 
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 767401f42871..7b7104e8cb1e 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -4,6 +4,7 @@ Qualcomm Global Clock & Reset Controller Binding
 Required properties :
 - compatible : shall contain only one of the following:
 
+                        "qcom,gcc-apq8064"
                         "qcom,gcc-msm8660"
                         "qcom,gcc-msm8960"
                         "qcom,gcc-msm8974"
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 02a25d99ca61..30df825d72ef 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -10,6 +10,7 @@ index in the group, from 0 to 31.
 Required Properties:
 
   - compatible: Must be one of the following
+    - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
     - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
     - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
     - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt
new file mode 100644
index 000000000000..2c03302f86ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7740-cpg-clocks.txt
@@ -0,0 +1,41 @@
+These bindings should be considered EXPERIMENTAL for now.
+
+* Renesas R8A7740  Clock Pulse Generator (CPG)
+
+The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs
+and several fixed ratio and variable ratio dividers.
+
+Required Properties:
+
+  - compatible: Must be "renesas,r8a7740-cpg-clocks"
+
+  - reg: Base address and length of the memory resource used by the CPG
+
+  - clocks: Reference to the three parent clocks
+  - #clock-cells: Must be 1
+  - clock-output-names: The names of the clocks. Supported clocks are
+    "system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b",
+    "m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp".
+
+  - renesas,mode: board-specific settings of the MD_CK* bits
+
+
+Example
+-------
+
+cpg_clocks: cpg_clocks@e6150000 {
+        compatible = "renesas,r8a7740-cpg-clocks";
+        reg = <0xe6150000 0x10000>;
+        clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
+        #clock-cells = <1>;
+        clock-output-names = "system", "pllc0", "pllc1",
+                             "pllc2", "r",
+                             "usb24s",
+                             "i", "zg", "b", "m1", "hp",
+                             "hpp", "usbp", "s", "zb", "m3",
+                             "cp";
+};
+
+&cpg_clocks {
+        renesas,mode = <0x05>;
+};
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
new file mode 100644
index 000000000000..ed3c8cb12f4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
@@ -0,0 +1,27 @@
+* Renesas R8A7779 Clock Pulse Generator (CPG)
+
+The CPG generates core clocks for the R8A7779. It includes one PLL and
+several fixed ratio dividers
+
+Required Properties:
+
+  - compatible: Must be "renesas,r8a7779-cpg-clocks"
+  - reg: Base address and length of the memory resource used by the CPG
+
+  - clocks: Reference to the parent clock
+  - #clock-cells: Must be 1
+  - clock-output-names: The names of the clocks. Supported clocks are "plla",
+    "z", "zs", "s", "s1", "p", "b", "out".
+
+
+Example
+-------
+
+        cpg_clocks: cpg_clocks@ffc80000 {
+                compatible = "renesas,r8a7779-cpg-clocks";
+                reg = <0 0xffc80000 0 0x30>;
+                clocks = <&extal_clk>;
+                #clock-cells = <1>;
+                clock-output-names = "plla", "z", "zs", "s", "s1", "p",
+                                     "b", "out";
+        };