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-rw-r--r--Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt14
-rw-r--r--Documentation/devicetree/bindings/clock/altr_socfpga.txt5
-rw-r--r--Documentation/devicetree/bindings/clock/axi-clkgen.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/clock-bindings.txt17
-rw-r--r--Documentation/devicetree/bindings/clock/hi3620-clock.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt48
-rw-r--r--Documentation/devicetree/bindings/clock/mvebu-core-clock.txt14
-rw-r--r--Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt5
-rw-r--r--Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt65
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt29
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt49
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt36
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt48
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt36
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt53
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,clkgen.txt83
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,quadfs.txt45
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt102
18 files changed, 623 insertions, 29 deletions
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 8c7a4653508d..df0a452b8526 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -30,3 +30,17 @@ Example:
30 resume-offset = <0x308>; 30 resume-offset = <0x308>;
31 reboot-offset = <0x4>; 31 reboot-offset = <0x4>;
32 }; 32 };
33
34PCTRL: Peripheral misc control register
35
36Required Properties:
37- compatible: "hisilicon,pctrl"
38- reg: Address and size of pctrl.
39
40Example:
41
42 /* for Hi3620 */
43 pctrl: pctrl@fca09000 {
44 compatible = "hisilicon,pctrl";
45 reg = <0xfca09000 0x1000>;
46 };
diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index 0045433eae1f..5dfd145d3ccf 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -23,3 +23,8 @@ Optional properties:
23 and the bit index. 23 and the bit index.
24- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift, 24- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
25 and width. 25 and width.
26- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
27 the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
28 value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
29 hold/delay times that is needed for the SD/MMC CIU clock. The values of both
30 can be 0-315 degrees, in 45 degree increments.
diff --git a/Documentation/devicetree/bindings/clock/axi-clkgen.txt b/Documentation/devicetree/bindings/clock/axi-clkgen.txt
index 028b493e97ff..20e1704e7df2 100644
--- a/Documentation/devicetree/bindings/clock/axi-clkgen.txt
+++ b/Documentation/devicetree/bindings/clock/axi-clkgen.txt
@@ -5,7 +5,7 @@ This binding uses the common clock binding[1].
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6 6
7Required properties: 7Required properties:
8- compatible : shall be "adi,axi-clkgen". 8- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
9- #clock-cells : from common clock binding; Should always be set to 0. 9- #clock-cells : from common clock binding; Should always be set to 0.
10- reg : Address and length of the axi-clkgen register set. 10- reg : Address and length of the axi-clkgen register set.
11- clocks : Phandle and clock specifier for the parent clock. 11- clocks : Phandle and clock specifier for the parent clock.
diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt
index 7c52c29d99fa..700e7aac3717 100644
--- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
+++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -44,6 +44,23 @@ For example:
44 clocks by index. The names should reflect the clock output signal 44 clocks by index. The names should reflect the clock output signal
45 names for the device. 45 names for the device.
46 46
47clock-indices: If the identifyng number for the clocks in the node
48 is not linear from zero, then the this mapping allows
49 the mapping of identifiers into the clock-output-names
50 array.
51
52For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
53
54 oscillator {
55 compatible = "myclocktype";
56 #clock-cells = <1>;
57 clock-indices = <1>, <3>;
58 clock-output-names = "clka", "clkb";
59 }
60
61 This ensures we do not have any empty nodes in clock-output-names
62
63
47==Clock consumers== 64==Clock consumers==
48 65
49Required properties: 66Required properties:
diff --git a/Documentation/devicetree/bindings/clock/hi3620-clock.txt b/Documentation/devicetree/bindings/clock/hi3620-clock.txt
index 4b71ab41be53..dad6269f52c5 100644
--- a/Documentation/devicetree/bindings/clock/hi3620-clock.txt
+++ b/Documentation/devicetree/bindings/clock/hi3620-clock.txt
@@ -7,6 +7,7 @@ Required Properties:
7 7
8- compatible: should be one of the following. 8- compatible: should be one of the following.
9 - "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC. 9 - "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC.
10 - "hisilicon,hi3620-mmc-clock" - controller specific for Hi3620 mmc.
10 11
11- reg: physical base address of the controller and length of memory mapped 12- reg: physical base address of the controller and length of memory mapped
12 region. 13 region.
diff --git a/Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt b/Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt
new file mode 100644
index 000000000000..fedea84314a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt
@@ -0,0 +1,48 @@
1Device Tree Clock bindings for arch-moxart
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7MOXA ART SoCs allow to determine PLL output and APB frequencies
8by reading registers holding multiplier and divisor information.
9
10
11PLL:
12
13Required properties:
14- compatible : Must be "moxa,moxart-pll-clock"
15- #clock-cells : Should be 0
16- reg : Should contain registers location and length
17- clocks : Should contain phandle + clock-specifier for the parent clock
18
19Optional properties:
20- clock-output-names : Should contain clock name
21
22
23APB:
24
25Required properties:
26- compatible : Must be "moxa,moxart-apb-clock"
27- #clock-cells : Should be 0
28- reg : Should contain registers location and length
29- clocks : Should contain phandle + clock-specifier for the parent clock
30
31Optional properties:
32- clock-output-names : Should contain clock name
33
34
35For example:
36
37 clk_pll: clk_pll@98100000 {
38 compatible = "moxa,moxart-pll-clock";
39 #clock-cells = <0>;
40 reg = <0x98100000 0x34>;
41 };
42
43 clk_apb: clk_apb@98100000 {
44 compatible = "moxa,moxart-apb-clock";
45 #clock-cells = <0>;
46 reg = <0x98100000 0x34>;
47 clocks = <&clk_pll>;
48 };
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index 1e662948661e..307a503c5db8 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -11,6 +11,18 @@ The following is a list of provided IDs and clock names on Armada 370/XP:
11 3 = hclk (DRAM control clock) 11 3 = hclk (DRAM control clock)
12 4 = dramclk (DDR clock) 12 4 = dramclk (DDR clock)
13 13
14The following is a list of provided IDs and clock names on Armada 375:
15 0 = tclk (Internal Bus clock)
16 1 = cpuclk (CPU clock)
17 2 = l2clk (L2 Cache clock)
18 3 = ddrclk (DDR clock)
19
20The following is a list of provided IDs and clock names on Armada 380/385:
21 0 = tclk (Internal Bus clock)
22 1 = cpuclk (CPU clock)
23 2 = l2clk (L2 Cache clock)
24 3 = ddrclk (DDR clock)
25
14The following is a list of provided IDs and clock names on Kirkwood and Dove: 26The following is a list of provided IDs and clock names on Kirkwood and Dove:
15 0 = tclk (Internal Bus clock) 27 0 = tclk (Internal Bus clock)
16 1 = cpuclk (CPU0 clock) 28 1 = cpuclk (CPU0 clock)
@@ -20,6 +32,8 @@ The following is a list of provided IDs and clock names on Kirkwood and Dove:
20Required properties: 32Required properties:
21- compatible : shall be one of the following: 33- compatible : shall be one of the following:
22 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks 34 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
35 "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
36 "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
23 "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks 37 "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
24 "marvell,dove-core-clock" - for Dove SoC core clocks 38 "marvell,dove-core-clock" - for Dove SoC core clocks
25 "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) 39 "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
index c62391fc0e39..520562a7dc2a 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
@@ -4,7 +4,10 @@ The following is a list of provided IDs and clock names on Armada 370/XP:
4 0 = nand (NAND clock) 4 0 = nand (NAND clock)
5 5
6Required properties: 6Required properties:
7- compatible : must be "marvell,armada-370-corediv-clock" 7- compatible : must be "marvell,armada-370-corediv-clock",
8 "marvell,armada-375-corediv-clock",
9 "marvell,armada-380-corediv-clock",
10
8- reg : must be the register address of Core Divider control register 11- reg : must be the register address of Core Divider control register
9- #clock-cells : from common clock binding; shall be set to 1 12- #clock-cells : from common clock binding; shall be set to 1
10- clocks : must be set to the parent's phandle 13- clocks : must be set to the parent's phandle
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
index fc2910fa7e45..76477be742b2 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -1,9 +1,10 @@
1* Gated Clock bindings for Marvell EBU SoCs 1* Gated Clock bindings for Marvell EBU SoCs
2 2
3Marvell Armada 370/XP, Dove and Kirkwood allow some peripheral clocks to be 3Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some
4gated to save some power. The clock consumer should specify the desired clock 4peripheral clocks to be gated to save some power. The clock consumer
5by having the clock ID in its "clocks" phandle cell. The clock ID is directly 5should specify the desired clock by having the clock ID in its
6mapped to the corresponding clock gating control bit in HW to ease manual clock 6"clocks" phandle cell. The clock ID is directly mapped to the
7corresponding clock gating control bit in HW to ease manual clock
7lookup in datasheet. 8lookup in datasheet.
8 9
9The following is a list of provided IDs for Armada 370: 10The following is a list of provided IDs for Armada 370:
@@ -22,6 +23,60 @@ ID Clock Peripheral
2228 ddr DDR Cntrl 2328 ddr DDR Cntrl
2330 sata1 SATA Host 0 2430 sata1 SATA Host 0
24 25
26The following is a list of provided IDs for Armada 375:
27ID Clock Peripheral
28-----------------------------------
292 mu Management Unit
303 pp Packet Processor
314 ptp PTP
325 pex0 PCIe 0 Clock out
336 pex1 PCIe 1 Clock out
348 audio Audio Cntrl
3511 nd_clk Nand Flash Cntrl
3614 sata0_link SATA 0 Link
3715 sata0_core SATA 0 Core
3816 usb3 USB3 Host
3917 sdio SDHCI Host
4018 usb USB Host
4119 gop Gigabit Ethernet MAC
4220 sata1_link SATA 1 Link
4321 sata1_core SATA 1 Core
4422 xor0 XOR DMA 0
4523 xor1 XOR DMA 0
4624 copro Coprocessor
4725 tdm Time Division Mplx
4828 crypto0_enc Cryptographic Unit Port 0 Encryption
4929 crypto0_core Cryptographic Unit Port 0 Core
5030 crypto1_enc Cryptographic Unit Port 1 Encryption
5131 crypto1_core Cryptographic Unit Port 1 Core
52
53The following is a list of provided IDs for Armada 380/385:
54ID Clock Peripheral
55-----------------------------------
560 audio Audio
572 ge2 Gigabit Ethernet 2
583 ge1 Gigabit Ethernet 1
594 ge0 Gigabit Ethernet 0
605 pex1 PCIe 1
616 pex2 PCIe 2
627 pex3 PCIe 3
638 pex0 PCIe 0
649 usb3h0 USB3 Host 0
6510 usb3h1 USB3 Host 1
6611 usb3d USB3 Device
6713 bm Buffer Management
6814 crypto0z Cryptographic 0 Z
6915 sata0 SATA 0
7016 crypto1z Cryptographic 1 Z
7117 sdio SDIO
7218 usb2 USB 2
7321 crypto1 Cryptographic 1
7422 xor0 XOR 0
7523 crypto0 Cryptographic 0
7625 tdm Time Division Multiplexing
7728 xor1 XOR 1
7830 sata1 SATA 1
79
25The following is a list of provided IDs for Armada XP: 80The following is a list of provided IDs for Armada XP:
26ID Clock Peripheral 81ID Clock Peripheral
27----------------------------------- 82-----------------------------------
@@ -95,6 +150,8 @@ ID Clock Peripheral
95Required properties: 150Required properties:
96- compatible : shall be one of the following: 151- compatible : shall be one of the following:
97 "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating 152 "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
153 "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
154 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
98 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating 155 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
99 "marvell,dove-gating-clock" - for Dove SoC clock gating 156 "marvell,dove-gating-clock" - for Dove SoC clock gating
100 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating 157 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
new file mode 100644
index 000000000000..98a257492522
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
@@ -0,0 +1,29 @@
1* Renesas RZ Clock Pulse Generator (CPG)
2
3The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
4CPU and GPU clocks, and several fixed ratio dividers.
5
6Required Properties:
7
8 - compatible: Must be one of
9 - "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
10 - "renesas,rz-cpg-clocks" for the generic RZ CPG
11 - reg: Base address and length of the memory resource used by the CPG
12 - clocks: References to possible parent clocks. Order must match clock modes
13 in the datasheet. For the r7s72100, this is extal, usb_x1.
14 - #clock-cells: Must be 1
15 - clock-output-names: The names of the clocks. Supported clocks are "pll",
16 "i", and "g"
17
18
19Example
20-------
21
22 cpg_clocks: cpg_clocks@fcfe0000 {
23 #clock-cells = <1>;
24 compatible = "renesas,r7s72100-cpg-clocks",
25 "renesas,rz-cpg-clocks";
26 reg = <0xfcfe0000 0x18>;
27 clocks = <&extal_clk>, <&usb_x1_clk>;
28 clock-output-names = "pll", "i", "g";
29 };
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
new file mode 100644
index 000000000000..ae56315fcec5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
@@ -0,0 +1,49 @@
1Binding for a ST divider and multiplexer clock driver.
2
3This binding uses the common clock binding[1].
4Base address is located to the parent node. See clock binding[2]
5
6[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
8
9Required properties:
10
11- compatible : shall be:
12 "st,clkgena-divmux-c65-hs", "st,clkgena-divmux"
13 "st,clkgena-divmux-c65-ls", "st,clkgena-divmux"
14 "st,clkgena-divmux-c32-odf0", "st,clkgena-divmux"
15 "st,clkgena-divmux-c32-odf1", "st,clkgena-divmux"
16 "st,clkgena-divmux-c32-odf2", "st,clkgena-divmux"
17 "st,clkgena-divmux-c32-odf3", "st,clkgena-divmux"
18
19- #clock-cells : From common clock binding; shall be set to 1.
20
21- clocks : From common clock binding
22
23- clock-output-names : From common clock binding.
24
25Example:
26
27 clockgenA@fd345000 {
28 reg = <0xfd345000 0xb50>;
29
30 CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
31 #clock-cells = <1>;
32 compatible = "st,clkgena-divmux-c32-odf1",
33 "st,clkgena-divmux";
34
35 clocks = <&CLK_M_A1_OSC_PREDIV>,
36 <&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
37 <&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
38
39 clock-output-names = "CLK_M_RX_ICN_TS",
40 "CLK_M_RX_ICN_VDP_0",
41 "", /* Unused */
42 "CLK_M_PRV_T1_BUS",
43 "CLK_M_ICN_REG_12",
44 "CLK_M_ICN_REG_10",
45 "", /* Unused */
46 "CLK_M_ICN_ST231";
47 };
48 };
49
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
new file mode 100644
index 000000000000..943e0808e212
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
@@ -0,0 +1,36 @@
1Binding for a ST multiplexed clock driver.
2
3This binding supports only simple indexed multiplexers, it does not
4support table based parent index to hardware value translations.
5
6This binding uses the common clock binding[1].
7
8[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9
10Required properties:
11
12- compatible : shall be:
13 "st,stih416-clkgenc-vcc-hd", "st,clkgen-mux"
14 "st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux"
15 "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"
16 "st,stih416-clkgenf-vcc-hd", "st,clkgen-mux"
17 "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
18 "st,stih415-clkgen-a9-mux", "st,clkgen-mux"
19 "st,stih416-clkgen-a9-mux", "st,clkgen-mux"
20
21
22- #clock-cells : from common clock binding; shall be set to 0.
23
24- reg : A Base address and length of the register set.
25
26- clocks : from common clock binding
27
28Example:
29
30 CLK_M_HVA: CLK_M_HVA {
31 #clock-cells = <0>;
32 compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
33 reg = <0xfd690868 4>;
34
35 clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;
36 };
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
new file mode 100644
index 000000000000..81eb3855ab92
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -0,0 +1,48 @@
1Binding for a ST pll clock driver.
2
3This binding uses the common clock binding[1].
4Base address is located to the parent node. See clock binding[2]
5
6[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
8
9Required properties:
10
11- compatible : shall be:
12 "st,clkgena-prediv-c65", "st,clkgena-prediv"
13 "st,clkgena-prediv-c32", "st,clkgena-prediv"
14
15 "st,clkgena-plls-c65"
16 "st,plls-c32-a1x-0", "st,clkgen-plls-c32"
17 "st,plls-c32-a1x-1", "st,clkgen-plls-c32"
18 "st,stih415-plls-c32-a9", "st,clkgen-plls-c32"
19 "st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
20 "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
21 "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
22
23 "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
24 "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
25
26
27- #clock-cells : From common clock binding; shall be set to 1.
28
29- clocks : From common clock binding
30
31- clock-output-names : From common clock binding.
32
33Example:
34
35 clockgenA@fee62000 {
36 reg = <0xfee62000 0xb48>;
37
38 CLK_S_A0_PLL: CLK_S_A0_PLL {
39 #clock-cells = <1>;
40 compatible = "st,clkgena-plls-c65";
41
42 clocks = <&CLK_SYSIN>;
43
44 clock-output-names = "CLK_S_A0_PLL0_HS",
45 "CLK_S_A0_PLL0_LS",
46 "CLK_S_A0_PLL1";
47 };
48 };
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
new file mode 100644
index 000000000000..566c9d79ed32
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
@@ -0,0 +1,36 @@
1Binding for a ST pre-divider clock driver.
2
3This binding uses the common clock binding[1].
4Base address is located to the parent node. See clock binding[2]
5
6[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
8
9Required properties:
10
11- compatible : shall be:
12 "st,clkgena-prediv-c65", "st,clkgena-prediv"
13 "st,clkgena-prediv-c32", "st,clkgena-prediv"
14
15- #clock-cells : From common clock binding; shall be set to 0.
16
17- clocks : From common clock binding
18
19- clock-output-names : From common clock binding.
20
21Example:
22
23 clockgenA@fd345000 {
24 reg = <0xfd345000 0xb50>;
25
26 CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
27 #clock-cells = <0>;
28 compatible = "st,clkgena-prediv-c32",
29 "st,clkgena-prediv";
30
31 clocks = <&CLK_SYSIN>;
32
33 clock-output-names = "CLK_M_A2_OSC_PREDIV";
34 };
35 };
36
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
new file mode 100644
index 000000000000..4e3ff28b04c3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
@@ -0,0 +1,53 @@
1Binding for a type of STMicroelectronics clock crossbar (VCC).
2
3The crossbar can take up to 4 input clocks and control up to 16
4output clocks. Not all inputs or outputs have to be in use in a
5particular instantiation. Each output can be individually enabled,
6select any of the input clocks and apply a divide (by 1,2,4 or 8) to
7that selected clock.
8
9This binding uses the common clock binding[1].
10
11[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12
13Required properties:
14
15- compatible : shall be:
16 "st,stih416-clkgenc", "st,vcc"
17 "st,stih416-clkgenf", "st,vcc"
18
19- #clock-cells : from common clock binding; shall be set to 1.
20
21- reg : A Base address and length of the register set.
22
23- clocks : from common clock binding
24
25- clock-output-names : From common clock binding. The block has 16
26 clock outputs but not all of them in a specific instance
27 have to be used in the SoC. If a clock name is left as
28 an empty string then no clock will be created for the
29 output associated with that string index. If fewer than
30 16 strings are provided then no clocks will be created
31 for the remaining outputs.
32
33Example:
34
35 CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {
36 #clock-cells = <1>;
37 compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
38 reg = <0xfe8308ac 12>;
39
40 clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,
41 <&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;
42
43 clock-output-names =
44 "CLK_S_PIX_HDMI", "CLK_S_PIX_DVO",
45 "CLK_S_OUT_DVO", "CLK_S_PIX_HD",
46 "CLK_S_HDDAC", "CLK_S_DENC",
47 "CLK_S_SDDAC", "CLK_S_PIX_MAIN",
48 "CLK_S_PIX_AUX", "CLK_S_STFE_FRC_0",
49 "CLK_S_REF_MCRU", "CLK_S_SLAVE_MCRU",
50 "CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",
51 "CLK_S_THSENS";
52 };
53
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
new file mode 100644
index 000000000000..49ec5ae18b5b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
@@ -0,0 +1,83 @@
1Binding for a Clockgen hardware block found on
2certain STMicroelectronics consumer electronics SoC devices.
3
4A Clockgen node can contain pll, diviser or multiplexer nodes.
5
6We will find only the base address of the Clockgen, this base
7address is common of all subnode.
8
9 clockgen_node {
10 reg = <>;
11
12 pll_node {
13 ...
14 };
15
16 prediv_node {
17 ...
18 };
19
20 divmux_node {
21 ...
22 };
23
24 quadfs_node {
25 ...
26 };
27 ...
28 };
29
30This binding uses the common clock binding[1].
31Each subnode should use the binding discribe in [2]..[4]
32
33[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
34[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
35[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
36[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
37
38Required properties:
39- reg : A Base address and length of the register set.
40
41Example:
42
43 clockgenA@fee62000 {
44
45 reg = <0xfee62000 0xb48>;
46
47 CLK_S_A0_PLL: CLK_S_A0_PLL {
48 #clock-cells = <1>;
49 compatible = "st,clkgena-plls-c65";
50
51 clocks = <&CLK_SYSIN>;
52
53 clock-output-names = "CLK_S_A0_PLL0_HS",
54 "CLK_S_A0_PLL0_LS",
55 "CLK_S_A0_PLL1";
56 };
57
58 CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
59 #clock-cells = <0>;
60 compatible = "st,clkgena-prediv-c65",
61 "st,clkgena-prediv";
62
63 clocks = <&CLK_SYSIN>;
64
65 clock-output-names = "CLK_S_A0_OSC_PREDIV";
66 };
67
68 CLK_S_A0_HS: CLK_S_A0_HS {
69 #clock-cells = <1>;
70 compatible = "st,clkgena-divmux-c65-hs",
71 "st,clkgena-divmux";
72
73 clocks = <&CLK_S_A0_OSC_PREDIV>,
74 <&CLK_S_A0_PLL 0>, /* PLL0 HS */
75 <&CLK_S_A0_PLL 2>; /* PLL1 */
76
77 clock-output-names = "CLK_S_FDMA_0",
78 "CLK_S_FDMA_1",
79 ""; /* CLK_S_JIT_SENSE */
80 /* Fourth output unused */
81 };
82 };
83
diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
new file mode 100644
index 000000000000..ec86d62ca283
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
@@ -0,0 +1,45 @@
1Binding for a type of quad channel digital frequency synthesizer found on
2certain STMicroelectronics consumer electronics SoC devices.
3
4This version contains a programmable PLL which can generate up to 216, 432
5or 660MHz (from a 30MHz oscillator input) as the input to the digital
6synthesizers.
7
8This binding uses the common clock binding[1].
9
10[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
11
12Required properties:
13- compatible : shall be:
14 "st,stih416-quadfs216", "st,quadfs"
15 "st,stih416-quadfs432", "st,quadfs"
16 "st,stih416-quadfs660-E", "st,quadfs"
17 "st,stih416-quadfs660-F", "st,quadfs"
18
19- #clock-cells : from common clock binding; shall be set to 1.
20
21- reg : A Base address and length of the register set.
22
23- clocks : from common clock binding
24
25- clock-output-names : From common clock binding. The block has 4
26 clock outputs but not all of them in a specific instance
27 have to be used in the SoC. If a clock name is left as
28 an empty string then no clock will be created for the
29 output associated with that string index. If fewer than
30 4 strings are provided then no clocks will be created
31 for the remaining outputs.
32
33Example:
34
35 CLOCKGEN_E: CLOCKGEN_E {
36 #clock-cells = <1>;
37 compatible = "st,stih416-quadfs660-E", "st,quadfs";
38 reg = <0xfd3208bc 0xB0>;
39
40 clocks = <&CLK_SYSIN>;
41 clock-output-names = "CLK_M_PIX_MDTP_0",
42 "CLK_M_PIX_MDTP_1",
43 "CLK_M_PIX_MDTP_2",
44 "CLK_M_MPELPC";
45 };
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index c2cb7621ad2d..a5160d8cbb5f 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -6,37 +6,41 @@ This binding uses the common clock binding[1].
6 6
7Required properties: 7Required properties:
8- compatible : shall be one of the following: 8- compatible : shall be one of the following:
9 "allwinner,sun4i-osc-clk" - for a gatable oscillator 9 "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
10 "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4 10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun4i-pll5-clk" - for the PLL5 clock 12 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
13 "allwinner,sun4i-pll6-clk" - for the PLL6 clock 13 "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
14 "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock 14 "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
15 "allwinner,sun4i-axi-clk" - for the AXI clock 15 "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
16 "allwinner,sun4i-axi-gates-clk" - for the AXI gates 16 "allwinner,sun4i-a10-axi-clk" - for the AXI clock
17 "allwinner,sun4i-ahb-clk" - for the AHB clock 17 "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
18 "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10 18 "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
19 "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
19 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 20 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
20 "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s 21 "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
21 "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 22 "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
22 "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31 23 "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
23 "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 24 "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
24 "allwinner,sun4i-apb0-clk" - for the APB0 clock 25 "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
25 "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10 26 "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
26 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 27 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
27 "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s 28 "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
28 "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 29 "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
29 "allwinner,sun4i-apb1-clk" - for the APB1 clock 30 "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
30 "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing 31 "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
31 "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10 32 "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
32 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 33 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
33 "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s 34 "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
34 "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31 35 "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
35 "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20 36 "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
36 "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31 37 "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
37 "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 38 "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
38 "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks 39 "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
39 "allwinner,sun7i-a20-out-clk" - for the external output clocks 40 "allwinner,sun7i-a20-out-clk" - for the external output clocks
41 "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
42 "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
43 "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
40 44
41Required properties for all clocks: 45Required properties for all clocks:
42- reg : shall be the control register address for the clock. 46- reg : shall be the control register address for the clock.
@@ -44,10 +48,17 @@ Required properties for all clocks:
44 multiplexed clocks, the list order must match the hardware 48 multiplexed clocks, the list order must match the hardware
45 programming order. 49 programming order.
46- #clock-cells : from common clock binding; shall be set to 0 except for 50- #clock-cells : from common clock binding; shall be set to 0 except for
47 "allwinner,*-gates-clk" where it shall be set to 1 51 "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
52 "allwinner,sun4i-pll6-clk" where it shall be set to 1
53- clock-output-names : shall be the corresponding names of the outputs.
54 If the clock module only has one output, the name shall be the
55 module name.
48 56
49Additionally, "allwinner,*-gates-clk" clocks require: 57And "allwinner,*-usb-clk" clocks also require:
50- clock-output-names : the corresponding gate names that the clock controls 58- reset-cells : shall be set to 1
59
60For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
61dummy clocks at 25 MHz and 125 MHz, respectively. See example.
51 62
52Clock consumers should specify the desired clocks they use with a 63Clock consumers should specify the desired clocks they use with a
53"clocks" phandle cell. Consumers that are using a gated clock should 64"clocks" phandle cell. Consumers that are using a gated clock should
@@ -56,23 +67,68 @@ offset of the bit controlling this particular gate in the register.
56 67
57For example: 68For example:
58 69
59osc24M: osc24M@01c20050 { 70osc24M: clk@01c20050 {
60 #clock-cells = <0>; 71 #clock-cells = <0>;
61 compatible = "allwinner,sun4i-osc-clk"; 72 compatible = "allwinner,sun4i-a10-osc-clk";
62 reg = <0x01c20050 0x4>; 73 reg = <0x01c20050 0x4>;
63 clocks = <&osc24M_fixed>; 74 clocks = <&osc24M_fixed>;
75 clock-output-names = "osc24M";
64}; 76};
65 77
66pll1: pll1@01c20000 { 78pll1: clk@01c20000 {
67 #clock-cells = <0>; 79 #clock-cells = <0>;
68 compatible = "allwinner,sun4i-pll1-clk"; 80 compatible = "allwinner,sun4i-a10-pll1-clk";
69 reg = <0x01c20000 0x4>; 81 reg = <0x01c20000 0x4>;
70 clocks = <&osc24M>; 82 clocks = <&osc24M>;
83 clock-output-names = "pll1";
84};
85
86pll5: clk@01c20020 {
87 #clock-cells = <1>;
88 compatible = "allwinner,sun4i-pll5-clk";
89 reg = <0x01c20020 0x4>;
90 clocks = <&osc24M>;
91 clock-output-names = "pll5_ddr", "pll5_other";
71}; 92};
72 93
73cpu: cpu@01c20054 { 94cpu: cpu@01c20054 {
74 #clock-cells = <0>; 95 #clock-cells = <0>;
75 compatible = "allwinner,sun4i-cpu-clk"; 96 compatible = "allwinner,sun4i-a10-cpu-clk";
76 reg = <0x01c20054 0x4>; 97 reg = <0x01c20054 0x4>;
77 clocks = <&osc32k>, <&osc24M>, <&pll1>; 98 clocks = <&osc32k>, <&osc24M>, <&pll1>;
99 clock-output-names = "cpu";
100};
101
102mmc0_clk: clk@01c20088 {
103 #clock-cells = <0>;
104 compatible = "allwinner,sun4i-mod0-clk";
105 reg = <0x01c20088 0x4>;
106 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
107 clock-output-names = "mmc0";
108};
109
110mii_phy_tx_clk: clk@2 {
111 #clock-cells = <0>;
112 compatible = "fixed-clock";
113 clock-frequency = <25000000>;
114 clock-output-names = "mii_phy_tx";
115};
116
117gmac_int_tx_clk: clk@3 {
118 #clock-cells = <0>;
119 compatible = "fixed-clock";
120 clock-frequency = <125000000>;
121 clock-output-names = "gmac_int_tx";
122};
123
124gmac_clk: clk@01c20164 {
125 #clock-cells = <0>;
126 compatible = "allwinner,sun7i-a20-gmac-clk";
127 reg = <0x01c20164 0x4>;
128 /*
129 * The first clock must be fixed at 25MHz;
130 * the second clock must be fixed at 125MHz
131 */
132 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
133 clock-output-names = "gmac";
78}; 134};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-17 08:14:41 -0500