1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index 0045433eae1f..5dfd145d3ccf 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -23,3 +23,8 @@ Optional properties:
        and the bit index.
 - div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
        and width.
+- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
+        the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
+        value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
+        hold/delay times that is needed for the SD/MMC CIU clock. The values of both
+        can be 0-315 degrees, in 45 degree increments.

diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt index 0045433eae1f..5dfd145d3ccf 100644 --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -23,3 +23,8 @@ Optional properties:
23	and the bit index.	23	and the bit index.
24	- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,	24	- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
25	and width.	25	and width.
		26	- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
		27	the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
		28	value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
		29	hold/delay times that is needed for the SD/MMC CIU clock. The values of both
		30	can be 0-315 degrees, in 45 degree increments.