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-rw-r--r--arch/arm/boot/dts/Makefile6
-rw-r--r--arch/arm/boot/dts/sun4i-a10-a1000.dts101
-rw-r--r--arch/arm/boot/dts/sun4i-a10-cubieboard.dts6
-rw-r--r--arch/arm/boot/dts/sun4i-a10-hackberry.dts2
-rw-r--r--arch/arm/boot/dts/sun4i-a10-mini-xplus.dts2
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi3
-rw-r--r--arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts27
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi93
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino.dts2
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi3
-rw-r--r--arch/arm/boot/dts/sun6i-a31-colombus.dts32
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi299
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubieboard2.dts53
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts61
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi311
15 files changed, 965 insertions, 36 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 68701d937741..05f6c2a29019 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -207,11 +207,15 @@ dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
207 stih415-b2020.dtb \ 207 stih415-b2020.dtb \
208 stih416-b2020.dtb 208 stih416-b2020.dtb
209dtb-$(CONFIG_ARCH_SUNXI) += \ 209dtb-$(CONFIG_ARCH_SUNXI) += \
210 sun4i-a10-a1000.dtb \
210 sun4i-a10-cubieboard.dtb \ 211 sun4i-a10-cubieboard.dtb \
211 sun4i-a10-mini-xplus.dtb \ 212 sun4i-a10-mini-xplus.dtb \
212 sun4i-a10-hackberry.dtb \ 213 sun4i-a10-hackberry.dtb \
213 sun5i-a10s-olinuxino-micro.dtb \ 214 sun5i-a10s-olinuxino-micro.dtb \
214 sun5i-a13-olinuxino.dtb 215 sun5i-a13-olinuxino.dtb \
216 sun6i-a31-colombus.dtb \
217 sun7i-a20-cubieboard2.dtb \
218 sun7i-a20-olinuxino-micro.dtb
215dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ 219dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
216 tegra20-iris-512.dtb \ 220 tegra20-iris-512.dtb \
217 tegra20-medcom-wide.dtb \ 221 tegra20-medcom-wide.dtb \
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
new file mode 100644
index 000000000000..eb4d73b6a090
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -0,0 +1,101 @@
1/*
2 * Copyright 2013 Emilio López
3 *
4 * Emilio López <emilio@elopez.com.ar>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun4i-a10.dtsi"
16
17/ {
18 model = "Mele A1000";
19 compatible = "mele,a1000", "allwinner,sun4i-a10";
20
21 aliases {
22 serial0 = &uart0;
23 };
24
25 soc@01c00000 {
26 emac: ethernet@01c0b000 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&emac_pins_a>;
29 phy = <&phy1>;
30 status = "okay";
31 };
32
33 mdio@01c0b080 {
34 phy-supply = <&reg_emac_3v3>;
35 status = "okay";
36
37 phy1: ethernet-phy@1 {
38 reg = <1>;
39 };
40 };
41
42 pinctrl@01c20800 {
43 emac_power_pin_a1000: emac_power_pin@0 {
44 allwinner,pins = "PH15";
45 allwinner,function = "gpio_out";
46 allwinner,drive = <0>;
47 allwinner,pull = <0>;
48 };
49
50 led_pins_a1000: led_pins@0 {
51 allwinner,pins = "PH10", "PH20";
52 allwinner,function = "gpio_out";
53 allwinner,drive = <0>;
54 allwinner,pull = <0>;
55 };
56 };
57
58 uart0: serial@01c28000 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&uart0_pins_a>;
61 status = "okay";
62 };
63
64 i2c0: i2c@01c2ac00 {
65 pinctrl-names = "default";
66 pinctrl-0 = <&i2c0_pins_a>;
67 status = "okay";
68 };
69 };
70
71 leds {
72 compatible = "gpio-leds";
73 pinctrl-names = "default";
74 pinctrl-0 = <&led_pins_a1000>;
75
76 red {
77 label = "a1000:red:usr";
78 gpios = <&pio 7 10 0>;
79 };
80
81 blue {
82 label = "a1000:blue:usr";
83 gpios = <&pio 7 20 0>;
84 };
85 };
86
87 regulators {
88 compatible = "simple-bus";
89
90 reg_emac_3v3: emac-3v3 {
91 compatible = "regulator-fixed";
92 pinctrl-names = "default";
93 pinctrl-0 = <&emac_power_pin_a1000>;
94 regulator-name = "emac-3v3";
95 regulator-min-microvolt = <3300000>;
96 regulator-max-microvolt = <3300000>;
97 enable-active-high;
98 gpio = <&pio 7 15 0>;
99 };
100 };
101};
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 757c4cd900ee..425a7db898c5 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -26,7 +26,7 @@
26 bootargs = "earlyprintk console=ttyS0,115200"; 26 bootargs = "earlyprintk console=ttyS0,115200";
27 }; 27 };
28 28
29 soc@01c20000 { 29 soc@01c00000 {
30 emac: ethernet@01c0b000 { 30 emac: ethernet@01c0b000 {
31 pinctrl-names = "default"; 31 pinctrl-names = "default";
32 pinctrl-0 = <&emac_pins_a>; 32 pinctrl-0 = <&emac_pins_a>;
@@ -76,12 +76,12 @@
76 pinctrl-0 = <&led_pins_cubieboard>; 76 pinctrl-0 = <&led_pins_cubieboard>;
77 77
78 blue { 78 blue {
79 label = "cubieboard::blue"; 79 label = "cubieboard:blue:usr";
80 gpios = <&pio 7 21 0>; /* LED1 */ 80 gpios = <&pio 7 21 0>; /* LED1 */
81 }; 81 };
82 82
83 green { 83 green {
84 label = "cubieboard::green"; 84 label = "cubieboard:green:usr";
85 gpios = <&pio 7 20 0>; /* LED2 */ 85 gpios = <&pio 7 20 0>; /* LED2 */
86 linux,default-trigger = "heartbeat"; 86 linux,default-trigger = "heartbeat";
87 }; 87 };
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index 3514b37d66bc..b3ae51fa9372 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -22,7 +22,7 @@
22 bootargs = "earlyprintk console=ttyS0,115200"; 22 bootargs = "earlyprintk console=ttyS0,115200";
23 }; 23 };
24 24
25 soc@01c20000 { 25 soc@01c00000 {
26 emac: ethernet@01c0b000 { 26 emac: ethernet@01c0b000 {
27 pinctrl-names = "default"; 27 pinctrl-names = "default";
28 pinctrl-0 = <&emac_pins_a>; 28 pinctrl-0 = <&emac_pins_a>;
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index 078ed7f618d7..0c1447c68059 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -22,7 +22,7 @@
22 bootargs = "earlyprintk console=ttyS0,115200"; 22 bootargs = "earlyprintk console=ttyS0,115200";
23 }; 23 };
24 24
25 soc@01c20000 { 25 soc@01c00000 {
26 uart0: serial@01c28000 { 26 uart0: serial@01c28000 {
27 pinctrl-names = "default"; 27 pinctrl-names = "default";
28 pinctrl-0 = <&uart0_pins_a>; 28 pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index b2bd6e124250..c32770a28acf 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -160,11 +160,10 @@
160 }; 160 };
161 }; 161 };
162 162
163 soc@01c20000 { 163 soc@01c00000 {
164 compatible = "simple-bus"; 164 compatible = "simple-bus";
165 #address-cells = <1>; 165 #address-cells = <1>;
166 #size-cells = <1>; 166 #size-cells = <1>;
167 reg = <0x01c20000 0x300000>;
168 ranges; 167 ranges;
169 168
170 emac: ethernet@01c0b000 { 169 emac: ethernet@01c0b000 {
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 64dc0c42c43a..3c9f8b3cd3e3 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -18,7 +18,7 @@
18 model = "Olimex A10s-Olinuxino Micro"; 18 model = "Olimex A10s-Olinuxino Micro";
19 compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s"; 19 compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s";
20 20
21 soc@01c20000 { 21 soc@01c00000 {
22 emac: ethernet@01c0b000 { 22 emac: ethernet@01c0b000 {
23 pinctrl-names = "default"; 23 pinctrl-names = "default";
24 pinctrl-0 = <&emac_pins_a>; 24 pinctrl-0 = <&emac_pins_a>;
@@ -60,6 +60,31 @@
60 pinctrl-0 = <&uart3_pins_a>; 60 pinctrl-0 = <&uart3_pins_a>;
61 status = "okay"; 61 status = "okay";
62 }; 62 };
63
64 i2c0: i2c@01c2ac00 {
65 pinctrl-names = "default";
66 pinctrl-0 = <&i2c0_pins_a>;
67 status = "okay";
68 };
69
70 i2c1: i2c@01c2b000 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&i2c1_pins_a>;
73 status = "okay";
74
75 at24@50 {
76 compatible = "at,24c16";
77 pagesize = <16>;
78 reg = <0x50>;
79 read-only;
80 };
81 };
82
83 i2c2: i2c@01c2b400 {
84 pinctrl-names = "default";
85 pinctrl-0 = <&i2c2_pins_a>;
86 status = "okay";
87 };
63 }; 88 };
64 89
65 leds { 90 leds {
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 2307ce827ae0..3b4a0574f068 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -95,20 +95,16 @@
95 95
96 ahb_gates: ahb_gates@01c20060 { 96 ahb_gates: ahb_gates@01c20060 {
97 #clock-cells = <1>; 97 #clock-cells = <1>;
98 compatible = "allwinner,sun4i-ahb-gates-clk"; 98 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
99 reg = <0x01c20060 0x8>; 99 reg = <0x01c20060 0x8>;
100 clocks = <&ahb>; 100 clocks = <&ahb>;
101 clock-output-names = "ahb_usb0", "ahb_ehci0", 101 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
102 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", 102 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
103 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", 103 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
104 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", 104 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
105 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", 105 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
106 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", 106 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
107 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", 107 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
108 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
109 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
110 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
111 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
112 }; 108 };
113 109
114 apb0: apb0@01c20054 { 110 apb0: apb0@01c20054 {
@@ -120,12 +116,11 @@
120 116
121 apb0_gates: apb0_gates@01c20068 { 117 apb0_gates: apb0_gates@01c20068 {
122 #clock-cells = <1>; 118 #clock-cells = <1>;
123 compatible = "allwinner,sun4i-apb0-gates-clk"; 119 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
124 reg = <0x01c20068 0x4>; 120 reg = <0x01c20068 0x4>;
125 clocks = <&apb0>; 121 clocks = <&apb0>;
126 clock-output-names = "apb0_codec", "apb0_spdif", 122 clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
127 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", 123 "apb0_ir", "apb0_keypad";
128 "apb0_ir1", "apb0_keypad";
129 }; 124 };
130 125
131 /* dummy is pll62 */ 126 /* dummy is pll62 */
@@ -145,23 +140,19 @@
145 140
146 apb1_gates: apb1_gates@01c2006c { 141 apb1_gates: apb1_gates@01c2006c {
147 #clock-cells = <1>; 142 #clock-cells = <1>;
148 compatible = "allwinner,sun4i-apb1-gates-clk"; 143 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
149 reg = <0x01c2006c 0x4>; 144 reg = <0x01c2006c 0x4>;
150 clocks = <&apb1>; 145 clocks = <&apb1>;
151 clock-output-names = "apb1_i2c0", "apb1_i2c1", 146 clock-output-names = "apb1_i2c0", "apb1_i2c1",
152 "apb1_i2c2", "apb1_can", "apb1_scr", 147 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
153 "apb1_ps20", "apb1_ps21", "apb1_uart0", 148 "apb1_uart2", "apb1_uart3";
154 "apb1_uart1", "apb1_uart2", "apb1_uart3",
155 "apb1_uart4", "apb1_uart5", "apb1_uart6",
156 "apb1_uart7";
157 }; 149 };
158 }; 150 };
159 151
160 soc@01c20000 { 152 soc@01c00000 {
161 compatible = "simple-bus"; 153 compatible = "simple-bus";
162 #address-cells = <1>; 154 #address-cells = <1>;
163 #size-cells = <1>; 155 #size-cells = <1>;
164 reg = <0x01c20000 0x300000>;
165 ranges; 156 ranges;
166 157
167 emac: ethernet@01c0b000 { 158 emac: ethernet@01c0b000 {
@@ -229,6 +220,27 @@
229 allwinner,drive = <0>; 220 allwinner,drive = <0>;
230 allwinner,pull = <0>; 221 allwinner,pull = <0>;
231 }; 222 };
223
224 i2c0_pins_a: i2c0@0 {
225 allwinner,pins = "PB0", "PB1";
226 allwinner,function = "i2c0";
227 allwinner,drive = <0>;
228 allwinner,pull = <0>;
229 };
230
231 i2c1_pins_a: i2c1@0 {
232 allwinner,pins = "PB15", "PB16";
233 allwinner,function = "i2c1";
234 allwinner,drive = <0>;
235 allwinner,pull = <0>;
236 };
237
238 i2c2_pins_a: i2c2@0 {
239 allwinner,pins = "PB17", "PB18";
240 allwinner,function = "i2c2";
241 allwinner,drive = <0>;
242 allwinner,pull = <0>;
243 };
232 }; 244 };
233 245
234 timer@01c20c00 { 246 timer@01c20c00 {
@@ -282,5 +294,38 @@
282 clocks = <&apb1_gates 19>; 294 clocks = <&apb1_gates 19>;
283 status = "disabled"; 295 status = "disabled";
284 }; 296 };
297
298 i2c0: i2c@01c2ac00 {
299 #address-cells = <1>;
300 #size-cells = <0>;
301 compatible = "allwinner,sun4i-i2c";
302 reg = <0x01c2ac00 0x400>;
303 interrupts = <7>;
304 clocks = <&apb1_gates 0>;
305 clock-frequency = <100000>;
306 status = "disabled";
307 };
308
309 i2c1: i2c@01c2b000 {
310 #address-cells = <1>;
311 #size-cells = <0>;
312 compatible = "allwinner,sun4i-i2c";
313 reg = <0x01c2b000 0x400>;
314 interrupts = <8>;
315 clocks = <&apb1_gates 1>;
316 clock-frequency = <100000>;
317 status = "disabled";
318 };
319
320 i2c2: i2c@01c2b400 {
321 #address-cells = <1>;
322 #size-cells = <0>;
323 compatible = "allwinner,sun4i-i2c";
324 reg = <0x01c2b400 0x400>;
325 interrupts = <9>;
326 clocks = <&apb1_gates 2>;
327 clock-frequency = <100000>;
328 status = "disabled";
329 };
285 }; 330 };
286}; 331};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 80497e376706..9e508dcc4245 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -22,7 +22,7 @@
22 bootargs = "earlyprintk console=ttyS0,115200"; 22 bootargs = "earlyprintk console=ttyS0,115200";
23 }; 23 };
24 24
25 soc@01c20000 { 25 soc@01c00000 {
26 pinctrl@01c20800 { 26 pinctrl@01c20800 {
27 led_pins_olinuxino: led_pins@0 { 27 led_pins_olinuxino: led_pins@0 {
28 allwinner,pins = "PG9"; 28 allwinner,pins = "PG9";
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 7363211daf84..f6091dc0936c 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -150,11 +150,10 @@
150 }; 150 };
151 }; 151 };
152 152
153 soc@01c20000 { 153 soc@01c00000 {
154 compatible = "simple-bus"; 154 compatible = "simple-bus";
155 #address-cells = <1>; 155 #address-cells = <1>;
156 #size-cells = <1>; 156 #size-cells = <1>;
157 reg = <0x01c20000 0x300000>;
158 ranges; 157 ranges;
159 158
160 intc: interrupt-controller@01c20400 { 159 intc: interrupt-controller@01c20400 {
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
new file mode 100644
index 000000000000..e5adae30899b
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -0,0 +1,32 @@
1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun6i-a31.dtsi"
16
17/ {
18 model = "WITS A31 Colombus Evaluation Board";
19 compatible = "wits,colombus", "allwinner,sun6i-a31";
20
21 chosen {
22 bootargs = "earlyprintk console=ttyS0,115200";
23 };
24
25 soc@01c00000 {
26 uart0: serial@01c28000 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&uart0_pins_a>;
29 status = "okay";
30 };
31 };
32};
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
new file mode 100644
index 000000000000..f244f5f02365
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -0,0 +1,299 @@
1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&gic>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu@0 {
24 compatible = "arm,cortex-a7";
25 device_type = "cpu";
26 reg = <0>;
27 };
28
29 cpu@1 {
30 compatible = "arm,cortex-a7";
31 device_type = "cpu";
32 reg = <1>;
33 };
34
35 cpu@2 {
36 compatible = "arm,cortex-a7";
37 device_type = "cpu";
38 reg = <2>;
39 };
40
41 cpu@3 {
42 compatible = "arm,cortex-a7";
43 device_type = "cpu";
44 reg = <3>;
45 };
46 };
47
48 memory {
49 reg = <0x40000000 0x80000000>;
50 };
51
52 clocks {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 osc24M: osc24M {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <24000000>;
61 };
62
63 osc32k: osc32k {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
67 };
68
69 pll1: pll1@01c20000 {
70 #clock-cells = <0>;
71 compatible = "allwinner,sun6i-a31-pll1-clk";
72 reg = <0x01c20000 0x4>;
73 clocks = <&osc24M>;
74 };
75
76 /*
77 * This is a dummy clock, to be used as placeholder on
78 * other mux clocks when a specific parent clock is not
79 * yet implemented. It should be dropped when the driver
80 * is complete.
81 */
82 pll6: pll6 {
83 #clock-cells = <0>;
84 compatible = "fixed-clock";
85 clock-frequency = <0>;
86 };
87
88 cpu: cpu@01c20050 {
89 #clock-cells = <0>;
90 compatible = "allwinner,sun4i-cpu-clk";
91 reg = <0x01c20050 0x4>;
92
93 /*
94 * PLL1 is listed twice here.
95 * While it looks suspicious, it's actually documented
96 * that way both in the datasheet and in the code from
97 * Allwinner.
98 */
99 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
100 };
101
102 axi: axi@01c20050 {
103 #clock-cells = <0>;
104 compatible = "allwinner,sun4i-axi-clk";
105 reg = <0x01c20050 0x4>;
106 clocks = <&cpu>;
107 };
108
109 ahb1_mux: ahb1_mux@01c20054 {
110 #clock-cells = <0>;
111 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
112 reg = <0x01c20054 0x4>;
113 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
114 };
115
116 ahb1: ahb1@01c20054 {
117 #clock-cells = <0>;
118 compatible = "allwinner,sun4i-ahb-clk";
119 reg = <0x01c20054 0x4>;
120 clocks = <&ahb1_mux>;
121 };
122
123 ahb1_gates: ahb1_gates@01c20060 {
124 #clock-cells = <1>;
125 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
126 reg = <0x01c20060 0x8>;
127 clocks = <&ahb1>;
128 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
129 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
130 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
131 "ahb1_nand0", "ahb1_sdram",
132 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
133 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
134 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
135 "ahb1_ehci1", "ahb1_ohci0",
136 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
137 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
138 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
139 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
140 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
141 "ahb1_drc0", "ahb1_drc1";
142 };
143
144 apb1: apb1@01c20054 {
145 #clock-cells = <0>;
146 compatible = "allwinner,sun4i-apb0-clk";
147 reg = <0x01c20054 0x4>;
148 clocks = <&ahb1>;
149 };
150
151 apb1_gates: apb1_gates@01c20060 {
152 #clock-cells = <1>;
153 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
154 reg = <0x01c20068 0x4>;
155 clocks = <&apb1>;
156 clock-output-names = "apb1_codec", "apb1_digital_mic",
157 "apb1_pio", "apb1_daudio0",
158 "apb1_daudio1";
159 };
160
161 apb2_mux: apb2_mux@01c20058 {
162 #clock-cells = <0>;
163 compatible = "allwinner,sun4i-apb1-mux-clk";
164 reg = <0x01c20058 0x4>;
165 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
166 };
167
168 apb2: apb2@01c20058 {
169 #clock-cells = <0>;
170 compatible = "allwinner,sun6i-a31-apb2-div-clk";
171 reg = <0x01c20058 0x4>;
172 clocks = <&apb2_mux>;
173 };
174
175 apb2_gates: apb2_gates@01c2006c {
176 #clock-cells = <1>;
177 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
178 reg = <0x01c2006c 0x8>;
179 clocks = <&apb2>;
180 clock-output-names = "apb2_i2c0", "apb2_i2c1",
181 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
182 "apb2_uart1", "apb2_uart2", "apb2_uart3",
183 "apb2_uart4", "apb2_uart5";
184 };
185 };
186
187 soc@01c00000 {
188 compatible = "simple-bus";
189 #address-cells = <1>;
190 #size-cells = <1>;
191 ranges;
192
193 pio: pinctrl@01c20800 {
194 compatible = "allwinner,sun6i-a31-pinctrl";
195 reg = <0x01c20800 0x400>;
196 interrupts = <0 11 1>, <0 15 1>, <0 16 1>, <0 17 1>;
197 clocks = <&apb1_gates 5>;
198 gpio-controller;
199 interrupt-controller;
200 #address-cells = <1>;
201 #size-cells = <0>;
202 #gpio-cells = <3>;
203
204 uart0_pins_a: uart0@0 {
205 allwinner,pins = "PH20", "PH21";
206 allwinner,function = "uart0";
207 allwinner,drive = <0>;
208 allwinner,pull = <0>;
209 };
210 };
211
212 timer@01c20c00 {
213 compatible = "allwinner,sun4i-timer";
214 reg = <0x01c20c00 0xa0>;
215 interrupts = <0 18 1>,
216 <0 19 1>,
217 <0 20 1>,
218 <0 21 1>,
219 <0 22 1>;
220 clocks = <&osc24M>;
221 };
222
223 wdt1: watchdog@01c20ca0 {
224 compatible = "allwinner,sun6i-wdt";
225 reg = <0x01c20ca0 0x20>;
226 };
227
228 uart0: serial@01c28000 {
229 compatible = "snps,dw-apb-uart";
230 reg = <0x01c28000 0x400>;
231 interrupts = <0 0 1>;
232 reg-shift = <2>;
233 reg-io-width = <4>;
234 clocks = <&apb2_gates 16>;
235 status = "disabled";
236 };
237
238 uart1: serial@01c28400 {
239 compatible = "snps,dw-apb-uart";
240 reg = <0x01c28400 0x400>;
241 interrupts = <0 1 1>;
242 reg-shift = <2>;
243 reg-io-width = <4>;
244 clocks = <&apb2_gates 17>;
245 status = "disabled";
246 };
247
248 uart2: serial@01c28800 {
249 compatible = "snps,dw-apb-uart";
250 reg = <0x01c28800 0x400>;
251 interrupts = <0 2 1>;
252 reg-shift = <2>;
253 reg-io-width = <4>;
254 clocks = <&apb2_gates 18>;
255 status = "disabled";
256 };
257
258 uart3: serial@01c28c00 {
259 compatible = "snps,dw-apb-uart";
260 reg = <0x01c28c00 0x400>;
261 interrupts = <0 3 1>;
262 reg-shift = <2>;
263 reg-io-width = <4>;
264 clocks = <&apb2_gates 19>;
265 status = "disabled";
266 };
267
268 uart4: serial@01c29000 {
269 compatible = "snps,dw-apb-uart";
270 reg = <0x01c29000 0x400>;
271 interrupts = <0 4 1>;
272 reg-shift = <2>;
273 reg-io-width = <4>;
274 clocks = <&apb2_gates 20>;
275 status = "disabled";
276 };
277
278 uart5: serial@01c29400 {
279 compatible = "snps,dw-apb-uart";
280 reg = <0x01c29400 0x400>;
281 interrupts = <0 5 1>;
282 reg-shift = <2>;
283 reg-io-width = <4>;
284 clocks = <&apb2_gates 21>;
285 status = "disabled";
286 };
287
288 gic: interrupt-controller@01c81000 {
289 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
290 reg = <0x01c81000 0x1000>,
291 <0x01c82000 0x1000>,
292 <0x01c84000 0x2000>,
293 <0x01c86000 0x2000>;
294 interrupt-controller;
295 #interrupt-cells = <3>;
296 interrupts = <1 9 0xf04>;
297 };
298 };
299};
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
new file mode 100644
index 000000000000..31b76f08b3ad
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -0,0 +1,53 @@
1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun7i-a20.dtsi"
16
17/ {
18 model = "Cubietech Cubieboard2";
19 compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
20
21 soc@01c00000 {
22 pinctrl@01c20800 {
23 led_pins_cubieboard2: led_pins@0 {
24 allwinner,pins = "PH20", "PH21";
25 allwinner,function = "gpio_out";
26 allwinner,drive = <0>;
27 allwinner,pull = <0>;
28 };
29 };
30
31 uart0: serial@01c28000 {
32 pinctrl-names = "default";
33 pinctrl-0 = <&uart0_pins_a>;
34 status = "okay";
35 };
36 };
37
38 leds {
39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&led_pins_cubieboard2>;
42
43 blue {
44 label = "cubieboard2:blue:usr";
45 gpios = <&pio 7 21 0>;
46 };
47
48 green {
49 label = "cubieboard2:green:usr";
50 gpios = <&pio 7 20 0>;
51 };
52 };
53};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
new file mode 100644
index 000000000000..34a6c02a7c72
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -0,0 +1,61 @@
1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun7i-a20.dtsi"
16
17/ {
18 model = "Olimex A20-Olinuxino Micro";
19 compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
20
21 soc@01c00000 {
22 pinctrl@01c20800 {
23 led_pins_olinuxino: led_pins@0 {
24 allwinner,pins = "PH2";
25 allwinner,function = "gpio_out";
26 allwinner,drive = <1>;
27 allwinner,pull = <0>;
28 };
29 };
30
31 uart0: serial@01c28000 {
32 pinctrl-names = "default";
33 pinctrl-0 = <&uart0_pins_a>;
34 status = "okay";
35 };
36
37 uart6: serial@01c29800 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&uart6_pins_a>;
40 status = "okay";
41 };
42
43 uart7: serial@01c29c00 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&uart7_pins_a>;
46 status = "okay";
47 };
48 };
49
50 leds {
51 compatible = "gpio-leds";
52 pinctrl-names = "default";
53 pinctrl-0 = <&led_pins_olinuxino>;
54
55 green {
56 label = "a20-olinuxino-micro:green:usr";
57 gpios = <&pio 7 2 0>;
58 default-state = "on";
59 };
60 };
61};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
new file mode 100644
index 000000000000..999ff45cb77e
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -0,0 +1,311 @@
1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&gic>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu@0 {
24 compatible = "arm,cortex-a7";
25 device_type = "cpu";
26 reg = <0>;
27 };
28
29 cpu@1 {
30 compatible = "arm,cortex-a7";
31 device_type = "cpu";
32 reg = <1>;
33 };
34 };
35
36 memory {
37 reg = <0x40000000 0x80000000>;
38 };
39
40 clocks {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 ranges;
44
45 osc24M: osc24M@01c20050 {
46 #clock-cells = <0>;
47 compatible = "allwinner,sun4i-osc-clk";
48 reg = <0x01c20050 0x4>;
49 clock-frequency = <24000000>;
50 };
51
52 osc32k: osc32k {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
55 clock-frequency = <32768>;
56 };
57
58 pll1: pll1@01c20000 {
59 #clock-cells = <0>;
60 compatible = "allwinner,sun4i-pll1-clk";
61 reg = <0x01c20000 0x4>;
62 clocks = <&osc24M>;
63 };
64
65 /*
66 * This is a dummy clock, to be used as placeholder on
67 * other mux clocks when a specific parent clock is not
68 * yet implemented. It should be dropped when the driver
69 * is complete.
70 */
71 pll6: pll6 {
72 #clock-cells = <0>;
73 compatible = "fixed-clock";
74 clock-frequency = <0>;
75 };
76
77 cpu: cpu@01c20054 {
78 #clock-cells = <0>;
79 compatible = "allwinner,sun4i-cpu-clk";
80 reg = <0x01c20054 0x4>;
81 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
82 };
83
84 axi: axi@01c20054 {
85 #clock-cells = <0>;
86 compatible = "allwinner,sun4i-axi-clk";
87 reg = <0x01c20054 0x4>;
88 clocks = <&cpu>;
89 };
90
91 ahb: ahb@01c20054 {
92 #clock-cells = <0>;
93 compatible = "allwinner,sun4i-ahb-clk";
94 reg = <0x01c20054 0x4>;
95 clocks = <&axi>;
96 };
97
98 ahb_gates: ahb_gates@01c20060 {
99 #clock-cells = <1>;
100 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
101 reg = <0x01c20060 0x8>;
102 clocks = <&ahb>;
103 clock-output-names = "ahb_usb0", "ahb_ehci0",
104 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
105 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
106 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
107 "ahb_nand", "ahb_sdram", "ahb_ace",
108 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
109 "ahb_spi2", "ahb_spi3", "ahb_sata",
110 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
111 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
112 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
113 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
114 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
115 "ahb_mali";
116 };
117
118 apb0: apb0@01c20054 {
119 #clock-cells = <0>;
120 compatible = "allwinner,sun4i-apb0-clk";
121 reg = <0x01c20054 0x4>;
122 clocks = <&ahb>;
123 };
124
125 apb0_gates: apb0_gates@01c20068 {
126 #clock-cells = <1>;
127 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
128 reg = <0x01c20068 0x4>;
129 clocks = <&apb0>;
130 clock-output-names = "apb0_codec", "apb0_spdif",
131 "apb0_ac97", "apb0_iis0", "apb0_iis1",
132 "apb0_pio", "apb0_ir0", "apb0_ir1",
133 "apb0_iis2", "apb0_keypad";
134 };
135
136 apb1_mux: apb1_mux@01c20058 {
137 #clock-cells = <0>;
138 compatible = "allwinner,sun4i-apb1-mux-clk";
139 reg = <0x01c20058 0x4>;
140 clocks = <&osc24M>, <&pll6>, <&osc32k>;
141 };
142
143 apb1: apb1@01c20058 {
144 #clock-cells = <0>;
145 compatible = "allwinner,sun4i-apb1-clk";
146 reg = <0x01c20058 0x4>;
147 clocks = <&apb1_mux>;
148 };
149
150 apb1_gates: apb1_gates@01c2006c {
151 #clock-cells = <1>;
152 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
153 reg = <0x01c2006c 0x4>;
154 clocks = <&apb1>;
155 clock-output-names = "apb1_i2c0", "apb1_i2c1",
156 "apb1_i2c2", "apb1_i2c3", "apb1_can",
157 "apb1_scr", "apb1_ps20", "apb1_ps21",
158 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
159 "apb1_uart2", "apb1_uart3", "apb1_uart4",
160 "apb1_uart5", "apb1_uart6", "apb1_uart7";
161 };
162 };
163
164 soc@01c00000 {
165 compatible = "simple-bus";
166 #address-cells = <1>;
167 #size-cells = <1>;
168 ranges;
169
170 pio: pinctrl@01c20800 {
171 compatible = "allwinner,sun7i-a20-pinctrl";
172 reg = <0x01c20800 0x400>;
173 interrupts = <0 28 1>;
174 clocks = <&apb0_gates 5>;
175 gpio-controller;
176 interrupt-controller;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 #gpio-cells = <3>;
180
181 uart0_pins_a: uart0@0 {
182 allwinner,pins = "PB22", "PB23";
183 allwinner,function = "uart0";
184 allwinner,drive = <0>;
185 allwinner,pull = <0>;
186 };
187
188 uart6_pins_a: uart6@0 {
189 allwinner,pins = "PI12", "PI13";
190 allwinner,function = "uart6";
191 allwinner,drive = <0>;
192 allwinner,pull = <0>;
193 };
194
195 uart7_pins_a: uart7@0 {
196 allwinner,pins = "PI20", "PI21";
197 allwinner,function = "uart7";
198 allwinner,drive = <0>;
199 allwinner,pull = <0>;
200 };
201 };
202
203 timer@01c20c00 {
204 compatible = "allwinner,sun4i-timer";
205 reg = <0x01c20c00 0x90>;
206 interrupts = <0 22 1>,
207 <0 23 1>,
208 <0 24 1>,
209 <0 25 1>,
210 <0 67 1>,
211 <0 68 1>;
212 clocks = <&osc24M>;
213 };
214
215 wdt: watchdog@01c20c90 {
216 compatible = "allwinner,sun4i-wdt";
217 reg = <0x01c20c90 0x10>;
218 };
219
220 uart0: serial@01c28000 {
221 compatible = "snps,dw-apb-uart";
222 reg = <0x01c28000 0x400>;
223 interrupts = <0 1 1>;
224 reg-shift = <2>;
225 reg-io-width = <4>;
226 clocks = <&apb1_gates 16>;
227 status = "disabled";
228 };
229
230 uart1: serial@01c28400 {
231 compatible = "snps,dw-apb-uart";
232 reg = <0x01c28400 0x400>;
233 interrupts = <0 2 1>;
234 reg-shift = <2>;
235 reg-io-width = <4>;
236 clocks = <&apb1_gates 17>;
237 status = "disabled";
238 };
239
240 uart2: serial@01c28800 {
241 compatible = "snps,dw-apb-uart";
242 reg = <0x01c28800 0x400>;
243 interrupts = <0 3 1>;
244 reg-shift = <2>;
245 reg-io-width = <4>;
246 clocks = <&apb1_gates 18>;
247 status = "disabled";
248 };
249
250 uart3: serial@01c28c00 {
251 compatible = "snps,dw-apb-uart";
252 reg = <0x01c28c00 0x400>;
253 interrupts = <0 4 1>;
254 reg-shift = <2>;
255 reg-io-width = <4>;
256 clocks = <&apb1_gates 19>;
257 status = "disabled";
258 };
259
260 uart4: serial@01c29000 {
261 compatible = "snps,dw-apb-uart";
262 reg = <0x01c29000 0x400>;
263 interrupts = <0 17 1>;
264 reg-shift = <2>;
265 reg-io-width = <4>;
266 clocks = <&apb1_gates 20>;
267 status = "disabled";
268 };
269
270 uart5: serial@01c29400 {
271 compatible = "snps,dw-apb-uart";
272 reg = <0x01c29400 0x400>;
273 interrupts = <0 18 1>;
274 reg-shift = <2>;
275 reg-io-width = <4>;
276 clocks = <&apb1_gates 21>;
277 status = "disabled";
278 };
279
280 uart6: serial@01c29800 {
281 compatible = "snps,dw-apb-uart";
282 reg = <0x01c29800 0x400>;
283 interrupts = <0 19 1>;
284 reg-shift = <2>;
285 reg-io-width = <4>;
286 clocks = <&apb1_gates 22>;
287 status = "disabled";
288 };
289
290 uart7: serial@01c29c00 {
291 compatible = "snps,dw-apb-uart";
292 reg = <0x01c29c00 0x400>;
293 interrupts = <0 20 1>;
294 reg-shift = <2>;
295 reg-io-width = <4>;
296 clocks = <&apb1_gates 23>;
297 status = "disabled";
298 };
299
300 gic: interrupt-controller@01c81000 {
301 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
302 reg = <0x01c81000 0x1000>,
303 <0x01c82000 0x1000>,
304 <0x01c84000 0x2000>,
305 <0x01c86000 0x2000>;
306 interrupt-controller;
307 #interrupt-cells = <3>;
308 interrupts = <1 9 0xf04>;
309 };
310 };
311};
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-10 12:27:56 -0400