Merge tag 'sunxi-dt-for-3.12-4' of https://github.com/mripard/linux into late/all

From Maxime Ripard:
Allwinner DT changes for 3.12, take 3 and 4

These patches add support for:
  - The cubieboard2 board
  - The pinctrl driver that got merged for the A20 and A31
  - The associated muxing for the A20 and A31 boards already supported
  - Enables the gated clocks on the A10s, A20 and A31 DTSI.

* tag 'sunxi-dt-for-3.12-4' of https://github.com/mripard/linux:
  ARM: sun7i: Enable the A20 clocks in the DTSI
  ARM: sun6i: Enable clock support in the DTSI
  ARM: sun5i: dt: Use the A10s gates in the DTSI
  ARM: sun7i: Add Cubieboard2 Device Tree
  ARM: sun7i: a20-olinuxino: Enable the user LED
  ARM: sun7i: a20-olinuxino: Enable UARTs muxing
  ARM: sun7i: DT: Add UART muxing options to the DTSI
  ARM: sun7i: Add the PIO controller node to the DTSI
  ARM: sun6i: colombus: Add uart0 muxing
  ARM: sun6i: Add UART0 muxing options
  ARM: sunxi: dt: Add PIO controller to A31 DTSI

Signed-off-by: Olof Johansson <olof@lixom.net>

15 files changed, 965 insertions, 36 deletions

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 68701d937741..05f6c2a29019 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -207,11 +207,15 @@ dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
         stih415-b2020.dtb \
         stih416-b2020.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += \
+        sun4i-a10-a1000.dtb \
         sun4i-a10-cubieboard.dtb \
         sun4i-a10-mini-xplus.dtb \
         sun4i-a10-hackberry.dtb \
         sun5i-a10s-olinuxino-micro.dtb \
-        sun5i-a13-olinuxino.dtb
+        sun5i-a13-olinuxino.dtb \
+        sun6i-a31-colombus.dtb \
+        sun7i-a20-cubieboard2.dtb \
+        sun7i-a20-olinuxino-micro.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
         tegra20-iris-512.dtb \
         tegra20-medcom-wide.dtb \
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
new file mode 100644
index 000000000000..eb4d73b6a090
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2013 Emilio López
+ *
+ * Emilio López <emilio@elopez.com.ar>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun4i-a10.dtsi"
+
+/ {
+        model = "Mele A1000";
+        compatible = "mele,a1000", "allwinner,sun4i-a10";
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        soc@01c00000 {
+                emac: ethernet@01c0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&emac_pins_a>;
+                        phy = <&phy1>;
+                        status = "okay";
+                };
+
+                mdio@01c0b080 {
+                        phy-supply = <&reg_emac_3v3>;
+                        status = "okay";
+
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+
+                pinctrl@01c20800 {
+                        emac_power_pin_a1000: emac_power_pin@0 {
+                                allwinner,pins = "PH15";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        led_pins_a1000: led_pins@0 {
+                                allwinner,pins = "PH10", "PH20";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_a1000>;
+
+                red {
+                        label = "a1000:red:usr";
+                        gpios = <&pio 7 10 0>;
+                };
+
+                blue {
+                        label = "a1000:blue:usr";
+                        gpios = <&pio 7 20 0>;
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_emac_3v3: emac-3v3 {
+                        compatible = "regulator-fixed";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&emac_power_pin_a1000>;
+                        regulator-name = "emac-3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&pio 7 15 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 757c4cd900ee..425a7db898c5 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -26,7 +26,7 @@
                 bootargs = "earlyprintk console=ttyS0,115200";
         };
 
-        soc@01c20000 {
+        soc@01c00000 {
                 emac: ethernet@01c0b000 {
                         pinctrl-names = "default";
                         pinctrl-0 = <&emac_pins_a>;
@@ -76,12 +76,12 @@
                 pinctrl-0 = <&led_pins_cubieboard>;
 
                 blue {
-                        label = "cubieboard::blue";
+                        label = "cubieboard:blue:usr";
                         gpios = <&pio 7 21 0>; /* LED1 */
                 };
 
                 green {
-                        label = "cubieboard::green";
+                        label = "cubieboard:green:usr";
                         gpios = <&pio 7 20 0>; /* LED2 */
                         linux,default-trigger = "heartbeat";
                 };
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index 3514b37d66bc..b3ae51fa9372 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -22,7 +22,7 @@
                 bootargs = "earlyprintk console=ttyS0,115200";
         };
 
-        soc@01c20000 {
+        soc@01c00000 {
                 emac: ethernet@01c0b000 {
                         pinctrl-names = "default";
                         pinctrl-0 = <&emac_pins_a>;
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index 078ed7f618d7..0c1447c68059 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -22,7 +22,7 @@
                 bootargs = "earlyprintk console=ttyS0,115200";
         };
 
-        soc@01c20000 {
+        soc@01c00000 {
                 uart0: serial@01c28000 {
                         pinctrl-names = "default";
                         pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index b2bd6e124250..c32770a28acf 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -160,11 +160,10 @@
                 };
         };
 
-        soc@01c20000 {
+        soc@01c00000 {
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <1>;
-                reg = <0x01c20000 0x300000>;
                 ranges;
 
                 emac: ethernet@01c0b000 {
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 64dc0c42c43a..3c9f8b3cd3e3 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -18,7 +18,7 @@
         model = "Olimex A10s-Olinuxino Micro";
         compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s";
 
-        soc@01c20000 {
+        soc@01c00000 {
                 emac: ethernet@01c0b000 {
                         pinctrl-names = "default";
                         pinctrl-0 = <&emac_pins_a>;
@@ -60,6 +60,31 @@
                         pinctrl-0 = <&uart3_pins_a>;
                         status = "okay";
                 };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                };
+
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+
+                        at24@50 {
+                                compatible = "at,24c16";
+                                pagesize = <16>;
+                                reg = <0x50>;
+                                read-only;
+                        };
+                };
+
+                i2c2: i2c@01c2b400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_pins_a>;
+                        status = "okay";
+                };
         };
 
         leds {
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 2307ce827ae0..3b4a0574f068 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -95,20 +95,16 @@
 
                 ahb_gates: ahb_gates@01c20060 {
                         #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-ahb-gates-clk";
+                        compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
                         reg = <0x01c20060 0x8>;
                         clocks = <&ahb>;
-                        clock-output-names = "ahb_usb0", "ahb_ehci0",
-                                "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
-                                "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
-                                "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
-                                "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
-                                "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
-                                "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
-                                "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
-                                "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
-                                "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
-                                "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+                        clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
+                                "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+                                "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
+                                "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
+                                "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
+                                "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
+                                "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
                 };
 
                 apb0: apb0@01c20054 {
@@ -120,12 +116,11 @@
 
                 apb0_gates: apb0_gates@01c20068 {
                         #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-apb0-gates-clk";
+                        compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
                         reg = <0x01c20068 0x4>;
                         clocks = <&apb0>;
-                        clock-output-names = "apb0_codec", "apb0_spdif",
-                                "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
-                                "apb0_ir1", "apb0_keypad";
+                        clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
+                                "apb0_ir", "apb0_keypad";
                 };
 
                 /* dummy is pll62 */
@@ -145,23 +140,19 @@
 
                 apb1_gates: apb1_gates@01c2006c {
                         #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-apb1-gates-clk";
+                        compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
                         reg = <0x01c2006c 0x4>;
                         clocks = <&apb1>;
                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
-                                "apb1_i2c2", "apb1_can", "apb1_scr",
-                                "apb1_ps20", "apb1_ps21", "apb1_uart0",
-                                "apb1_uart1", "apb1_uart2", "apb1_uart3",
-                                "apb1_uart4", "apb1_uart5", "apb1_uart6",
-                                "apb1_uart7";
+                                "apb1_i2c2", "apb1_uart0", "apb1_uart1",
+                                "apb1_uart2", "apb1_uart3";
                 };
         };
 
-        soc@01c20000 {
+        soc@01c00000 {
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <1>;
-                reg = <0x01c20000 0x300000>;
                 ranges;
 
                 emac: ethernet@01c0b000 {
@@ -229,6 +220,27 @@
                                 allwinner,drive = <0>;
                                 allwinner,pull = <0>;
                         };
+
+                        i2c0_pins_a: i2c0@0 {
+                                allwinner,pins = "PB0", "PB1";
+                                allwinner,function = "i2c0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        i2c1_pins_a: i2c1@0 {
+                                allwinner,pins = "PB15", "PB16";
+                                allwinner,function = "i2c1";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        i2c2_pins_a: i2c2@0 {
+                                allwinner,pins = "PB17", "PB18";
+                                allwinner,function = "i2c2";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                 };
 
                 timer@01c20c00 {
@@ -282,5 +294,38 @@
                         clocks = <&apb1_gates 19>;
                         status = "disabled";
                 };
+
+                i2c0: i2c@01c2ac00 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2ac00 0x400>;
+                        interrupts = <7>;
+                        clocks = <&apb1_gates 0>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+
+                i2c1: i2c@01c2b000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2b000 0x400>;
+                        interrupts = <8>;
+                        clocks = <&apb1_gates 1>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+
+                i2c2: i2c@01c2b400 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2b400 0x400>;
+                        interrupts = <9>;
+                        clocks = <&apb1_gates 2>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 80497e376706..9e508dcc4245 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -22,7 +22,7 @@
                 bootargs = "earlyprintk console=ttyS0,115200";
         };
 
-        soc@01c20000 {
+        soc@01c00000 {
                 pinctrl@01c20800 {
                         led_pins_olinuxino: led_pins@0 {
                                 allwinner,pins = "PG9";
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 7363211daf84..f6091dc0936c 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -150,11 +150,10 @@
                 };
         };
 
-        soc@01c20000 {
+        soc@01c00000 {
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <1>;
-                reg = <0x01c20000 0x300000>;
                 ranges;
 
                 intc: interrupt-controller@01c20400 {
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
new file mode 100644
index 000000000000..e5adae30899b
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun6i-a31.dtsi"
+
+/ {
+        model = "WITS A31 Colombus Evaluation Board";
+        compatible = "wits,colombus", "allwinner,sun6i-a31";
+
+        chosen {
+                bootargs = "earlyprintk console=ttyS0,115200";
+        };
+
+        soc@01c00000 {
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
new file mode 100644
index 000000000000..f244f5f02365
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -0,0 +1,299 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        interrupt-parent = <&gic>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+
+                cpu@2 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <2>;
+                };
+
+                cpu@3 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <3>;
+                };
+        };
+
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                osc24M: osc24M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+
+                osc32k: osc32k {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                pll1: pll1@01c20000 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun6i-a31-pll1-clk";
+                        reg = <0x01c20000 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                /*
+                 * This is a dummy clock, to be used as placeholder on
+                 * other mux clocks when a specific parent clock is not
+                 * yet implemented. It should be dropped when the driver
+                 * is complete.
+                 */
+                pll6: pll6 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+
+                cpu: cpu@01c20050 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-cpu-clk";
+                        reg = <0x01c20050 0x4>;
+
+                        /*
+                         * PLL1 is listed twice here.
+                         * While it looks suspicious, it's actually documented
+                         * that way both in the datasheet and in the code from
+                         * Allwinner.
+                         */
+                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
+                };
+
+                axi: axi@01c20050 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-axi-clk";
+                        reg = <0x01c20050 0x4>;
+                        clocks = <&cpu>;
+                };
+
+                ahb1_mux: ahb1_mux@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
+                };
+
+                ahb1: ahb1@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-ahb-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&ahb1_mux>;
+                };
+
+                ahb1_gates: ahb1_gates@01c20060 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
+                        reg = <0x01c20060 0x8>;
+                        clocks = <&ahb1>;
+                        clock-output-names = "ahb1_mipidsi", "ahb1_ss",
+                                        "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
+                                        "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
+                                        "ahb1_nand0", "ahb1_sdram",
+                                        "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
+                                        "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
+                                        "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
+                                        "ahb1_ehci1", "ahb1_ohci0",
+                                        "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
+                                        "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
+                                        "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
+                                        "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
+                                        "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
+                                        "ahb1_drc0", "ahb1_drc1";
+                };
+
+                apb1: apb1@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb0-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&ahb1>;
+                };
+
+                apb1_gates: apb1_gates@01c20060 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-apb1-gates-clk";
+                        reg = <0x01c20068 0x4>;
+                        clocks = <&apb1>;
+                        clock-output-names = "apb1_codec", "apb1_digital_mic",
+                                        "apb1_pio", "apb1_daudio0",
+                                        "apb1_daudio1";
+                };
+
+                apb2_mux: apb2_mux@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-mux-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+                };
+
+                apb2: apb2@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun6i-a31-apb2-div-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&apb2_mux>;
+                };
+
+                apb2_gates: apb2_gates@01c2006c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-apb2-gates-clk";
+                        reg = <0x01c2006c 0x8>;
+                        clocks = <&apb2>;
+                        clock-output-names = "apb2_i2c0", "apb2_i2c1",
+                                        "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
+                                        "apb2_uart1", "apb2_uart2", "apb2_uart3",
+                                        "apb2_uart4", "apb2_uart5";
+                };
+        };
+
+        soc@01c00000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                pio: pinctrl@01c20800 {
+                        compatible = "allwinner,sun6i-a31-pinctrl";
+                        reg = <0x01c20800 0x400>;
+                        interrupts = <0 11 1>, <0 15 1>, <0 16 1>, <0 17 1>;
+                        clocks = <&apb1_gates 5>;
+                        gpio-controller;
+                        interrupt-controller;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #gpio-cells = <3>;
+
+                        uart0_pins_a: uart0@0 {
+                                allwinner,pins = "PH20", "PH21";
+                                allwinner,function = "uart0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                timer@01c20c00 {
+                        compatible = "allwinner,sun4i-timer";
+                        reg = <0x01c20c00 0xa0>;
+                        interrupts = <0 18 1>,
+                                     <0 19 1>,
+                                     <0 20 1>,
+                                     <0 21 1>,
+                                     <0 22 1>;
+                        clocks = <&osc24M>;
+                };
+
+                wdt1: watchdog@01c20ca0 {
+                        compatible = "allwinner,sun6i-wdt";
+                        reg = <0x01c20ca0 0x20>;
+                };
+
+                uart0: serial@01c28000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28000 0x400>;
+                        interrupts = <0 0 1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb2_gates 16>;
+                        status = "disabled";
+                };
+
+                uart1: serial@01c28400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28400 0x400>;
+                        interrupts = <0 1 1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb2_gates 17>;
+                        status = "disabled";
+                };
+
+                uart2: serial@01c28800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28800 0x400>;
+                        interrupts = <0 2 1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb2_gates 18>;
+                        status = "disabled";
+                };
+
+                uart3: serial@01c28c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28c00 0x400>;
+                        interrupts = <0 3 1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb2_gates 19>;
+                        status = "disabled";
+                };
+
+                uart4: serial@01c29000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c29000 0x400>;
+                        interrupts = <0 4 1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb2_gates 20>;
+                        status = "disabled";
+                };
+
+                uart5: serial@01c29400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c29400 0x400>;
+                        interrupts = <0 5 1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb2_gates 21>;
+                        status = "disabled";
+                };
+
+                gic: interrupt-controller@01c81000 {
+                        compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+                        reg = <0x01c81000 0x1000>,
+                              <0x01c82000 0x1000>,
+                              <0x01c84000 0x2000>,
+                              <0x01c86000 0x2000>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        interrupts = <1 9 0xf04>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
new file mode 100644
index 000000000000..31b76f08b3ad
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+
+/ {
+        model = "Cubietech Cubieboard2";
+        compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
+
+        soc@01c00000 {
+                pinctrl@01c20800 {
+                        led_pins_cubieboard2: led_pins@0 {
+                                allwinner,pins = "PH20", "PH21";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_cubieboard2>;
+
+                blue {
+                        label = "cubieboard2:blue:usr";
+                        gpios = <&pio 7 21 0>;
+                };
+
+                green {
+                        label = "cubieboard2:green:usr";
+                        gpios = <&pio 7 20 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
new file mode 100644
index 000000000000..34a6c02a7c72
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+
+/ {
+        model = "Olimex A20-Olinuxino Micro";
+        compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
+
+        soc@01c00000 {
+                pinctrl@01c20800 {
+                        led_pins_olinuxino: led_pins@0 {
+                                allwinner,pins = "PH2";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <1>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+
+                uart6: serial@01c29800 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart6_pins_a>;
+                        status = "okay";
+                };
+
+                uart7: serial@01c29c00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart7_pins_a>;
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_olinuxino>;
+
+                green {
+                        label = "a20-olinuxino-micro:green:usr";
+                        gpios = <&pio 7 2 0>;
+                        default-state = "on";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
new file mode 100644
index 000000000000..999ff45cb77e
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -0,0 +1,311 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        interrupt-parent = <&gic>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+        };
+
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                osc24M: osc24M@01c20050 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-osc-clk";
+                        reg = <0x01c20050 0x4>;
+                        clock-frequency = <24000000>;
+                };
+
+                osc32k: osc32k {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                pll1: pll1@01c20000 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20000 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                /*
+                 * This is a dummy clock, to be used as placeholder on
+                 * other mux clocks when a specific parent clock is not
+                 * yet implemented. It should be dropped when the driver
+                 * is complete.
+                 */
+                pll6: pll6 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+
+                cpu: cpu@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-cpu-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
+                };
+
+                axi: axi@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-axi-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&cpu>;
+                };
+
+                ahb: ahb@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-ahb-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&axi>;
+                };
+
+                ahb_gates: ahb_gates@01c20060 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun7i-a20-ahb-gates-clk";
+                        reg = <0x01c20060 0x8>;
+                        clocks = <&ahb>;
+                        clock-output-names = "ahb_usb0", "ahb_ehci0",
+                                "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
+                                "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+                                "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
+                                "ahb_nand", "ahb_sdram", "ahb_ace",
+                                "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
+                                "ahb_spi2", "ahb_spi3", "ahb_sata",
+                                "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
+                                "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
+                                "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
+                                "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+                                "ahb_de_fe1", "ahb_gmac", "ahb_mp",
+                                "ahb_mali";
+                };
+
+                apb0: apb0@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb0-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&ahb>;
+                };
+
+                apb0_gates: apb0_gates@01c20068 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun7i-a20-apb0-gates-clk";
+                        reg = <0x01c20068 0x4>;
+                        clocks = <&apb0>;
+                        clock-output-names = "apb0_codec", "apb0_spdif",
+                                "apb0_ac97", "apb0_iis0", "apb0_iis1",
+                                "apb0_pio", "apb0_ir0", "apb0_ir1",
+                                "apb0_iis2", "apb0_keypad";
+                };
+
+                apb1_mux: apb1_mux@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-mux-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&osc24M>, <&pll6>, <&osc32k>;
+                };
+
+                apb1: apb1@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&apb1_mux>;
+                };
+
+                apb1_gates: apb1_gates@01c2006c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun7i-a20-apb1-gates-clk";
+                        reg = <0x01c2006c 0x4>;
+                        clocks = <&apb1>;
+                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
+                                "apb1_i2c2", "apb1_i2c3", "apb1_can",
+                                "apb1_scr", "apb1_ps20", "apb1_ps21",
+                                "apb1_i2c4", "apb1_uart0", "apb1_uart1",
+                                "apb1_uart2", "apb1_uart3", "apb1_uart4",
+                                "apb1_uart5", "apb1_uart6", "apb1_uart7";
+                };
+        };
+
+        soc@01c00000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                pio: pinctrl@01c20800 {
+                        compatible = "allwinner,sun7i-a20-pinctrl";
+                        reg = <0x01c20800 0x400>;
+                        interrupts = <0 28 1>;
+                        clocks = <&apb0_gates 5>;
+                        gpio-controller;
+                        interrupt-controller;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #gpio-cells = <3>;
+
+                        uart0_pins_a: uart0@0 {
+                                allwinner,pins = "PB22", "PB23";
+                                allwinner,function = "uart0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        uart6_pins_a: uart6@0 {
+                                allwinner,pins = "PI12", "PI13";
+                                allwinner,function = "uart6";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        uart7_pins_a: uart7@0 {
+                                allwinner,pins = "PI20", "PI21";
+                                allwinner,function = "uart7";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                timer@01c20c00 {
+                        compatible = "allwinner,sun4i-timer";
+                        reg = <0x01c20c00 0x90>;
+                        interrupts = <0 22 1>,
+                                     <0 23 1>,
+                                     <0 24 1>,
+                                     <0 25 1>,
+                                     <0 67 1>,
+                                     <0 68 1>;
+                        clocks = <&osc24M>;
+                };
+
+                wdt: watchdog@01c20c90 {
+                        compatible = "allwinner,sun4i-wdt";
+                        reg = <0x01c20c90 0x10>;
+                };
+
+                uart0: serial@01c28000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28000 0x400>;
+                        interrupts = <0 1 1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 16>;
+                        status = "disabled";
+                };
+
+                uart1: serial@01c28400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28400 0x400>;
+                        interrupts = <0 2 1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 17>;
+                        status = "disabled";
+                };
+
+                uart2: serial@01c28800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28800 0x400>;
+                        interrupts = <0 3 1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 18>;
+                        status = "disabled";
+                };
+
+                uart3: serial@01c28c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28c00 0x400>;
+                        interrupts = <0 4 1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 19>;
+                        status = "disabled";
+                };
+
+                uart4: serial@01c29000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c29000 0x400>;
+                        interrupts = <0 17 1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 20>;
+                        status = "disabled";
+                };
+
+                uart5: serial@01c29400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c29400 0x400>;
+                        interrupts = <0 18 1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 21>;
+                        status = "disabled";
+                };
+
+                uart6: serial@01c29800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c29800 0x400>;
+                        interrupts = <0 19 1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 22>;
+                        status = "disabled";
+                };
+
+                uart7: serial@01c29c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c29c00 0x400>;
+                        interrupts = <0 20 1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 23>;
+                        status = "disabled";
+                };
+
+                gic: interrupt-controller@01c81000 {
+                        compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+                        reg = <0x01c81000 0x1000>,
+                              <0x01c82000 0x1000>,
+                              <0x01c84000 0x2000>,
+                              <0x01c86000 0x2000>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        interrupts = <1 9 0xf04>;
+                };
+        };
+};