6 files changed, 18 insertions, 18 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 35f4182c63b6..b1e11f8434e2 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -127,7 +127,7 @@ static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
         /* flags not zero */
         if (args.v1.ucReplyStatus == 2) {
                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
-                r = -EBUSY;
+                r = -EIO;
                 goto done;
         }
 
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index 10dae4106c08..584090ac3eb9 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -1179,7 +1179,7 @@ static int ci_stop_dpm(struct radeon_device *rdev)
         tmp &= ~GLOBAL_PWRMGT_EN;
         WREG32_SMC(GENERAL_PWRMGT, tmp);
 
-        tmp = RREG32(SCLK_PWRMGT_CNTL);
+        tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
         tmp &= ~DYNAMIC_PM_EN;
         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
 
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index dcd4518a9b08..0b2471107137 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -7676,14 +7676,16 @@ restart_ih:
                         addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
                         status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
                         mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
+                        /* reset addr and status */
+                        WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
+                        if (addr == 0x0 && status == 0x0)
+                                break;
                         dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
                                 addr);
                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
                                 status);
                         cik_vm_decode_fault(rdev, status, addr, mc_client);
-                        /* reset addr and status */
-                        WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
                         break;
                 case 167: /* VCE */
                         DRM_DEBUG("IH: VCE int: 0x%08x\n", src_data);
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e2f605224e8c..f7ece0ff431b 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -189,7 +189,7 @@ static const u32 evergreen_golden_registers[] =
         0x8c1c, 0xffffffff, 0x00001010,
         0x28350, 0xffffffff, 0x00000000,
         0xa008, 0xffffffff, 0x00010000,
-        0x5cc, 0xffffffff, 0x00000001,
+        0x5c4, 0xffffffff, 0x00000001,
         0x9508, 0xffffffff, 0x00000002,
         0x913c, 0x0000000f, 0x0000000a
 };
@@ -476,7 +476,7 @@ static const u32 cedar_golden_registers[] =
         0x8c1c, 0xffffffff, 0x00001010,
         0x28350, 0xffffffff, 0x00000000,
         0xa008, 0xffffffff, 0x00010000,
-        0x5cc, 0xffffffff, 0x00000001,
+        0x5c4, 0xffffffff, 0x00000001,
         0x9508, 0xffffffff, 0x00000002
 };
 
@@ -635,7 +635,7 @@ static const u32 juniper_mgcg_init[] =
 static const u32 supersumo_golden_registers[] =
 {
         0x5eb4, 0xffffffff, 0x00000002,
-        0x5cc, 0xffffffff, 0x00000001,
+        0x5c4, 0xffffffff, 0x00000001,
         0x7030, 0xffffffff, 0x00000011,
         0x7c30, 0xffffffff, 0x00000011,
         0x6104, 0x01000300, 0x00000000,
@@ -719,7 +719,7 @@ static const u32 sumo_golden_registers[] =
 static const u32 wrestler_golden_registers[] =
 {
         0x5eb4, 0xffffffff, 0x00000002,
-        0x5cc, 0xffffffff, 0x00000001,
+        0x5c4, 0xffffffff, 0x00000001,
         0x7030, 0xffffffff, 0x00000011,
         0x7c30, 0xffffffff, 0x00000011,
         0x6104, 0x01000300, 0x00000000,
@@ -5066,14 +5066,16 @@ restart_ih:
                 case 147:
                         addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
                         status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
+                        /* reset addr and status */
+                        WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
+                        if (addr == 0x0 && status == 0x0)
+                                break;
                         dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
                                 addr);
                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
                                 status);
                         cayman_vm_decode_fault(rdev, status, addr);
-                        /* reset addr and status */
-                        WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
                         break;
                 case 176: /* CP_INT in ring buffer */
                 case 177: /* CP_INT in IB1 */
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c
index da041a43d82e..3c76e1dcdf04 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.c
+++ b/drivers/gpu/drm/radeon/rv770_dpm.c
@@ -2329,12 +2329,6 @@ void rv770_get_engine_memory_ss(struct radeon_device *rdev)
         pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
                                                        ASIC_INTERNAL_MEMORY_SS, 0);
 
-        /* disable ss, causes hangs on some cayman boards */
-        if (rdev->family == CHIP_CAYMAN) {
-                pi->sclk_ss = false;
-                pi->mclk_ss = false;
-        }
-
         if (pi->sclk_ss || pi->mclk_ss)
                 pi->dynamic_ss = true;
         else
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 730cee2c34cf..eba0225259a4 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -6376,14 +6376,16 @@ restart_ih:
                 case 147:
                         addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
                         status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
+                        /* reset addr and status */
+                        WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
+                        if (addr == 0x0 && status == 0x0)
+                                break;
                         dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
                                 addr);
                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
                                 status);
                         si_vm_decode_fault(rdev, status, addr);
-                        /* reset addr and status */
-                        WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
                         break;
                 case 176: /* RINGID0 CP_INT */
                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);