aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h23
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fence.c24
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c12
-rw-r--r--drivers/gpu/drm/nouveau/nvd0_display.c4
4 files changed, 38 insertions, 25 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 0df21752d274..eaf9872f9ee2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -1763,13 +1763,26 @@ nv44_graph_class(struct drm_device *dev)
1763#define NV_MEM_TYPE_VM 0x7f 1763#define NV_MEM_TYPE_VM 0x7f
1764#define NV_MEM_COMP_VM 0x03 1764#define NV_MEM_COMP_VM 0x03
1765 1765
1766/* FIFO methods */
1767#define NV01_SUBCHAN_OBJECT 0x00000000
1768#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010
1769#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014
1770#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018
1771#define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c
1772#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001
1773#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002
1774#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004
1775#define NV84_SUBCHAN_NOTIFY_INTR 0x00000020
1776#define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024
1777#define NV10_SUBCHAN_REF_CNT 0x00000050
1778#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
1779#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
1780#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
1781#define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
1782#define NV40_SUBCHAN_YIELD 0x00000080
1783
1766/* NV_SW object class */ 1784/* NV_SW object class */
1767#define NV_SW 0x0000506e 1785#define NV_SW 0x0000506e
1768#define NV_SW_DMA_SEMAPHORE 0x00000060
1769#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1770#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1771#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1772#define NV_SW_YIELD 0x00000080
1773#define NV_SW_DMA_VBLSEM 0x0000018c 1786#define NV_SW_DMA_VBLSEM 0x0000018c
1774#define NV_SW_VBLSEM_OFFSET 0x00000400 1787#define NV_SW_VBLSEM_OFFSET 0x00000400
1775#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1788#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
index 2f6daae68b9d..f676ecd3fd3c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -165,9 +165,9 @@ nouveau_fence_emit(struct nouveau_fence *fence)
165 165
166 if (USE_REFCNT(dev)) { 166 if (USE_REFCNT(dev)) {
167 if (dev_priv->card_type < NV_C0) 167 if (dev_priv->card_type < NV_C0)
168 BEGIN_RING(chan, NvSubSw, 0x0050, 1); 168 BEGIN_RING(chan, 0, NV10_SUBCHAN_REF_CNT, 1);
169 else 169 else
170 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0050, 1); 170 BEGIN_NVC0(chan, 2, 0, NV10_SUBCHAN_REF_CNT, 1);
171 } else { 171 } else {
172 BEGIN_RING(chan, NvSubSw, 0x0150, 1); 172 BEGIN_RING(chan, NvSubSw, 0x0150, 1);
173 } 173 }
@@ -344,7 +344,7 @@ semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
344 if (ret) 344 if (ret)
345 return ret; 345 return ret;
346 346
347 BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 3); 347 BEGIN_RING(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 3);
348 OUT_RING (chan, NvSema); 348 OUT_RING (chan, NvSema);
349 OUT_RING (chan, offset); 349 OUT_RING (chan, offset);
350 OUT_RING (chan, 1); 350 OUT_RING (chan, 1);
@@ -354,9 +354,9 @@ semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
354 if (ret) 354 if (ret)
355 return ret; 355 return ret;
356 356
357 BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1); 357 BEGIN_RING(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
358 OUT_RING (chan, chan->vram_handle); 358 OUT_RING (chan, chan->vram_handle);
359 BEGIN_RING(chan, NvSubSw, 0x0010, 4); 359 BEGIN_RING(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
360 OUT_RING (chan, upper_32_bits(offset)); 360 OUT_RING (chan, upper_32_bits(offset));
361 OUT_RING (chan, lower_32_bits(offset)); 361 OUT_RING (chan, lower_32_bits(offset));
362 OUT_RING (chan, 1); 362 OUT_RING (chan, 1);
@@ -366,7 +366,7 @@ semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
366 if (ret) 366 if (ret)
367 return ret; 367 return ret;
368 368
369 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4); 369 BEGIN_NVC0(chan, 2, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
370 OUT_RING (chan, upper_32_bits(offset)); 370 OUT_RING (chan, upper_32_bits(offset));
371 OUT_RING (chan, lower_32_bits(offset)); 371 OUT_RING (chan, lower_32_bits(offset));
372 OUT_RING (chan, 1); 372 OUT_RING (chan, 1);
@@ -397,10 +397,10 @@ semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
397 if (ret) 397 if (ret)
398 return ret; 398 return ret;
399 399
400 BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 2); 400 BEGIN_RING(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
401 OUT_RING (chan, NvSema); 401 OUT_RING (chan, NvSema);
402 OUT_RING (chan, offset); 402 OUT_RING (chan, offset);
403 BEGIN_RING(chan, NvSubSw, NV_SW_SEMAPHORE_RELEASE, 1); 403 BEGIN_RING(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
404 OUT_RING (chan, 1); 404 OUT_RING (chan, 1);
405 } else 405 } else
406 if (dev_priv->chipset < 0xc0) { 406 if (dev_priv->chipset < 0xc0) {
@@ -408,9 +408,9 @@ semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
408 if (ret) 408 if (ret)
409 return ret; 409 return ret;
410 410
411 BEGIN_RING(chan, NvSubSw, NV_SW_DMA_SEMAPHORE, 1); 411 BEGIN_RING(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
412 OUT_RING (chan, chan->vram_handle); 412 OUT_RING (chan, chan->vram_handle);
413 BEGIN_RING(chan, NvSubSw, 0x0010, 4); 413 BEGIN_RING(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
414 OUT_RING (chan, upper_32_bits(offset)); 414 OUT_RING (chan, upper_32_bits(offset));
415 OUT_RING (chan, lower_32_bits(offset)); 415 OUT_RING (chan, lower_32_bits(offset));
416 OUT_RING (chan, 1); 416 OUT_RING (chan, 1);
@@ -420,7 +420,7 @@ semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema)
420 if (ret) 420 if (ret)
421 return ret; 421 return ret;
422 422
423 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4); 423 BEGIN_NVC0(chan, 2, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
424 OUT_RING (chan, upper_32_bits(offset)); 424 OUT_RING (chan, upper_32_bits(offset));
425 OUT_RING (chan, lower_32_bits(offset)); 425 OUT_RING (chan, lower_32_bits(offset));
426 OUT_RING (chan, 1); 426 OUT_RING (chan, 1);
@@ -510,7 +510,7 @@ nouveau_fence_channel_init(struct nouveau_channel *chan)
510 if (ret) 510 if (ret)
511 return ret; 511 return ret;
512 512
513 BEGIN_RING(chan, NvSubSw, 0, 1); 513 BEGIN_RING(chan, NvSubSw, NV01_SUBCHAN_OBJECT, 1);
514 OUT_RING (chan, NvSw); 514 OUT_RING (chan, NvSw);
515 FIRE_RING (chan); 515 FIRE_RING (chan);
516 } 516 }
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 0e47a898f415..8b78b9cfa383 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -474,15 +474,15 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
474 } 474 }
475 475
476 if (dev_priv->chipset < 0xc0) { 476 if (dev_priv->chipset < 0xc0) {
477 BEGIN_RING(chan, NvSubSw, 0x0060, 2); 477 BEGIN_RING(chan, 0, 0x0060, 2);
478 OUT_RING (chan, NvEvoSema0 + nv_crtc->index); 478 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
479 OUT_RING (chan, dispc->sem.offset); 479 OUT_RING (chan, dispc->sem.offset);
480 BEGIN_RING(chan, NvSubSw, 0x006c, 1); 480 BEGIN_RING(chan, 0, 0x006c, 1);
481 OUT_RING (chan, 0xf00d0000 | dispc->sem.value); 481 OUT_RING (chan, 0xf00d0000 | dispc->sem.value);
482 BEGIN_RING(chan, NvSubSw, 0x0064, 2); 482 BEGIN_RING(chan, 0, 0x0064, 2);
483 OUT_RING (chan, dispc->sem.offset ^ 0x10); 483 OUT_RING (chan, dispc->sem.offset ^ 0x10);
484 OUT_RING (chan, 0x74b1e000); 484 OUT_RING (chan, 0x74b1e000);
485 BEGIN_RING(chan, NvSubSw, 0x0060, 1); 485 BEGIN_RING(chan, 0, 0x0060, 1);
486 if (dev_priv->chipset < 0x84) 486 if (dev_priv->chipset < 0x84)
487 OUT_RING (chan, NvSema); 487 OUT_RING (chan, NvSema);
488 else 488 else
@@ -490,12 +490,12 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
490 } else { 490 } else {
491 u64 offset = chan->dispc_vma[nv_crtc->index].offset; 491 u64 offset = chan->dispc_vma[nv_crtc->index].offset;
492 offset += dispc->sem.offset; 492 offset += dispc->sem.offset;
493 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4); 493 BEGIN_NVC0(chan, 2, 0, 0x0010, 4);
494 OUT_RING (chan, upper_32_bits(offset)); 494 OUT_RING (chan, upper_32_bits(offset));
495 OUT_RING (chan, lower_32_bits(offset)); 495 OUT_RING (chan, lower_32_bits(offset));
496 OUT_RING (chan, 0xf00d0000 | dispc->sem.value); 496 OUT_RING (chan, 0xf00d0000 | dispc->sem.value);
497 OUT_RING (chan, 0x1002); 497 OUT_RING (chan, 0x1002);
498 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4); 498 BEGIN_NVC0(chan, 2, 0, 0x0010, 4);
499 OUT_RING (chan, upper_32_bits(offset)); 499 OUT_RING (chan, upper_32_bits(offset));
500 OUT_RING (chan, lower_32_bits(offset ^ 0x10)); 500 OUT_RING (chan, lower_32_bits(offset ^ 0x10));
501 OUT_RING (chan, 0x74b1e000); 501 OUT_RING (chan, 0x74b1e000);
diff --git a/drivers/gpu/drm/nouveau/nvd0_display.c b/drivers/gpu/drm/nouveau/nvd0_display.c
index dfb8a951cbbe..5e2b79bdcae0 100644
--- a/drivers/gpu/drm/nouveau/nvd0_display.c
+++ b/drivers/gpu/drm/nouveau/nvd0_display.c
@@ -303,12 +303,12 @@ nvd0_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
303 offset = chan->dispc_vma[nv_crtc->index].offset; 303 offset = chan->dispc_vma[nv_crtc->index].offset;
304 offset += evo->sem.offset; 304 offset += evo->sem.offset;
305 305
306 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4); 306 BEGIN_NVC0(chan, 2, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
307 OUT_RING (chan, upper_32_bits(offset)); 307 OUT_RING (chan, upper_32_bits(offset));
308 OUT_RING (chan, lower_32_bits(offset)); 308 OUT_RING (chan, lower_32_bits(offset));
309 OUT_RING (chan, 0xf00d0000 | evo->sem.value); 309 OUT_RING (chan, 0xf00d0000 | evo->sem.value);
310 OUT_RING (chan, 0x1002); 310 OUT_RING (chan, 0x1002);
311 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4); 311 BEGIN_NVC0(chan, 2, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
312 OUT_RING (chan, upper_32_bits(offset)); 312 OUT_RING (chan, upper_32_bits(offset));
313 OUT_RING (chan, lower_32_bits(offset ^ 0x10)); 313 OUT_RING (chan, lower_32_bits(offset ^ 0x10));
314 OUT_RING (chan, 0x74b1e000); 314 OUT_RING (chan, 0x74b1e000);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 16:07:26 -0500