aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c6
-rw-r--r--arch/arm/mach-omap2/dpll44xx.c6
-rw-r--r--include/linux/clk/ti.h4
3 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 20e120d071dd..c2da2a0fe5ad 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -474,7 +474,7 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
474 */ 474 */
475long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate, 475long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
476 unsigned long *best_parent_rate, 476 unsigned long *best_parent_rate,
477 struct clk **best_parent_clk) 477 struct clk_hw **best_parent_clk)
478{ 478{
479 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 479 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
480 struct dpll_data *dd; 480 struct dpll_data *dd;
@@ -488,10 +488,10 @@ long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
488 488
489 if (__clk_get_rate(dd->clk_bypass) == rate && 489 if (__clk_get_rate(dd->clk_bypass) == rate &&
490 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { 490 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
491 *best_parent_clk = dd->clk_bypass; 491 *best_parent_clk = __clk_get_hw(dd->clk_bypass);
492 } else { 492 } else {
493 rate = omap2_dpll_round_rate(hw, rate, best_parent_rate); 493 rate = omap2_dpll_round_rate(hw, rate, best_parent_rate);
494 *best_parent_clk = dd->clk_ref; 494 *best_parent_clk = __clk_get_hw(dd->clk_ref);
495 } 495 }
496 496
497 *best_parent_rate = rate; 497 *best_parent_rate = rate;
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 535822fcf4bb..0e58e5a85d53 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -223,7 +223,7 @@ out:
223 */ 223 */
224long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate, 224long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
225 unsigned long *best_parent_rate, 225 unsigned long *best_parent_rate,
226 struct clk **best_parent_clk) 226 struct clk_hw **best_parent_clk)
227{ 227{
228 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 228 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
229 struct dpll_data *dd; 229 struct dpll_data *dd;
@@ -237,11 +237,11 @@ long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
237 237
238 if (__clk_get_rate(dd->clk_bypass) == rate && 238 if (__clk_get_rate(dd->clk_bypass) == rate &&
239 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { 239 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
240 *best_parent_clk = dd->clk_bypass; 240 *best_parent_clk = __clk_get_hw(dd->clk_bypass);
241 } else { 241 } else {
242 rate = omap4_dpll_regm4xen_round_rate(hw, rate, 242 rate = omap4_dpll_regm4xen_round_rate(hw, rate,
243 best_parent_rate); 243 best_parent_rate);
244 *best_parent_clk = dd->clk_ref; 244 *best_parent_clk = __clk_get_hw(dd->clk_ref);
245 } 245 }
246 246
247 *best_parent_rate = rate; 247 *best_parent_rate = rate;
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 74e5341463c9..55ef529a0dbf 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -264,7 +264,7 @@ int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
264long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, 264long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
265 unsigned long rate, 265 unsigned long rate,
266 unsigned long *best_parent_rate, 266 unsigned long *best_parent_rate,
267 struct clk **best_parent_clk); 267 struct clk_hw **best_parent_clk);
268unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 268unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
269 unsigned long parent_rate); 269 unsigned long parent_rate);
270long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, 270long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
@@ -273,7 +273,7 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
273long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, 273long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
274 unsigned long rate, 274 unsigned long rate,
275 unsigned long *best_parent_rate, 275 unsigned long *best_parent_rate,
276 struct clk **best_parent_clk); 276 struct clk_hw **best_parent_clk);
277u8 omap2_init_dpll_parent(struct clk_hw *hw); 277u8 omap2_init_dpll_parent(struct clk_hw *hw);
278unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); 278unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
279long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, 279long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,