ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs

While the change for determine_rate clock operation was merged,
the OMAP counterpart using these calls was overlooked for some reason,
and caused boot failures on at least OMAP4 platforms. Fixed by updating
the DPLL API calls to use the new parameters.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Fixes: 646cafc6aa ("clk: Change clk_ops->determine_rate")
Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Reported-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

3 files changed, 8 insertions, 8 deletions

diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 20e120d071dd..c2da2a0fe5ad 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -474,7 +474,7 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
  */
 long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
                                        unsigned long *best_parent_rate,
-                                       struct clk **best_parent_clk)
+                                       struct clk_hw **best_parent_clk)
 {
         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
         struct dpll_data *dd;
@@ -488,10 +488,10 @@ long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
 
         if (__clk_get_rate(dd->clk_bypass) == rate &&
             (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
-                *best_parent_clk = dd->clk_bypass;
+                *best_parent_clk = __clk_get_hw(dd->clk_bypass);
         } else {
                 rate = omap2_dpll_round_rate(hw, rate, best_parent_rate);
-                *best_parent_clk = dd->clk_ref;
+                *best_parent_clk = __clk_get_hw(dd->clk_ref);
         }
 
         *best_parent_rate = rate;
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index 535822fcf4bb..0e58e5a85d53 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -223,7 +223,7 @@ out:
  */
 long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
                                         unsigned long *best_parent_rate,
-                                        struct clk **best_parent_clk)
+                                        struct clk_hw **best_parent_clk)
 {
         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
         struct dpll_data *dd;
@@ -237,11 +237,11 @@ long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
 
         if (__clk_get_rate(dd->clk_bypass) == rate &&
             (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
-                *best_parent_clk = dd->clk_bypass;
+                *best_parent_clk = __clk_get_hw(dd->clk_bypass);
         } else {
                 rate = omap4_dpll_regm4xen_round_rate(hw, rate,
                                                       best_parent_rate);
-                *best_parent_clk = dd->clk_ref;
+                *best_parent_clk = __clk_get_hw(dd->clk_ref);
         }
 
         *best_parent_rate = rate;
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 74e5341463c9..55ef529a0dbf 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -264,7 +264,7 @@ int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
 long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
                                        unsigned long rate,
                                        unsigned long *best_parent_rate,
-                                       struct clk **best_parent_clk);
+                                       struct clk_hw **best_parent_clk);
 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
                                          unsigned long parent_rate);
 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
@@ -273,7 +273,7 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
 long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
                                         unsigned long rate,
                                         unsigned long *best_parent_rate,
-                                        struct clk **best_parent_clk);
+                                        struct clk_hw **best_parent_clk);
 u8 omap2_init_dpll_parent(struct clk_hw *hw);
 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,