aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi14
-rw-r--r--drivers/clk/samsung/clk-exynos4.c4
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c16
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c854
-rw-r--r--drivers/clk/samsung/clk.c9
-rw-r--r--include/dt-bindings/clock/exynos4.h2
-rw-r--r--include/dt-bindings/clock/exynos5250.h5
-rw-r--r--include/dt-bindings/clock/exynos5420.h39
8 files changed, 608 insertions, 335 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index c3a9a66c5767..67ba2c56fa8e 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -549,7 +549,7 @@
549 #size-cells = <0>; 549 #size-cells = <0>;
550 pinctrl-names = "default"; 550 pinctrl-names = "default";
551 pinctrl-0 = <&i2c4_hs_bus>; 551 pinctrl-0 = <&i2c4_hs_bus>;
552 clocks = <&clock CLK_I2C4>; 552 clocks = <&clock CLK_USI0>;
553 clock-names = "hsi2c"; 553 clock-names = "hsi2c";
554 status = "disabled"; 554 status = "disabled";
555 }; 555 };
@@ -562,7 +562,7 @@
562 #size-cells = <0>; 562 #size-cells = <0>;
563 pinctrl-names = "default"; 563 pinctrl-names = "default";
564 pinctrl-0 = <&i2c5_hs_bus>; 564 pinctrl-0 = <&i2c5_hs_bus>;
565 clocks = <&clock CLK_I2C5>; 565 clocks = <&clock CLK_USI1>;
566 clock-names = "hsi2c"; 566 clock-names = "hsi2c";
567 status = "disabled"; 567 status = "disabled";
568 }; 568 };
@@ -575,7 +575,7 @@
575 #size-cells = <0>; 575 #size-cells = <0>;
576 pinctrl-names = "default"; 576 pinctrl-names = "default";
577 pinctrl-0 = <&i2c6_hs_bus>; 577 pinctrl-0 = <&i2c6_hs_bus>;
578 clocks = <&clock CLK_I2C6>; 578 clocks = <&clock CLK_USI2>;
579 clock-names = "hsi2c"; 579 clock-names = "hsi2c";
580 status = "disabled"; 580 status = "disabled";
581 }; 581 };
@@ -588,7 +588,7 @@
588 #size-cells = <0>; 588 #size-cells = <0>;
589 pinctrl-names = "default"; 589 pinctrl-names = "default";
590 pinctrl-0 = <&i2c7_hs_bus>; 590 pinctrl-0 = <&i2c7_hs_bus>;
591 clocks = <&clock CLK_I2C7>; 591 clocks = <&clock CLK_USI3>;
592 clock-names = "hsi2c"; 592 clock-names = "hsi2c";
593 status = "disabled"; 593 status = "disabled";
594 }; 594 };
@@ -601,7 +601,7 @@
601 #size-cells = <0>; 601 #size-cells = <0>;
602 pinctrl-names = "default"; 602 pinctrl-names = "default";
603 pinctrl-0 = <&i2c8_hs_bus>; 603 pinctrl-0 = <&i2c8_hs_bus>;
604 clocks = <&clock CLK_I2C8>; 604 clocks = <&clock CLK_USI4>;
605 clock-names = "hsi2c"; 605 clock-names = "hsi2c";
606 status = "disabled"; 606 status = "disabled";
607 }; 607 };
@@ -614,7 +614,7 @@
614 #size-cells = <0>; 614 #size-cells = <0>;
615 pinctrl-names = "default"; 615 pinctrl-names = "default";
616 pinctrl-0 = <&i2c9_hs_bus>; 616 pinctrl-0 = <&i2c9_hs_bus>;
617 clocks = <&clock CLK_I2C9>; 617 clocks = <&clock CLK_USI5>;
618 clock-names = "hsi2c"; 618 clock-names = "hsi2c";
619 status = "disabled"; 619 status = "disabled";
620 }; 620 };
@@ -627,7 +627,7 @@
627 #size-cells = <0>; 627 #size-cells = <0>;
628 pinctrl-names = "default"; 628 pinctrl-names = "default";
629 pinctrl-0 = <&i2c10_hs_bus>; 629 pinctrl-0 = <&i2c10_hs_bus>;
630 clocks = <&clock CLK_I2C10>; 630 clocks = <&clock CLK_USI6>;
631 clock-names = "hsi2c"; 631 clock-names = "hsi2c";
632 status = "disabled"; 632 status = "disabled";
633 }; 633 };
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 57ed5a8fb052..c4df294bb7fb 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -428,7 +428,7 @@ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata
428/* fixed rate clocks generated inside the soc */ 428/* fixed rate clocks generated inside the soc */
429static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { 429static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
430 FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), 430 FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
431 FRATE(0, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), 431 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
432 FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), 432 FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
433}; 433};
434 434
@@ -903,7 +903,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
903 GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), 903 GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
904 GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), 904 GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
905 GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), 905 GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
906 GATE(CLK_MDMA2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), 906 GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
907 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 907 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
908 0), 908 0),
909 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), 909 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index e549e862524a..88488596c00b 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -37,6 +37,7 @@
37#define VPLL_CON0 0x10140 37#define VPLL_CON0 0x10140
38#define GPLL_CON0 0x10150 38#define GPLL_CON0 0x10150
39#define SRC_TOP0 0x10210 39#define SRC_TOP0 0x10210
40#define SRC_TOP1 0x10214
40#define SRC_TOP2 0x10218 41#define SRC_TOP2 0x10218
41#define SRC_TOP3 0x1021c 42#define SRC_TOP3 0x1021c
42#define SRC_GSCL 0x10220 43#define SRC_GSCL 0x10220
@@ -71,6 +72,7 @@
71#define GATE_IP_GSCL 0x10920 72#define GATE_IP_GSCL 0x10920
72#define GATE_IP_DISP1 0x10928 73#define GATE_IP_DISP1 0x10928
73#define GATE_IP_MFC 0x1092c 74#define GATE_IP_MFC 0x1092c
75#define GATE_IP_G3D 0x10930
74#define GATE_IP_GEN 0x10934 76#define GATE_IP_GEN 0x10934
75#define GATE_IP_FSYS 0x10944 77#define GATE_IP_FSYS 0x10944
76#define GATE_IP_PERIC 0x10950 78#define GATE_IP_PERIC 0x10950
@@ -100,6 +102,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
100 DIV_CPU0, 102 DIV_CPU0,
101 SRC_CORE1, 103 SRC_CORE1,
102 SRC_TOP0, 104 SRC_TOP0,
105 SRC_TOP1,
103 SRC_TOP2, 106 SRC_TOP2,
104 SRC_TOP3, 107 SRC_TOP3,
105 SRC_GSCL, 108 SRC_GSCL,
@@ -133,6 +136,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
133 DIV_PERIC5, 136 DIV_PERIC5,
134 GATE_IP_GSCL, 137 GATE_IP_GSCL,
135 GATE_IP_MFC, 138 GATE_IP_MFC,
139 GATE_IP_G3D,
136 GATE_IP_GEN, 140 GATE_IP_GEN,
137 GATE_IP_FSYS, 141 GATE_IP_FSYS,
138 GATE_IP_PERIC, 142 GATE_IP_PERIC,
@@ -189,10 +193,12 @@ PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
189PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" }; 193PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
190PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" }; 194PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
191PNAME(mout_epll_p) = { "fin_pll", "fout_epll" }; 195PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
196PNAME(mout_gpll_p) = { "fin_pll", "fout_gpll" };
192PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" }; 197PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
193PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" }; 198PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
194PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" }; 199PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" };
195PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" }; 200PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" };
201PNAME(mout_aclk400_p) = { "mout_aclk400_g3d_mid", "mout_gpll" };
196PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" }; 202PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
197PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" }; 203PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
198PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" }; 204PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
@@ -273,12 +279,16 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
273 MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), 279 MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
274 MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1), 280 MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
275 MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), 281 MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
282 MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
283
284 MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),
276 285
277 MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1), 286 MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
278 MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1), 287 MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
279 MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1), 288 MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
280 MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1), 289 MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
281 MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), 290 MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
291 MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
282 292
283 MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1), 293 MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1),
284 MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1), 294 MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
@@ -351,6 +361,8 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
351 DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3), 361 DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
352 DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3), 362 DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
353 DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3), 363 DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
364 DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
365 24, 3),
354 366
355 DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3), 367 DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
356 368
@@ -428,6 +440,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
428 * CMU_ACP 440 * CMU_ACP
429 */ 441 */
430 GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0), 442 GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
443 GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
431 GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0), 444 GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
432 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0), 445 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
433 446
@@ -533,7 +546,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
533 0), 546 0),
534 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0, 547 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
535 0), 548 0),
536 549 GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0,
550 CLK_SET_RATE_PARENT, 0),
537 GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0), 551 GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
538 GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0), 552 GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
539 GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0), 553 GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index c3e0894d0279..1c3674ecc0dc 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -27,18 +27,24 @@
27#define DIV_CPU1 0x504 27#define DIV_CPU1 0x504
28#define GATE_BUS_CPU 0x700 28#define GATE_BUS_CPU 0x700
29#define GATE_SCLK_CPU 0x800 29#define GATE_SCLK_CPU 0x800
30#define CLKOUT_CMU_CPU 0xa00
31#define GATE_IP_G2D 0x8800
30#define CPLL_LOCK 0x10020 32#define CPLL_LOCK 0x10020
31#define DPLL_LOCK 0x10030 33#define DPLL_LOCK 0x10030
32#define EPLL_LOCK 0x10040 34#define EPLL_LOCK 0x10040
33#define RPLL_LOCK 0x10050 35#define RPLL_LOCK 0x10050
34#define IPLL_LOCK 0x10060 36#define IPLL_LOCK 0x10060
35#define SPLL_LOCK 0x10070 37#define SPLL_LOCK 0x10070
36#define VPLL_LOCK 0x10070 38#define VPLL_LOCK 0x10080
37#define MPLL_LOCK 0x10090 39#define MPLL_LOCK 0x10090
38#define CPLL_CON0 0x10120 40#define CPLL_CON0 0x10120
39#define DPLL_CON0 0x10128 41#define DPLL_CON0 0x10128
40#define EPLL_CON0 0x10130 42#define EPLL_CON0 0x10130
43#define EPLL_CON1 0x10134
44#define EPLL_CON2 0x10138
41#define RPLL_CON0 0x10140 45#define RPLL_CON0 0x10140
46#define RPLL_CON1 0x10144
47#define RPLL_CON2 0x10148
42#define IPLL_CON0 0x10150 48#define IPLL_CON0 0x10150
43#define SPLL_CON0 0x10160 49#define SPLL_CON0 0x10160
44#define VPLL_CON0 0x10170 50#define VPLL_CON0 0x10170
@@ -56,10 +62,14 @@
56#define SRC_FSYS 0x10244 62#define SRC_FSYS 0x10244
57#define SRC_PERIC0 0x10250 63#define SRC_PERIC0 0x10250
58#define SRC_PERIC1 0x10254 64#define SRC_PERIC1 0x10254
65#define SRC_ISP 0x10270
59#define SRC_TOP10 0x10280 66#define SRC_TOP10 0x10280
60#define SRC_TOP11 0x10284 67#define SRC_TOP11 0x10284
61#define SRC_TOP12 0x10288 68#define SRC_TOP12 0x10288
62#define SRC_MASK_DISP10 0x1032c 69#define SRC_MASK_TOP2 0x10308
70#define SRC_MASK_TOP7 0x1031c
71#define SRC_MASK_DISP10 0x1032c
72#define SRC_MASK_MAU 0x10334
63#define SRC_MASK_FSYS 0x10340 73#define SRC_MASK_FSYS 0x10340
64#define SRC_MASK_PERIC0 0x10350 74#define SRC_MASK_PERIC0 0x10350
65#define SRC_MASK_PERIC1 0x10354 75#define SRC_MASK_PERIC1 0x10354
@@ -76,27 +86,38 @@
76#define DIV_PERIC2 0x10560 86#define DIV_PERIC2 0x10560
77#define DIV_PERIC3 0x10564 87#define DIV_PERIC3 0x10564
78#define DIV_PERIC4 0x10568 88#define DIV_PERIC4 0x10568
89#define SCLK_DIV_ISP0 0x10580
90#define SCLK_DIV_ISP1 0x10584
91#define DIV2_RATIO0 0x10590
92#define DIV4_RATIO 0x105a0
79#define GATE_BUS_TOP 0x10700 93#define GATE_BUS_TOP 0x10700
94#define GATE_BUS_GEN 0x1073c
80#define GATE_BUS_FSYS0 0x10740 95#define GATE_BUS_FSYS0 0x10740
96#define GATE_BUS_FSYS2 0x10748
81#define GATE_BUS_PERIC 0x10750 97#define GATE_BUS_PERIC 0x10750
82#define GATE_BUS_PERIC1 0x10754 98#define GATE_BUS_PERIC1 0x10754
83#define GATE_BUS_PERIS0 0x10760 99#define GATE_BUS_PERIS0 0x10760
84#define GATE_BUS_PERIS1 0x10764 100#define GATE_BUS_PERIS1 0x10764
101#define GATE_BUS_NOC 0x10770
102#define GATE_TOP_SCLK_ISP 0x10870
85#define GATE_IP_GSCL0 0x10910 103#define GATE_IP_GSCL0 0x10910
86#define GATE_IP_GSCL1 0x10920 104#define GATE_IP_GSCL1 0x10920
87#define GATE_IP_MFC 0x1092c 105#define GATE_IP_MFC 0x1092c
88#define GATE_IP_DISP1 0x10928 106#define GATE_IP_DISP1 0x10928
89#define GATE_IP_G3D 0x10930 107#define GATE_IP_G3D 0x10930
90#define GATE_IP_GEN 0x10934 108#define GATE_IP_GEN 0x10934
109#define GATE_IP_FSYS 0x10944
110#define GATE_IP_PERIC 0x10950
111#define GATE_IP_PERIS 0x10960
91#define GATE_IP_MSCL 0x10970 112#define GATE_IP_MSCL 0x10970
92#define GATE_TOP_SCLK_GSCL 0x10820 113#define GATE_TOP_SCLK_GSCL 0x10820
93#define GATE_TOP_SCLK_DISP1 0x10828 114#define GATE_TOP_SCLK_DISP1 0x10828
94#define GATE_TOP_SCLK_MAU 0x1083c 115#define GATE_TOP_SCLK_MAU 0x1083c
95#define GATE_TOP_SCLK_FSYS 0x10840 116#define GATE_TOP_SCLK_FSYS 0x10840
96#define GATE_TOP_SCLK_PERIC 0x10850 117#define GATE_TOP_SCLK_PERIC 0x10850
118#define TOP_SPARE2 0x10b08
97#define BPLL_LOCK 0x20010 119#define BPLL_LOCK 0x20010
98#define BPLL_CON0 0x20110 120#define BPLL_CON0 0x20110
99#define SRC_CDREX 0x20200
100#define KPLL_LOCK 0x28000 121#define KPLL_LOCK 0x28000
101#define KPLL_CON0 0x28100 122#define KPLL_CON0 0x28100
102#define SRC_KFC 0x28200 123#define SRC_KFC 0x28200
@@ -124,6 +145,13 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
124 DIV_CPU1, 145 DIV_CPU1,
125 GATE_BUS_CPU, 146 GATE_BUS_CPU,
126 GATE_SCLK_CPU, 147 GATE_SCLK_CPU,
148 CLKOUT_CMU_CPU,
149 EPLL_CON0,
150 EPLL_CON1,
151 EPLL_CON2,
152 RPLL_CON0,
153 RPLL_CON1,
154 RPLL_CON2,
127 SRC_TOP0, 155 SRC_TOP0,
128 SRC_TOP1, 156 SRC_TOP1,
129 SRC_TOP2, 157 SRC_TOP2,
@@ -140,10 +168,13 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
140 SRC_TOP10, 168 SRC_TOP10,
141 SRC_TOP11, 169 SRC_TOP11,
142 SRC_TOP12, 170 SRC_TOP12,
171 SRC_MASK_TOP2,
172 SRC_MASK_TOP7,
143 SRC_MASK_DISP10, 173 SRC_MASK_DISP10,
144 SRC_MASK_FSYS, 174 SRC_MASK_FSYS,
145 SRC_MASK_PERIC0, 175 SRC_MASK_PERIC0,
146 SRC_MASK_PERIC1, 176 SRC_MASK_PERIC1,
177 SRC_ISP,
147 DIV_TOP0, 178 DIV_TOP0,
148 DIV_TOP1, 179 DIV_TOP1,
149 DIV_TOP2, 180 DIV_TOP2,
@@ -157,25 +188,36 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
157 DIV_PERIC2, 188 DIV_PERIC2,
158 DIV_PERIC3, 189 DIV_PERIC3,
159 DIV_PERIC4, 190 DIV_PERIC4,
191 SCLK_DIV_ISP0,
192 SCLK_DIV_ISP1,
193 DIV2_RATIO0,
194 DIV4_RATIO,
160 GATE_BUS_TOP, 195 GATE_BUS_TOP,
196 GATE_BUS_GEN,
161 GATE_BUS_FSYS0, 197 GATE_BUS_FSYS0,
198 GATE_BUS_FSYS2,
162 GATE_BUS_PERIC, 199 GATE_BUS_PERIC,
163 GATE_BUS_PERIC1, 200 GATE_BUS_PERIC1,
164 GATE_BUS_PERIS0, 201 GATE_BUS_PERIS0,
165 GATE_BUS_PERIS1, 202 GATE_BUS_PERIS1,
203 GATE_BUS_NOC,
204 GATE_TOP_SCLK_ISP,
166 GATE_IP_GSCL0, 205 GATE_IP_GSCL0,
167 GATE_IP_GSCL1, 206 GATE_IP_GSCL1,
168 GATE_IP_MFC, 207 GATE_IP_MFC,
169 GATE_IP_DISP1, 208 GATE_IP_DISP1,
170 GATE_IP_G3D, 209 GATE_IP_G3D,
171 GATE_IP_GEN, 210 GATE_IP_GEN,
211 GATE_IP_FSYS,
212 GATE_IP_PERIC,
213 GATE_IP_PERIS,
172 GATE_IP_MSCL, 214 GATE_IP_MSCL,
173 GATE_TOP_SCLK_GSCL, 215 GATE_TOP_SCLK_GSCL,
174 GATE_TOP_SCLK_DISP1, 216 GATE_TOP_SCLK_DISP1,
175 GATE_TOP_SCLK_MAU, 217 GATE_TOP_SCLK_MAU,
176 GATE_TOP_SCLK_FSYS, 218 GATE_TOP_SCLK_FSYS,
177 GATE_TOP_SCLK_PERIC, 219 GATE_TOP_SCLK_PERIC,
178 SRC_CDREX, 220 TOP_SPARE2,
179 SRC_KFC, 221 SRC_KFC,
180 DIV_KFC0, 222 DIV_KFC0,
181}; 223};
@@ -216,85 +258,117 @@ static void exynos5420_clk_sleep_init(void) {}
216#endif 258#endif
217 259
218/* list of all parent clocks */ 260/* list of all parent clocks */
219PNAME(mspll_cpu_p) = { "sclk_cpll", "sclk_dpll", 261PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
220 "sclk_mpll", "sclk_spll" }; 262 "mout_sclk_mpll", "mout_sclk_spll"};
221PNAME(cpu_p) = { "mout_apll" , "mout_mspll_cpu" }; 263PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
222PNAME(kfc_p) = { "mout_kpll" , "mout_mspll_kfc" }; 264PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
223PNAME(apll_p) = { "fin_pll", "fout_apll", }; 265PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
224PNAME(bpll_p) = { "fin_pll", "fout_bpll", }; 266PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
225PNAME(cpll_p) = { "fin_pll", "fout_cpll", }; 267PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
226PNAME(dpll_p) = { "fin_pll", "fout_dpll", }; 268PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
227PNAME(epll_p) = { "fin_pll", "fout_epll", }; 269PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
228PNAME(ipll_p) = { "fin_pll", "fout_ipll", }; 270PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
229PNAME(kpll_p) = { "fin_pll", "fout_kpll", }; 271PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
230PNAME(mpll_p) = { "fin_pll", "fout_mpll", }; 272PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
231PNAME(rpll_p) = { "fin_pll", "fout_rpll", }; 273PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
232PNAME(spll_p) = { "fin_pll", "fout_spll", }; 274PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
233PNAME(vpll_p) = { "fin_pll", "fout_vpll", }; 275PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
234 276
235PNAME(group1_p) = { "sclk_cpll", "sclk_dpll", "sclk_mpll" }; 277PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
236PNAME(group2_p) = { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll", 278 "mout_sclk_mpll"};
237 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 279PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
238PNAME(group3_p) = { "sclk_rpll", "sclk_spll" }; 280 "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
239PNAME(group4_p) = { "sclk_ipll", "sclk_dpll", "sclk_mpll" }; 281 "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
240PNAME(group5_p) = { "sclk_vpll", "sclk_dpll" }; 282PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
241 283PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
242PNAME(sw_aclk66_p) = { "dout_aclk66", "sclk_spll" }; 284PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
243PNAME(aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66" }; 285
244 286PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
245PNAME(sw_aclk200_fsys_p) = { "dout_aclk200_fsys", "sclk_spll"}; 287PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
246PNAME(user_aclk200_fsys_p) = { "fin_pll", "mout_sw_aclk200_fsys" }; 288PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
247 289PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
248PNAME(sw_aclk200_fsys2_p) = { "dout_aclk200_fsys2", "sclk_spll"}; 290
249PNAME(user_aclk200_fsys2_p) = { "fin_pll", "mout_sw_aclk200_fsys2" }; 291PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
250 292PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
251PNAME(sw_aclk200_p) = { "dout_aclk200", "sclk_spll"}; 293PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
252PNAME(aclk200_disp1_p) = { "fin_pll", "mout_sw_aclk200" }; 294PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
253 295
254PNAME(sw_aclk400_mscl_p) = { "dout_aclk400_mscl", "sclk_spll"}; 296PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
255PNAME(user_aclk400_mscl_p) = { "fin_pll", "mout_sw_aclk400_mscl" }; 297PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
256 298PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
257PNAME(sw_aclk333_p) = { "dout_aclk333", "sclk_spll"}; 299PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
258PNAME(user_aclk333_p) = { "fin_pll", "mout_sw_aclk333" }; 300
259 301PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
260PNAME(sw_aclk166_p) = { "dout_aclk166", "sclk_spll"}; 302PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
261PNAME(user_aclk166_p) = { "fin_pll", "mout_sw_aclk166" }; 303PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
262 304
263PNAME(sw_aclk266_p) = { "dout_aclk266", "sclk_spll"}; 305PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
264PNAME(user_aclk266_p) = { "fin_pll", "mout_sw_aclk266" }; 306PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
265 307
266PNAME(sw_aclk333_432_gscl_p) = { "dout_aclk333_432_gscl", "sclk_spll"}; 308PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
267PNAME(user_aclk333_432_gscl_p) = { "fin_pll", "mout_sw_aclk333_432_gscl" }; 309 "mout_sclk_spll"};
268 310PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
269PNAME(sw_aclk300_gscl_p) = { "dout_aclk300_gscl", "sclk_spll"}; 311
270PNAME(user_aclk300_gscl_p) = { "fin_pll", "mout_sw_aclk300_gscl" }; 312PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
271 313PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
272PNAME(sw_aclk300_disp1_p) = { "dout_aclk300_disp1", "sclk_spll"}; 314
273PNAME(user_aclk300_disp1_p) = { "fin_pll", "mout_sw_aclk300_disp1" }; 315PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
274 316PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
275PNAME(sw_aclk300_jpeg_p) = { "dout_aclk300_jpeg", "sclk_spll"}; 317
276PNAME(user_aclk300_jpeg_p) = { "fin_pll", "mout_sw_aclk300_jpeg" }; 318PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
277 319PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
278PNAME(sw_aclk_g3d_p) = { "dout_aclk_g3d", "sclk_spll"}; 320
279PNAME(user_aclk_g3d_p) = { "fin_pll", "mout_sw_aclk_g3d" }; 321PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
280 322PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
281PNAME(sw_aclk266_g2d_p) = { "dout_aclk266_g2d", "sclk_spll"}; 323
282PNAME(user_aclk266_g2d_p) = { "fin_pll", "mout_sw_aclk266_g2d" }; 324PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
283 325PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
284PNAME(sw_aclk333_g2d_p) = { "dout_aclk333_g2d", "sclk_spll"}; 326
285PNAME(user_aclk333_g2d_p) = { "fin_pll", "mout_sw_aclk333_g2d" }; 327PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
286 328PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
287PNAME(audio0_p) = { "fin_pll", "cdclk0", "sclk_dpll", "sclk_mpll", 329PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
288 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 330
289PNAME(audio1_p) = { "fin_pll", "cdclk1", "sclk_dpll", "sclk_mpll", 331PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
290 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 332PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
291PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll", 333
292 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 334PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
293PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2", 335PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
294 "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 336
295PNAME(hdmi_p) = { "dout_hdmi_pixel", "sclk_hdmiphy" }; 337PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
296PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll", 338PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
297 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 339PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
340PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
341
342PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
343PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
344
345PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
346PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
347
348PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
349PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
350
351PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
352PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
353
354PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
355 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
356 "mout_sclk_epll", "mout_sclk_rpll"};
357PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
358 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
359 "mout_sclk_epll", "mout_sclk_rpll"};
360PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
361 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
362 "mout_sclk_epll", "mout_sclk_rpll"};
363PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
364 "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
365 "mout_sclk_epll", "mout_sclk_rpll"};
366PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
367PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
368 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
369 "mout_sclk_epll", "mout_sclk_rpll"};
370PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
371 "mout_sclk_mpll", "mout_sclk_spll"};
298 372
299/* fixed rate clocks generated outside the soc */ 373/* fixed rate clocks generated outside the soc */
300static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { 374static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
@@ -311,145 +385,219 @@ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata =
311}; 385};
312 386
313static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { 387static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
314 FFACTOR(0, "sclk_hsic_12m", "fin_pll", 1, 2, 0), 388 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
389 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
315}; 390};
316 391
317static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 392static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
318 MUX(0, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2), 393 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
319 MUX(0, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2), 394 SRC_TOP7, 4, 1),
320 MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1), 395 MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
321 MUX(0, "mout_cpu", cpu_p, SRC_CPU, 16, 1), 396 MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
322 MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1), 397 MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
323 MUX(0, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1),
324 398
325 MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1), 399 MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
400 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
401 MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
402 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
326 403
327 MUX_A(0, "mout_aclk400_mscl", group1_p, 404 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
405
406 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
407 MUX_A(0, "mout_aclk400_mscl", mout_group1_p,
328 SRC_TOP0, 4, 2, "aclk400_mscl"), 408 SRC_TOP0, 4, 2, "aclk400_mscl"),
329 MUX(0, "mout_aclk200", group1_p, SRC_TOP0, 8, 2), 409 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
330 MUX(0, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2), 410 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
331 MUX(0, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2), 411 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
332 412 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
333 MUX(0, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2), 413 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
334 MUX(0, "mout_aclk66", group1_p, SRC_TOP1, 8, 2), 414 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
335 MUX(0, "mout_aclk266", group1_p, SRC_TOP1, 20, 2), 415
336 MUX(0, "mout_aclk166", group1_p, SRC_TOP1, 24, 2), 416 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
337 MUX(0, "mout_aclk333", group1_p, SRC_TOP1, 28, 2), 417 MUX(0, "mout_aclk333_432_isp", mout_group4_p,
338 418 SRC_TOP1, 4, 2),
339 MUX(0, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2), 419 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
340 MUX(0, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2), 420 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
341 MUX(0, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1), 421 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
342 MUX(0, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2), 422 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
343 MUX(0, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2), 423 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
344 MUX(0, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2), 424
345 425 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
346 MUX(0, "mout_user_aclk400_mscl", user_aclk400_mscl_p, 426 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
427 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
428 MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
429 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
430 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
431 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
432
433 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
434 SRC_TOP3, 0, 1),
435 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
347 SRC_TOP3, 4, 1), 436 SRC_TOP3, 4, 1),
348 MUX_A(0, "mout_aclk200_disp1", aclk200_disp1_p, 437 MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p,
349 SRC_TOP3, 8, 1, "aclk200_disp1"), 438 SRC_TOP3, 8, 1),
350 MUX(0, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p, 439 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
351 SRC_TOP3, 12, 1), 440 SRC_TOP3, 12, 1),
352 MUX(0, "mout_user_aclk200_fsys", user_aclk200_fsys_p, 441 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
442 SRC_TOP3, 16, 1),
443 MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
444 SRC_TOP3, 20, 1),
445 MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
446 SRC_TOP3, 24, 1),
447 MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
353 SRC_TOP3, 28, 1), 448 SRC_TOP3, 28, 1),
354 449
355 MUX(0, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p, 450 MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
356 SRC_TOP4, 0, 1), 451 SRC_TOP4, 0, 1),
357 MUX(0, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1), 452 MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
358 MUX(0, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1), 453 SRC_TOP4, 4, 1),
359 MUX(0, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1), 454 MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
360 MUX(0, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1), 455 SRC_TOP4, 8, 1),
361 456 MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
362 MUX(0, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1), 457 SRC_TOP4, 12, 1),
363 MUX(0, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1), 458 MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
364 MUX(0, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1), 459 SRC_TOP4, 16, 1),
365 MUX_A(0, "mout_user_aclk_g3d", user_aclk_g3d_p, 460 MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
366 SRC_TOP5, 16, 1, "aclkg3d"), 461 MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
367 MUX(0, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p, 462 MUX(0, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1),
463
464 MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
465 SRC_TOP5, 0, 1),
466 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
467 SRC_TOP5, 4, 1),
468 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
469 SRC_TOP5, 8, 1),
470 MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
471 SRC_TOP5, 12, 1),
472 MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
473 SRC_TOP5, 16, 1),
474 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
368 SRC_TOP5, 20, 1), 475 SRC_TOP5, 20, 1),
369 MUX(0, "mout_user_aclk300_disp1", user_aclk300_disp1_p, 476 MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p,
370 SRC_TOP5, 24, 1), 477 SRC_TOP5, 24, 1),
371 MUX(0, "mout_user_aclk300_gscl", user_aclk300_gscl_p, 478 MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
372 SRC_TOP5, 28, 1), 479 SRC_TOP5, 28, 1),
373 480
374 MUX(0, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1), 481 MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
375 MUX(0, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1), 482 MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
376 MUX(0, "sclk_spll", spll_p, SRC_TOP6, 8, 1), 483 MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
377 MUX(0, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1), 484 MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
378 MUX(0, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1), 485 MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
379 MUX(0, "sclk_epll", epll_p, SRC_TOP6, 20, 1), 486 MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
380 MUX(0, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1), 487 MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
381 MUX(0, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1), 488 MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
382 489
383 MUX(0, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1), 490 MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
384 MUX(0, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1), 491 SRC_TOP10, 0, 1),
385 MUX(0, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p, 492 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
493 SRC_TOP10, 4, 1),
494 MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1),
495 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
386 SRC_TOP10, 12, 1), 496 SRC_TOP10, 12, 1),
387 MUX(0, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1), 497 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
388 498 SRC_TOP10, 16, 1),
389 MUX(0, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p, 499 MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
500 SRC_TOP10, 20, 1),
501 MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
502 SRC_TOP10, 24, 1),
503 MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
504 SRC_TOP10, 28, 1),
505
506 MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
390 SRC_TOP11, 0, 1), 507 SRC_TOP11, 0, 1),
391 MUX(0, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1), 508 MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
392 MUX(0, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1), 509 SRC_TOP11, 4, 1),
393 MUX(0, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1), 510 MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
394 MUX(0, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1), 511 MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
395 512 SRC_TOP11, 12, 1),
396 MUX(0, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1), 513 MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
397 MUX(0, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1), 514 MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
398 MUX(0, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1), 515 MUX(0, "mout_sw_aclk333", mout_sw_aclk333_p, SRC_TOP11, 28, 1),
399 MUX(0, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1), 516
400 MUX(0, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p, 517 MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
518 SRC_TOP12, 4, 1),
519 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
520 SRC_TOP12, 8, 1),
521 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
522 SRC_TOP12, 12, 1),
523 MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
524 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
525 SRC_TOP12, 20, 1),
526 MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p,
401 SRC_TOP12, 24, 1), 527 SRC_TOP12, 24, 1),
402 MUX(0, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 528 MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
529 SRC_TOP12, 28, 1),
403 530
404 /* DISP1 Block */ 531 /* DISP1 Block */
405 MUX(0, "mout_fimd1", group3_p, SRC_DISP10, 4, 1), 532 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
406 MUX(0, "mout_mipi1", group2_p, SRC_DISP10, 16, 3), 533 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
407 MUX(0, "mout_dp1", group2_p, SRC_DISP10, 20, 3), 534 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
408 MUX(0, "mout_pixel", group2_p, SRC_DISP10, 24, 3), 535 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
409 MUX(CLK_MOUT_HDMI, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1), 536 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
537 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
538
539 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
540 TOP_SPARE2, 4, 1),
541 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
410 542
411 /* MAU Block */ 543 /* MAU Block */
412 MUX(0, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3), 544 MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
413 545
414 /* FSYS Block */ 546 /* FSYS Block */
415 MUX(0, "mout_usbd301", group2_p, SRC_FSYS, 4, 3), 547 MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
416 MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 8, 3), 548 MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
417 MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 12, 3), 549 MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
418 MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 16, 3), 550 MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
419 MUX(0, "mout_usbd300", group2_p, SRC_FSYS, 20, 3), 551 MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
420 MUX(0, "mout_unipro", group2_p, SRC_FSYS, 24, 3), 552 MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
553 MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
421 554
422 /* PERIC Block */ 555 /* PERIC Block */
423 MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 4, 3), 556 MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
424 MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 8, 3), 557 MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
425 MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 12, 3), 558 MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
426 MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 16, 3), 559 MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
427 MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 3), 560 MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
428 MUX(0, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3), 561 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
429 MUX(0, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3), 562 MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
430 MUX(0, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3), 563 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
431 MUX(0, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3), 564 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
432 MUX(0, "mout_spi0", group2_p, SRC_PERIC1, 20, 3), 565 MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
433 MUX(0, "mout_spi1", group2_p, SRC_PERIC1, 24, 3), 566 MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
434 MUX(0, "mout_spi2", group2_p, SRC_PERIC1, 28, 3), 567 MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
568
569 /* ISP Block */
570 MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
571 MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
572 MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
573 MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
574 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
435}; 575};
436 576
437static struct samsung_div_clock exynos5420_div_clks[] __initdata = { 577static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
438 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 578 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
439 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 579 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
440 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 580 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
441 DIV(0, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3), 581 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
442 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 582 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
443 583
584 DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
444 DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), 585 DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
445 DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), 586 DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
446 DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), 587 DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
588 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll",
589 DIV_TOP0, 16, 3),
590 DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3),
447 DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), 591 DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
448 DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), 592 DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
449 593
450 DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", 594 DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
451 DIV_TOP1, 0, 3), 595 DIV_TOP1, 0, 3),
596 DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp",
597 DIV_TOP1, 4, 3),
452 DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), 598 DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
599 DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",
600 DIV_TOP1, 16, 3),
453 DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), 601 DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
454 DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), 602 DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
455 DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), 603 DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
@@ -458,15 +606,16 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
458 DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), 606 DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
459 DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), 607 DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
460 DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), 608 DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
461 DIV_A(0, "dout_aclk300_disp1", "mout_aclk300_disp1", 609 DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3),
462 DIV_TOP2, 24, 3, "aclk300_disp1"),
463 DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), 610 DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
464 611
465 /* DISP1 Block */ 612 /* DISP1 Block */
466 DIV(0, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), 613 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
467 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 614 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
468 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 615 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
469 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 616 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
617 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
618 DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3),
470 619
471 /* Audio Block */ 620 /* Audio Block */
472 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 621 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
@@ -484,6 +633,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
484 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 633 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
485 634
486 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 635 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
636 DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
487 637
488 /* UART and PWM */ 638 /* UART and PWM */
489 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 639 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
@@ -497,6 +647,9 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
497 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 647 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
498 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 648 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
499 649
650 /* Mfc Block */
651 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
652
500 /* PCM */ 653 /* PCM */
501 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 654 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
502 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 655 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
@@ -509,15 +662,43 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
509 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 662 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
510 663
511 /* SPI Pre-Ratio */ 664 /* SPI Pre-Ratio */
512 DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8), 665 DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
513 DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8), 666 DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
514 DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), 667 DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
668
669 /* GSCL Block */
670 DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
671 DIV2_RATIO0, 4, 2),
672 DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
673
674 /* MSCL Block */
675 DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
676
677 /* PSGEN */
678 DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
679 DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
680
681 /* ISP Block */
682 DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
683 DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
684 DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
685 DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
686 DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
687 DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
688 DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
689 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
690 CLK_SET_RATE_PARENT, 0),
691 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
692 CLK_SET_RATE_PARENT, 0),
515}; 693};
516 694
517static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 695static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
518 /* TODO: Re-verify the CG bits for all the gate clocks */ 696 /* G2D */
519 GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, 697 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
520 "mct"), 698 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
699 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
700 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
701 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
521 702
522 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 703 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
523 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), 704 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
@@ -530,20 +711,42 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
530 GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0), 711 GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
531 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 712 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
532 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 713 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
714 GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
715 GATE_BUS_TOP, 5, 0, 0),
533 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 716 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
534 GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0), 717 GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
535 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 718 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
536 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 719 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
537 GATE(0, "pclk66_gpio", "mout_sw_aclk66", 720 GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
721 GATE_BUS_TOP, 8, 0, 0),
722 GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
538 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 723 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
539 GATE(0, "aclk66_psgen", "mout_aclk66_psgen", 724 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
540 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 725 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
541 GATE(0, "aclk66_peric", "mout_aclk66_peric", 726 GATE(CLK_ACLK66_PERIC, "aclk66_peric", "mout_user_aclk66_peric",
542 GATE_BUS_TOP, 11, 0, 0), 727 GATE_BUS_TOP, 11, CLK_IGNORE_UNUSED, 0),
728 GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
729 GATE_BUS_TOP, 13, 0, 0),
543 GATE(0, "aclk166", "mout_user_aclk166", 730 GATE(0, "aclk166", "mout_user_aclk166",
544 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 731 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
545 GATE(0, "aclk333", "mout_aclk333", 732 GATE(0, "aclk333", "mout_aclk333",
546 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), 733 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
734 GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
735 GATE_BUS_TOP, 16, 0, 0),
736 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
737 GATE_BUS_TOP, 17, 0, 0),
738 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
739 GATE_BUS_TOP, 18, 0, 0),
740 GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
741 GATE_BUS_TOP, 28, 0, 0),
742 GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
743 GATE_BUS_TOP, 29, 0, 0),
744
745 GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
746 SRC_MASK_TOP2, 24, 0, 0),
747
748 GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
749 SRC_MASK_TOP7, 20, 0, 0),
547 750
548 /* sclk */ 751 /* sclk */
549 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 752 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
@@ -554,11 +757,11 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
554 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 757 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
555 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 758 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
556 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 759 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
557 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_pre_spi0", 760 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
558 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 761 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
559 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_pre_spi1", 762 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
560 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 763 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
561 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_pre_spi2", 764 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
562 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 765 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
563 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 766 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
564 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 767 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
@@ -588,161 +791,188 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
588 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 791 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
589 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 792 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
590 793
591 GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro",
592 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
593
594 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "aclK333_432_gscl",
595 GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0),
596 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "aclk333_432_gscl",
597 GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),
598
599 /* Display */ 794 /* Display */
600 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 795 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
601 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 796 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
602 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 797 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
603 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 798 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
604 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 799 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
605 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), 800 GATE_TOP_SCLK_DISP1, 9, 0, 0),
606 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 801 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
607 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 802 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
608 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 803 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
609 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 804 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
610 805
611 /* Maudio Block */ 806 /* Maudio Block */
612 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 807 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
613 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 808 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
614 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 809 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
615 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 810 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
616 /* FSYS */ 811
812 /* FSYS Block */
617 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 813 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
618 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 814 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
619 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 815 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
620 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 816 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
621 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0), 817 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
622 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0), 818 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
623 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0), 819 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
624 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0), 820 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
625 GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 821 GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
626 GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0), 822 GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
627 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0), 823 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
628 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0), 824 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
629 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0), 825 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
630 826 GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
631 /* UART */ 827 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
632 GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
633 GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
634 GATE_A(CLK_UART2, "uart2", "aclk66_peric",
635 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
636 GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
637 /* I2C */
638 GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
639 GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
640 GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
641 GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
642 GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
643 GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
644 GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
645 GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
646 GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0,
647 0),
648 GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
649 /* SPI */
650 GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
651 GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
652 GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
653 GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
654 /* I2S */
655 GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
656 GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
657 /* PCM */
658 GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
659 GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
660 /* PWM */
661 GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
662 /* SPDIF */
663 GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
664 828
665 GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0), 829 /* PERIC Block */
666 GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0), 830 GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_IP_PERIC, 0, 0, 0),
667 GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0), 831 GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_IP_PERIC, 1, 0, 0),
832 GATE(CLK_UART2, "uart2", "aclk66_peric", GATE_IP_PERIC, 2, 0, 0),
833 GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_IP_PERIC, 3, 0, 0),
834 GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_IP_PERIC, 6, 0, 0),
835 GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_IP_PERIC, 7, 0, 0),
836 GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_IP_PERIC, 8, 0, 0),
837 GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_IP_PERIC, 9, 0, 0),
838 GATE(CLK_USI0, "usi0", "aclk66_peric", GATE_IP_PERIC, 10, 0, 0),
839 GATE(CLK_USI1, "usi1", "aclk66_peric", GATE_IP_PERIC, 11, 0, 0),
840 GATE(CLK_USI2, "usi2", "aclk66_peric", GATE_IP_PERIC, 12, 0, 0),
841 GATE(CLK_USI3, "usi3", "aclk66_peric", GATE_IP_PERIC, 13, 0, 0),
842 GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_IP_PERIC, 14, 0, 0),
843 GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_IP_PERIC, 15, 0, 0),
844 GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_IP_PERIC, 16, 0, 0),
845 GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_IP_PERIC, 17, 0, 0),
846 GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_IP_PERIC, 18, 0, 0),
847 GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_IP_PERIC, 20, 0, 0),
848 GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_IP_PERIC, 21, 0, 0),
849 GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_IP_PERIC, 22, 0, 0),
850 GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_IP_PERIC, 23, 0, 0),
851 GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_IP_PERIC, 24, 0, 0),
852 GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_IP_PERIC, 26, 0, 0),
853 GATE(CLK_USI4, "usi4", "aclk66_peric", GATE_IP_PERIC, 28, 0, 0),
854 GATE(CLK_USI5, "usi5", "aclk66_peric", GATE_IP_PERIC, 30, 0, 0),
855 GATE(CLK_USI6, "usi6", "aclk66_peric", GATE_IP_PERIC, 31, 0, 0),
668 856
857 GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
858
859 /* PERIS Block */
669 GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 860 GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
670 GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0), 861 GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
671 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 862 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
672 GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0), 863 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
673 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0), 864 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
674 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0), 865 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
675 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0), 866 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
676 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0), 867 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
677 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0), 868 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
678 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0), 869 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
679 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0), 870 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
680 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0), 871 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
681 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0), 872 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
682 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0), 873 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
683 874 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
684 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 875 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
685 0), 876 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
877 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
878 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
879 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
880
686 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 881 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
687 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0), 882
688 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0), 883 /* GEN Block */
689 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0), 884 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
690 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0), 885 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
886 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
887 GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
888 GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
889 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
890 GATE_IP_GEN, 6, 0, 0),
891 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
892 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
893 GATE_IP_GEN, 9, 0, 0),
894
895 /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
896 GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
897 GATE_BUS_GEN, 28, 0, 0),
898 GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
899
900 /* GSCL Block */
901 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
902 GATE_TOP_SCLK_GSCL, 6, 0, 0),
903 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
904 GATE_TOP_SCLK_GSCL, 7, 0, 0),
691 905
692 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 906 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
693 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 907 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
694 GATE(CLK_CLK_3AA, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0), 908 GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
695 909 GATE_IP_GSCL0, 4, 0, 0),
696 GATE(CLK_SMMU_3AA, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 910 GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
697 0), 911 GATE_IP_GSCL0, 5, 0, 0),
698 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "aclk333_432_gscl", 912 GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
913 GATE_IP_GSCL0, 6, 0, 0),
914
915 GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
916 GATE_IP_GSCL1, 2, 0, 0),
917 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
699 GATE_IP_GSCL1, 3, 0, 0), 918 GATE_IP_GSCL1, 3, 0, 0),
700 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "aclk333_432_gscl", 919 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
701 GATE_IP_GSCL1, 4, 0, 0), 920 GATE_IP_GSCL1, 4, 0, 0),
702 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 921 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
703 0), 922 GATE_IP_GSCL1, 6, 0, 0),
704 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 923 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
705 0), 924 GATE_IP_GSCL1, 7, 0, 0),
706 GATE(CLK_GSCL_WA, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0), 925 GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0),
707 GATE(CLK_GSCL_WB, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0), 926 GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0),
708 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "aclk333_432_gscl", 927 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
709 GATE_IP_GSCL1, 16, 0, 0), 928 GATE_IP_GSCL1, 16, 0, 0),
710 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 929 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
711 GATE_IP_GSCL1, 17, 0, 0), 930 GATE_IP_GSCL1, 17, 0, 0),
712 931
932 /* MSCL Block */
933 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
934 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
935 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
936 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
937 GATE_IP_MSCL, 8, 0, 0),
938 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
939 GATE_IP_MSCL, 9, 0, 0),
940 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
941 GATE_IP_MSCL, 10, 0, 0),
942
713 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 943 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
714 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 944 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
715 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 945 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
716 GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0), 946 GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
717 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 947 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
718 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 948 GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
719 0), 949 GATE_IP_DISP1, 7, 0, 0),
950 GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
951 GATE_IP_DISP1, 8, 0, 0),
952 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
953 GATE_IP_DISP1, 9, 0, 0),
954
955 /* ISP */
956 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
957 GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
958 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
959 GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
960 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
961 GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
962 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
963 GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
964 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
965 GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
966 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
967 GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
968 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
969 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
720 970
721 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 971 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
722 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), 972 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
723 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), 973 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
724 974
725 GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0), 975 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
726
727 GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
728 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
729 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
730 GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
731 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
732 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
733 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
734
735 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
736 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
737 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
738 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0,
739 0),
740 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0,
741 0),
742 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0,
743 0),
744 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
745 0),
746}; 976};
747 977
748static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = { 978static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 41c1461d2f58..49629c71c9e7 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -54,14 +54,19 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
54 struct samsung_clk_provider *ctx; 54 struct samsung_clk_provider *ctx;
55 struct clk **clk_table; 55 struct clk **clk_table;
56 int ret; 56 int ret;
57 int i;
58
57 ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL); 59 ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
58 if (!ctx) 60 if (!ctx)
59 panic("could not allocate clock provider context.\n"); 61 panic("could not allocate clock provider context.\n");
60 62
61 clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); 63 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
62 if (!clk_table) 64 if (!clk_table)
63 panic("could not allocate clock lookup table\n"); 65 panic("could not allocate clock lookup table\n");
64 66
67 for (i = 0; i < nr_clks; ++i)
68 clk_table[i] = ERR_PTR(-ENOENT);
69
65 ctx->reg_base = base; 70 ctx->reg_base = base;
66 ctx->clk_data.clks = clk_table; 71 ctx->clk_data.clks = clk_table;
67 ctx->clk_data.clk_num = nr_clks; 72 ctx->clk_data.clk_num = nr_clks;
@@ -288,7 +293,7 @@ void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
288 for_each_matching_node_and_match(clk_np, clk_matches, &match) { 293 for_each_matching_node_and_match(clk_np, clk_matches, &match) {
289 if (of_property_read_u32(clk_np, "clock-frequency", &freq)) 294 if (of_property_read_u32(clk_np, "clock-frequency", &freq))
290 continue; 295 continue;
291 fixed_rate_clk[(u32)match->data].fixed_rate = freq; 296 fixed_rate_clk[(unsigned long)match->data].fixed_rate = freq;
292 } 297 }
293 samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk); 298 samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
294} 299}
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 75aff336dfb0..1106ca540a96 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -33,6 +33,7 @@
33#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */ 33#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
34#define CLK_MOUT_CORE 19 34#define CLK_MOUT_CORE 19
35#define CLK_MOUT_APLL 20 35#define CLK_MOUT_APLL 20
36#define CLK_SCLK_HDMIPHY 22
36 37
37/* gate for special clocks (sclk) */ 38/* gate for special clocks (sclk) */
38#define CLK_SCLK_FIMC0 128 39#define CLK_SCLK_FIMC0 128
@@ -181,7 +182,6 @@
181#define CLK_KEYIF 347 182#define CLK_KEYIF 347
182#define CLK_AUDSS 348 183#define CLK_AUDSS 348
183#define CLK_MIPI_HSI 349 /* Exynos4210 only */ 184#define CLK_MIPI_HSI 349 /* Exynos4210 only */
184#define CLK_MDMA2 350 /* Exynos4210 only */
185#define CLK_PIXELASYNCM0 351 185#define CLK_PIXELASYNCM0 351
186#define CLK_PIXELASYNCM1 352 186#define CLK_PIXELASYNCM1 352
187#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */ 187#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
index 922f2dca9bf0..415d447e6e29 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -150,11 +150,14 @@
150#define CLK_G2D 345 150#define CLK_G2D 345
151#define CLK_MDMA0 346 151#define CLK_MDMA0 346
152#define CLK_SMMU_MDMA0 347 152#define CLK_SMMU_MDMA0 347
153#define CLK_SSS 348
154#define CLK_G3D 349
153 155
154/* mux clocks */ 156/* mux clocks */
155#define CLK_MOUT_HDMI 1024 157#define CLK_MOUT_HDMI 1024
158#define CLK_MOUT_GPLL 1025
156 159
157/* must be greater than maximal clock id */ 160/* must be greater than maximal clock id */
158#define CLK_NR_CLKS 1025 161#define CLK_NR_CLKS 1026
159 162
160#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ 163#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 5eefd8813f02..7dd1cc3b5c57 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -58,6 +58,9 @@
58#define CLK_SCLK_GSCL_WA 156 58#define CLK_SCLK_GSCL_WA 156
59#define CLK_SCLK_GSCL_WB 157 59#define CLK_SCLK_GSCL_WB 157
60#define CLK_SCLK_HDMIPHY 158 60#define CLK_SCLK_HDMIPHY 158
61#define CLK_MAU_EPLL 159
62#define CLK_SCLK_HSIC_12M 160
63#define CLK_SCLK_MPHY_IXTAL24 161
61 64
62/* gate clocks */ 65/* gate clocks */
63#define CLK_ACLK66_PERIC 256 66#define CLK_ACLK66_PERIC 256
@@ -69,10 +72,10 @@
69#define CLK_I2C1 262 72#define CLK_I2C1 262
70#define CLK_I2C2 263 73#define CLK_I2C2 263
71#define CLK_I2C3 264 74#define CLK_I2C3 264
72#define CLK_I2C4 265 75#define CLK_USI0 265
73#define CLK_I2C5 266 76#define CLK_USI1 266
74#define CLK_I2C6 267 77#define CLK_USI2 267
75#define CLK_I2C7 268 78#define CLK_USI3 268
76#define CLK_I2C_HDMI 269 79#define CLK_I2C_HDMI 269
77#define CLK_TSADC 270 80#define CLK_TSADC 270
78#define CLK_SPI0 271 81#define CLK_SPI0 271
@@ -85,9 +88,9 @@
85#define CLK_PCM2 278 88#define CLK_PCM2 278
86#define CLK_PWM 279 89#define CLK_PWM 279
87#define CLK_SPDIF 280 90#define CLK_SPDIF 280
88#define CLK_I2C8 281 91#define CLK_USI4 281
89#define CLK_I2C9 282 92#define CLK_USI5 282
90#define CLK_I2C10 283 93#define CLK_USI6 283
91#define CLK_ACLK66_PSGEN 300 94#define CLK_ACLK66_PSGEN 300
92#define CLK_CHIPID 301 95#define CLK_CHIPID 301
93#define CLK_SYSREG 302 96#define CLK_SYSREG 302
@@ -140,7 +143,8 @@
140#define CLK_HDMI 413 143#define CLK_HDMI 413
141#define CLK_ACLK300_DISP1 420 144#define CLK_ACLK300_DISP1 420
142#define CLK_FIMD1 421 145#define CLK_FIMD1 421
143#define CLK_SMMU_FIMD1 422 146#define CLK_SMMU_FIMD1M0 422
147#define CLK_SMMU_FIMD1M1 423
144#define CLK_ACLK166 430 148#define CLK_ACLK166 430
145#define CLK_MIXER 431 149#define CLK_MIXER 431
146#define CLK_ACLK266 440 150#define CLK_ACLK266 440
@@ -152,6 +156,7 @@
152#define CLK_JPEG 451 156#define CLK_JPEG 451
153#define CLK_JPEG2 452 157#define CLK_JPEG2 452
154#define CLK_SMMU_JPEG 453 158#define CLK_SMMU_JPEG 453
159#define CLK_SMMU_JPEG2 454
155#define CLK_ACLK300_GSCL 460 160#define CLK_ACLK300_GSCL 460
156#define CLK_SMMU_GSCL0 461 161#define CLK_SMMU_GSCL0 461
157#define CLK_SMMU_GSCL1 462 162#define CLK_SMMU_GSCL1 462
@@ -159,7 +164,7 @@
159#define CLK_GSCL_WB 464 164#define CLK_GSCL_WB 464
160#define CLK_GSCL0 465 165#define CLK_GSCL0 465
161#define CLK_GSCL1 466 166#define CLK_GSCL1 466
162#define CLK_CLK_3AA 467 167#define CLK_FIMC_3AA 467
163#define CLK_ACLK266_G2D 470 168#define CLK_ACLK266_G2D 470
164#define CLK_SSS 471 169#define CLK_SSS 471
165#define CLK_SLIM_SSS 472 170#define CLK_SLIM_SSS 472
@@ -172,12 +177,28 @@
172#define CLK_SMMU_FIMCL1 493 177#define CLK_SMMU_FIMCL1 493
173#define CLK_SMMU_FIMCL3 494 178#define CLK_SMMU_FIMCL3 494
174#define CLK_FIMC_LITE3 495 179#define CLK_FIMC_LITE3 495
180#define CLK_FIMC_LITE0 496
181#define CLK_FIMC_LITE1 497
175#define CLK_ACLK_G3D 500 182#define CLK_ACLK_G3D 500
176#define CLK_G3D 501 183#define CLK_G3D 501
177#define CLK_SMMU_MIXER 502 184#define CLK_SMMU_MIXER 502
185#define CLK_SMMU_G2D 503
186#define CLK_SMMU_MDMA0 504
187#define CLK_MC 505
188#define CLK_TOP_RTC 506
189#define CLK_SCLK_UART_ISP 510
190#define CLK_SCLK_SPI0_ISP 511
191#define CLK_SCLK_SPI1_ISP 512
192#define CLK_SCLK_PWM_ISP 513
193#define CLK_SCLK_ISP_SENSOR0 514
194#define CLK_SCLK_ISP_SENSOR1 515
195#define CLK_SCLK_ISP_SENSOR2 516
178 196
179/* mux clocks */ 197/* mux clocks */
180#define CLK_MOUT_HDMI 640 198#define CLK_MOUT_HDMI 640
199#define CLK_MOUT_G3D 641
200#define CLK_MOUT_VPLL 642
201#define CLK_MOUT_MAUDIO0 643
181 202
182/* divider clocks */ 203/* divider clocks */
183#define CLK_DOUT_PIXEL 768 204#define CLK_DOUT_PIXEL 768
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-03 09:58:18 -0400