Merge branch 'for_3.16/clk_fixes_non_critical' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into v3.16-next/clk-samsung

Pull Samsung clock non-critical fixes from Tomasz Figa:

"This pull requests contains a number of non-critical fixes for Samsung clock
framework and drivers, including:

1) a series of fixes for Exynos5420 to correct clock definitions and make the
driver closer to the documentation,

2) several missing clocks and clock IDs added to Exynos4, Exynos5250 and
Exynos5420 drivers,

3) fix for incorrect initialization of clock table with NULL,

4) compiler warning fix."

Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

8 files changed, 608 insertions, 335 deletions

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index c3a9a66c5767..67ba2c56fa8e 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -549,7 +549,7 @@
                 #size-cells = <0>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c4_hs_bus>;
-                clocks = <&clock CLK_I2C4>;
+                clocks = <&clock CLK_USI0>;
                 clock-names = "hsi2c";
                 status = "disabled";
         };
@@ -562,7 +562,7 @@
                 #size-cells = <0>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c5_hs_bus>;
-                clocks = <&clock CLK_I2C5>;
+                clocks = <&clock CLK_USI1>;
                 clock-names = "hsi2c";
                 status = "disabled";
         };
@@ -575,7 +575,7 @@
                 #size-cells = <0>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c6_hs_bus>;
-                clocks = <&clock CLK_I2C6>;
+                clocks = <&clock CLK_USI2>;
                 clock-names = "hsi2c";
                 status = "disabled";
         };
@@ -588,7 +588,7 @@
                 #size-cells = <0>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c7_hs_bus>;
-                clocks = <&clock CLK_I2C7>;
+                clocks = <&clock CLK_USI3>;
                 clock-names = "hsi2c";
                 status = "disabled";
         };
@@ -601,7 +601,7 @@
                 #size-cells = <0>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c8_hs_bus>;
-                clocks = <&clock CLK_I2C8>;
+                clocks = <&clock CLK_USI4>;
                 clock-names = "hsi2c";
                 status = "disabled";
         };
@@ -614,7 +614,7 @@
                 #size-cells = <0>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c9_hs_bus>;
-                clocks = <&clock CLK_I2C9>;
+                clocks = <&clock CLK_USI5>;
                 clock-names = "hsi2c";
                 status = "disabled";
         };
@@ -627,7 +627,7 @@
                 #size-cells = <0>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2c10_hs_bus>;
-                clocks = <&clock CLK_I2C10>;
+                clocks = <&clock CLK_USI6>;
                 clock-names = "hsi2c";
                 status = "disabled";
         };
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 57ed5a8fb052..c4df294bb7fb 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -428,7 +428,7 @@ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata
 /* fixed rate clocks generated inside the soc */
 static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
         FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
-        FRATE(0, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
+        FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
         FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
 };
 
@@ -903,7 +903,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
         GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
         GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
         GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
-        GATE(CLK_MDMA2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
+        GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
         GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
                 0),
         GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index e549e862524a..88488596c00b 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -37,6 +37,7 @@
 #define VPLL_CON0               0x10140
 #define GPLL_CON0               0x10150
 #define SRC_TOP0                0x10210
+#define SRC_TOP1                0x10214
 #define SRC_TOP2                0x10218
 #define SRC_TOP3                0x1021c
 #define SRC_GSCL                0x10220
@@ -71,6 +72,7 @@
 #define GATE_IP_GSCL            0x10920
 #define GATE_IP_DISP1           0x10928
 #define GATE_IP_MFC             0x1092c
+#define GATE_IP_G3D             0x10930
 #define GATE_IP_GEN             0x10934
 #define GATE_IP_FSYS            0x10944
 #define GATE_IP_PERIC           0x10950
@@ -100,6 +102,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
         DIV_CPU0,
         SRC_CORE1,
         SRC_TOP0,
+        SRC_TOP1,
         SRC_TOP2,
         SRC_TOP3,
         SRC_GSCL,
@@ -133,6 +136,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
         DIV_PERIC5,
         GATE_IP_GSCL,
         GATE_IP_MFC,
+        GATE_IP_G3D,
         GATE_IP_GEN,
         GATE_IP_FSYS,
         GATE_IP_PERIC,
@@ -189,10 +193,12 @@ PNAME(mout_vpllsrc_p)	= { "fin_pll", "sclk_hdmi27m" };
 PNAME(mout_vpll_p)      = { "mout_vpllsrc", "fout_vpll" };
 PNAME(mout_cpll_p)      = { "fin_pll", "fout_cpll" };
 PNAME(mout_epll_p)      = { "fin_pll", "fout_epll" };
+PNAME(mout_gpll_p)      = { "fin_pll", "fout_gpll" };
 PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
 PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
 PNAME(mout_aclk166_p)   = { "mout_cpll", "mout_mpll_user" };
 PNAME(mout_aclk200_p)   = { "mout_mpll_user", "mout_bpll_user" };
+PNAME(mout_aclk400_p)   = { "mout_aclk400_g3d_mid", "mout_gpll" };
 PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
 PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
 PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
@@ -273,12 +279,16 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
         MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
         MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
         MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
+        MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
+
+        MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),
 
         MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
         MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
         MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
         MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
         MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
+        MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
 
         MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1),
         MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
@@ -351,6 +361,8 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
         DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
         DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
         DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
+        DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
+                                                        24, 3),
 
         DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
 
@@ -428,6 +440,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
          * CMU_ACP
          */
         GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
+        GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
         GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
         GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
 
@@ -533,7 +546,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
                 0),
         GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
                 0),
-
+        GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0,
+                                        CLK_SET_RATE_PARENT, 0),
         GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
         GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
         GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index c3e0894d0279..1c3674ecc0dc 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -27,18 +27,24 @@
 #define DIV_CPU1                0x504
 #define GATE_BUS_CPU            0x700
 #define GATE_SCLK_CPU           0x800
+#define CLKOUT_CMU_CPU          0xa00
+#define GATE_IP_G2D             0x8800
 #define CPLL_LOCK               0x10020
 #define DPLL_LOCK               0x10030
 #define EPLL_LOCK               0x10040
 #define RPLL_LOCK               0x10050
 #define IPLL_LOCK               0x10060
 #define SPLL_LOCK               0x10070
-#define VPLL_LOCK               0x10070
+#define VPLL_LOCK               0x10080
 #define MPLL_LOCK               0x10090
 #define CPLL_CON0               0x10120
 #define DPLL_CON0               0x10128
 #define EPLL_CON0               0x10130
+#define EPLL_CON1               0x10134
+#define EPLL_CON2               0x10138
 #define RPLL_CON0               0x10140
+#define RPLL_CON1               0x10144
+#define RPLL_CON2               0x10148
 #define IPLL_CON0               0x10150
 #define SPLL_CON0               0x10160
 #define VPLL_CON0               0x10170
@@ -56,10 +62,14 @@
 #define SRC_FSYS                0x10244
 #define SRC_PERIC0              0x10250
 #define SRC_PERIC1              0x10254
+#define SRC_ISP                 0x10270
 #define SRC_TOP10               0x10280
 #define SRC_TOP11               0x10284
 #define SRC_TOP12               0x10288
-#define SRC_MASK_DISP10         0x1032c
+#define SRC_MASK_TOP2           0x10308
+#define SRC_MASK_TOP7           0x1031c
+#define SRC_MASK_DISP10         0x1032c
+#define SRC_MASK_MAU            0x10334
 #define SRC_MASK_FSYS           0x10340
 #define SRC_MASK_PERIC0         0x10350
 #define SRC_MASK_PERIC1         0x10354
@@ -76,27 +86,38 @@
 #define DIV_PERIC2              0x10560
 #define DIV_PERIC3              0x10564
 #define DIV_PERIC4              0x10568
+#define SCLK_DIV_ISP0           0x10580
+#define SCLK_DIV_ISP1           0x10584
+#define DIV2_RATIO0             0x10590
+#define DIV4_RATIO              0x105a0
 #define GATE_BUS_TOP            0x10700
+#define GATE_BUS_GEN            0x1073c
 #define GATE_BUS_FSYS0          0x10740
+#define GATE_BUS_FSYS2          0x10748
 #define GATE_BUS_PERIC          0x10750
 #define GATE_BUS_PERIC1         0x10754
 #define GATE_BUS_PERIS0         0x10760
 #define GATE_BUS_PERIS1         0x10764
+#define GATE_BUS_NOC            0x10770
+#define GATE_TOP_SCLK_ISP       0x10870
 #define GATE_IP_GSCL0           0x10910
 #define GATE_IP_GSCL1           0x10920
 #define GATE_IP_MFC             0x1092c
 #define GATE_IP_DISP1           0x10928
 #define GATE_IP_G3D             0x10930
 #define GATE_IP_GEN             0x10934
+#define GATE_IP_FSYS            0x10944
+#define GATE_IP_PERIC           0x10950
+#define GATE_IP_PERIS           0x10960
 #define GATE_IP_MSCL            0x10970
 #define GATE_TOP_SCLK_GSCL      0x10820
 #define GATE_TOP_SCLK_DISP1     0x10828
 #define GATE_TOP_SCLK_MAU       0x1083c
 #define GATE_TOP_SCLK_FSYS      0x10840
 #define GATE_TOP_SCLK_PERIC     0x10850
+#define TOP_SPARE2              0x10b08
 #define BPLL_LOCK               0x20010
 #define BPLL_CON0               0x20110
-#define SRC_CDREX               0x20200
 #define KPLL_LOCK               0x28000
 #define KPLL_CON0               0x28100
 #define SRC_KFC                 0x28200
@@ -124,6 +145,13 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
         DIV_CPU1,
         GATE_BUS_CPU,
         GATE_SCLK_CPU,
+        CLKOUT_CMU_CPU,
+        EPLL_CON0,
+        EPLL_CON1,
+        EPLL_CON2,
+        RPLL_CON0,
+        RPLL_CON1,
+        RPLL_CON2,
         SRC_TOP0,
         SRC_TOP1,
         SRC_TOP2,
@@ -140,10 +168,13 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
         SRC_TOP10,
         SRC_TOP11,
         SRC_TOP12,
+        SRC_MASK_TOP2,
+        SRC_MASK_TOP7,
         SRC_MASK_DISP10,
         SRC_MASK_FSYS,
         SRC_MASK_PERIC0,
         SRC_MASK_PERIC1,
+        SRC_ISP,
         DIV_TOP0,
         DIV_TOP1,
         DIV_TOP2,
@@ -157,25 +188,36 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
         DIV_PERIC2,
         DIV_PERIC3,
         DIV_PERIC4,
+        SCLK_DIV_ISP0,
+        SCLK_DIV_ISP1,
+        DIV2_RATIO0,
+        DIV4_RATIO,
         GATE_BUS_TOP,
+        GATE_BUS_GEN,
         GATE_BUS_FSYS0,
+        GATE_BUS_FSYS2,
         GATE_BUS_PERIC,
         GATE_BUS_PERIC1,
         GATE_BUS_PERIS0,
         GATE_BUS_PERIS1,
+        GATE_BUS_NOC,
+        GATE_TOP_SCLK_ISP,
         GATE_IP_GSCL0,
         GATE_IP_GSCL1,
         GATE_IP_MFC,
         GATE_IP_DISP1,
         GATE_IP_G3D,
         GATE_IP_GEN,
+        GATE_IP_FSYS,
+        GATE_IP_PERIC,
+        GATE_IP_PERIS,
         GATE_IP_MSCL,
         GATE_TOP_SCLK_GSCL,
         GATE_TOP_SCLK_DISP1,
         GATE_TOP_SCLK_MAU,
         GATE_TOP_SCLK_FSYS,
         GATE_TOP_SCLK_PERIC,
-        SRC_CDREX,
+        TOP_SPARE2,
         SRC_KFC,
         DIV_KFC0,
 };
@@ -216,85 +258,117 @@ static void exynos5420_clk_sleep_init(void) {}
 #endif
 
 /* list of all parent clocks */
-PNAME(mspll_cpu_p)      = { "sclk_cpll", "sclk_dpll",
-                                "sclk_mpll", "sclk_spll" };
-PNAME(cpu_p)            = { "mout_apll" , "mout_mspll_cpu" };
-PNAME(kfc_p)            = { "mout_kpll" , "mout_mspll_kfc" };
-PNAME(apll_p)           = { "fin_pll", "fout_apll", };
-PNAME(bpll_p)           = { "fin_pll", "fout_bpll", };
-PNAME(cpll_p)           = { "fin_pll", "fout_cpll", };
-PNAME(dpll_p)           = { "fin_pll", "fout_dpll", };
-PNAME(epll_p)           = { "fin_pll", "fout_epll", };
-PNAME(ipll_p)           = { "fin_pll", "fout_ipll", };
-PNAME(kpll_p)           = { "fin_pll", "fout_kpll", };
-PNAME(mpll_p)           = { "fin_pll", "fout_mpll", };
-PNAME(rpll_p)           = { "fin_pll", "fout_rpll", };
-PNAME(spll_p)           = { "fin_pll", "fout_spll", };
-PNAME(vpll_p)           = { "fin_pll", "fout_vpll", };
-
-PNAME(group1_p)         = { "sclk_cpll", "sclk_dpll", "sclk_mpll" };
-PNAME(group2_p)         = { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll",
-                          "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
-PNAME(group3_p)         = { "sclk_rpll", "sclk_spll" };
-PNAME(group4_p)         = { "sclk_ipll", "sclk_dpll", "sclk_mpll" };
-PNAME(group5_p)         = { "sclk_vpll", "sclk_dpll" };
-
-PNAME(sw_aclk66_p)      = { "dout_aclk66", "sclk_spll" };
-PNAME(aclk66_peric_p)   = { "fin_pll", "mout_sw_aclk66" };
-
-PNAME(sw_aclk200_fsys_p) = { "dout_aclk200_fsys", "sclk_spll"};
-PNAME(user_aclk200_fsys_p)      = { "fin_pll", "mout_sw_aclk200_fsys" };
-
-PNAME(sw_aclk200_fsys2_p) = { "dout_aclk200_fsys2", "sclk_spll"};
-PNAME(user_aclk200_fsys2_p)     = { "fin_pll", "mout_sw_aclk200_fsys2" };
-
-PNAME(sw_aclk200_p) = { "dout_aclk200", "sclk_spll"};
-PNAME(aclk200_disp1_p)  = { "fin_pll", "mout_sw_aclk200" };
-
-PNAME(sw_aclk400_mscl_p) = { "dout_aclk400_mscl", "sclk_spll"};
-PNAME(user_aclk400_mscl_p)      = { "fin_pll", "mout_sw_aclk400_mscl" };
-
-PNAME(sw_aclk333_p) = { "dout_aclk333", "sclk_spll"};
-PNAME(user_aclk333_p)   = { "fin_pll", "mout_sw_aclk333" };
-
-PNAME(sw_aclk166_p) = { "dout_aclk166", "sclk_spll"};
-PNAME(user_aclk166_p)   = { "fin_pll", "mout_sw_aclk166" };
-
-PNAME(sw_aclk266_p) = { "dout_aclk266", "sclk_spll"};
-PNAME(user_aclk266_p)   = { "fin_pll", "mout_sw_aclk266" };
-
-PNAME(sw_aclk333_432_gscl_p) = { "dout_aclk333_432_gscl", "sclk_spll"};
-PNAME(user_aclk333_432_gscl_p)  = { "fin_pll", "mout_sw_aclk333_432_gscl" };
-
-PNAME(sw_aclk300_gscl_p) = { "dout_aclk300_gscl", "sclk_spll"};
-PNAME(user_aclk300_gscl_p)      = { "fin_pll", "mout_sw_aclk300_gscl" };
-
-PNAME(sw_aclk300_disp1_p) = { "dout_aclk300_disp1", "sclk_spll"};
-PNAME(user_aclk300_disp1_p)     = { "fin_pll", "mout_sw_aclk300_disp1" };
-
-PNAME(sw_aclk300_jpeg_p) = { "dout_aclk300_jpeg", "sclk_spll"};
-PNAME(user_aclk300_jpeg_p)      = { "fin_pll", "mout_sw_aclk300_jpeg" };
-
-PNAME(sw_aclk_g3d_p) = { "dout_aclk_g3d", "sclk_spll"};
-PNAME(user_aclk_g3d_p)  = { "fin_pll", "mout_sw_aclk_g3d" };
-
-PNAME(sw_aclk266_g2d_p) = { "dout_aclk266_g2d", "sclk_spll"};
-PNAME(user_aclk266_g2d_p)       = { "fin_pll", "mout_sw_aclk266_g2d" };
-
-PNAME(sw_aclk333_g2d_p) = { "dout_aclk333_g2d", "sclk_spll"};
-PNAME(user_aclk333_g2d_p)       = { "fin_pll", "mout_sw_aclk333_g2d" };
-
-PNAME(audio0_p) = { "fin_pll", "cdclk0", "sclk_dpll", "sclk_mpll",
-                  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
-PNAME(audio1_p) = { "fin_pll", "cdclk1", "sclk_dpll", "sclk_mpll",
-                  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
-PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll",
-                  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
-PNAME(spdif_p)  = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2",
-                  "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" };
-PNAME(hdmi_p)   = { "dout_hdmi_pixel", "sclk_hdmiphy" };
-PNAME(maudio0_p)        = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
-                          "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
+PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
+                                "mout_sclk_mpll", "mout_sclk_spll"};
+PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
+PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
+PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
+PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
+PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
+PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
+PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
+PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
+PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
+PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
+PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
+PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
+PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
+
+PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
+                                        "mout_sclk_mpll"};
+PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
+                        "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
+                        "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
+PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
+PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
+
+PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
+PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
+PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
+PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
+
+PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
+PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
+PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
+PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
+
+PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
+PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
+PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
+PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
+
+PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
+PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
+PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
+
+PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
+PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
+
+PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
+                                        "mout_sclk_spll"};
+PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
+
+PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
+PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
+
+PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
+PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
+
+PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
+PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
+
+PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
+PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
+
+PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
+PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
+
+PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
+PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
+PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
+
+PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
+PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
+
+PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
+PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
+
+PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
+PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
+PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
+PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
+
+PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
+PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
+
+PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
+PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
+
+PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
+PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
+
+PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
+PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
+
+PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
+                        "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
+                        "mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
+                        "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
+                        "mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
+                        "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
+                        "mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
+                        "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
+                        "mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
+PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
+                         "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
+                         "mout_sclk_epll", "mout_sclk_rpll"};
+PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
+                                "mout_sclk_mpll", "mout_sclk_spll"};
 
 /* fixed rate clocks generated outside the soc */
 static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
@@ -311,145 +385,219 @@ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata =
 };
 
 static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = {
-        FFACTOR(0, "sclk_hsic_12m", "fin_pll", 1, 2, 0),
+        FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
+        FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
 };
 
 static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
-        MUX(0, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2),
-        MUX(0, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2),
-        MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
-        MUX(0, "mout_cpu", cpu_p, SRC_CPU, 16, 1),
-        MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
-        MUX(0, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1),
+        MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
+                        SRC_TOP7, 4, 1),
+        MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
+        MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
+        MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
 
-        MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
+        MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+        MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
+        MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
+        MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
 
-        MUX_A(0, "mout_aclk400_mscl", group1_p,
+        MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
+
+        MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
+        MUX_A(0, "mout_aclk400_mscl", mout_group1_p,
                         SRC_TOP0, 4, 2, "aclk400_mscl"),
-        MUX(0, "mout_aclk200", group1_p, SRC_TOP0, 8, 2),
-        MUX(0, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2),
-        MUX(0, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2),
-
-        MUX(0, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2),
-        MUX(0, "mout_aclk66", group1_p, SRC_TOP1, 8, 2),
-        MUX(0, "mout_aclk266", group1_p, SRC_TOP1, 20, 2),
-        MUX(0, "mout_aclk166", group1_p, SRC_TOP1, 24, 2),
-        MUX(0, "mout_aclk333", group1_p, SRC_TOP1, 28, 2),
-
-        MUX(0, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2),
-        MUX(0, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2),
-        MUX(0, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1),
-        MUX(0, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2),
-        MUX(0, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2),
-        MUX(0, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2),
-
-        MUX(0, "mout_user_aclk400_mscl", user_aclk400_mscl_p,
+        MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
+        MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
+        MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
+        MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
+        MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
+        MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
+
+        MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
+        MUX(0, "mout_aclk333_432_isp", mout_group4_p,
+                        SRC_TOP1, 4, 2),
+        MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
+        MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
+        MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
+        MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
+        MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
+
+        MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
+        MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
+        MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
+        MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
+        MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
+        MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
+        MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
+
+        MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
+                        SRC_TOP3, 0, 1),
+        MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
                         SRC_TOP3, 4, 1),
-        MUX_A(0, "mout_aclk200_disp1", aclk200_disp1_p,
-                        SRC_TOP3, 8, 1, "aclk200_disp1"),
-        MUX(0, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p,
+        MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p,
+                        SRC_TOP3, 8, 1),
+        MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
                         SRC_TOP3, 12, 1),
-        MUX(0, "mout_user_aclk200_fsys", user_aclk200_fsys_p,
+        MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
+                        SRC_TOP3, 16, 1),
+        MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
+                        SRC_TOP3, 20, 1),
+        MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
+                        SRC_TOP3, 24, 1),
+        MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
                         SRC_TOP3, 28, 1),
 
-        MUX(0, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p,
+        MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
                         SRC_TOP4, 0, 1),
-        MUX(0, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1),
-        MUX(0, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1),
-        MUX(0, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1),
-        MUX(0, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1),
-
-        MUX(0, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1),
-        MUX(0, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1),
-        MUX(0, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1),
-        MUX_A(0, "mout_user_aclk_g3d", user_aclk_g3d_p,
-                        SRC_TOP5, 16, 1, "aclkg3d"),
-        MUX(0, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p,
+        MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
+                        SRC_TOP4, 4, 1),
+        MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
+                        SRC_TOP4, 8, 1),
+        MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
+                        SRC_TOP4, 12, 1),
+        MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
+                        SRC_TOP4, 16, 1),
+        MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
+        MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
+        MUX(0, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1),
+
+        MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
+                        SRC_TOP5, 0, 1),
+        MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
+                        SRC_TOP5, 4, 1),
+        MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
+                        SRC_TOP5, 8, 1),
+        MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
+                        SRC_TOP5, 12, 1),
+        MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
+                        SRC_TOP5, 16, 1),
+        MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
                         SRC_TOP5, 20, 1),
-        MUX(0, "mout_user_aclk300_disp1", user_aclk300_disp1_p,
+        MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p,
                         SRC_TOP5, 24, 1),
-        MUX(0, "mout_user_aclk300_gscl", user_aclk300_gscl_p,
+        MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
                         SRC_TOP5, 28, 1),
 
-        MUX(0, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1),
-        MUX(0, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),
-        MUX(0, "sclk_spll", spll_p, SRC_TOP6, 8, 1),
-        MUX(0, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1),
-        MUX(0, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1),
-        MUX(0, "sclk_epll", epll_p, SRC_TOP6, 20, 1),
-        MUX(0, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1),
-        MUX(0, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1),
-
-        MUX(0, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
-        MUX(0, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1),
-        MUX(0, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p,
+        MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
+        MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
+        MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
+        MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
+        MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
+        MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
+        MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
+        MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
+
+        MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
+                        SRC_TOP10, 0, 1),
+        MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
+                        SRC_TOP10, 4, 1),
+        MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1),
+        MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
                         SRC_TOP10, 12, 1),
-        MUX(0, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1),
-
-        MUX(0, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p,
+        MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
+                        SRC_TOP10, 16, 1),
+        MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
+                        SRC_TOP10, 20, 1),
+        MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
+                        SRC_TOP10, 24, 1),
+        MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
+                        SRC_TOP10, 28, 1),
+
+        MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
                         SRC_TOP11, 0, 1),
-        MUX(0, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1),
-        MUX(0, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1),
-        MUX(0, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1),
-        MUX(0, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1),
-
-        MUX(0, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1),
-        MUX(0, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1),
-        MUX(0, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1),
-        MUX(0, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1),
-        MUX(0, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p,
+        MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
+                        SRC_TOP11, 4, 1),
+        MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
+        MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
+                        SRC_TOP11, 12, 1),
+        MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
+        MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
+        MUX(0, "mout_sw_aclk333", mout_sw_aclk333_p, SRC_TOP11, 28, 1),
+
+        MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
+                        SRC_TOP12, 4, 1),
+        MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
+                        SRC_TOP12, 8, 1),
+        MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
+                        SRC_TOP12, 12, 1),
+        MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
+        MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
+                        SRC_TOP12, 20, 1),
+        MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p,
                         SRC_TOP12, 24, 1),
-        MUX(0, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
+        MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
+                        SRC_TOP12, 28, 1),
 
         /* DISP1 Block */
-        MUX(0, "mout_fimd1", group3_p, SRC_DISP10, 4, 1),
-        MUX(0, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
-        MUX(0, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
-        MUX(0, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
-        MUX(CLK_MOUT_HDMI, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
+        MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
+        MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
+        MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
+        MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
+        MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
+        MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
+
+        MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
+                        TOP_SPARE2, 4, 1),
+        MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
 
         /* MAU Block */
-        MUX(0, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
+        MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
 
         /* FSYS Block */
-        MUX(0, "mout_usbd301", group2_p, SRC_FSYS, 4, 3),
-        MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 8, 3),
-        MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 12, 3),
-        MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 16, 3),
-        MUX(0, "mout_usbd300", group2_p, SRC_FSYS, 20, 3),
-        MUX(0, "mout_unipro", group2_p, SRC_FSYS, 24, 3),
+        MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
+        MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
+        MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
+        MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
+        MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
+        MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
+        MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
 
         /* PERIC Block */
-        MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 4, 3),
-        MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 8, 3),
-        MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 12, 3),
-        MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 16, 3),
-        MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 3),
-        MUX(0, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3),
-        MUX(0, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3),
-        MUX(0, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3),
-        MUX(0, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3),
-        MUX(0, "mout_spi0", group2_p, SRC_PERIC1, 20, 3),
-        MUX(0, "mout_spi1", group2_p, SRC_PERIC1, 24, 3),
-        MUX(0, "mout_spi2", group2_p, SRC_PERIC1, 28, 3),
+        MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
+        MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
+        MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
+        MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
+        MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
+        MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
+        MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
+        MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
+        MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
+        MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
+        MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
+        MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
+
+        /* ISP Block */
+        MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
+        MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
+        MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
+        MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
+        MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
 };
 
 static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
         DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
         DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
         DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
-        DIV(0, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3),
+        DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
         DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
 
+        DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
         DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
         DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
         DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
+        DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll",
+                        DIV_TOP0, 16, 3),
+        DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3),
         DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
         DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
 
         DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
                         DIV_TOP1, 0, 3),
+        DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp",
+                        DIV_TOP1, 4, 3),
         DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
+        DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",
+                        DIV_TOP1, 16, 3),
         DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
         DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
         DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
@@ -458,15 +606,16 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
         DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
         DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
         DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
-        DIV_A(0, "dout_aclk300_disp1", "mout_aclk300_disp1",
-                        DIV_TOP2, 24, 3, "aclk300_disp1"),
+        DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3),
         DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
 
         /* DISP1 Block */
-        DIV(0, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
+        DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
         DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
         DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
         DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
+        DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
+        DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3),
 
         /* Audio Block */
         DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
@@ -484,6 +633,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
         DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
 
         DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
+        DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
 
         /* UART and PWM */
         DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
@@ -497,6 +647,9 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
         DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
         DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
 
+        /* Mfc Block */
+        DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
+
         /* PCM */
         DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
         DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
@@ -509,15 +662,43 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
         DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
 
         /* SPI Pre-Ratio */
-        DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8),
-        DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8),
-        DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8),
+        DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
+        DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
+        DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
+
+        /* GSCL Block */
+        DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
+                        DIV2_RATIO0, 4, 2),
+        DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
+
+        /* MSCL Block */
+        DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
+
+        /* PSGEN */
+        DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
+        DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
+
+        /* ISP Block */
+        DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
+        DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
+        DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
+        DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
+        DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
+        DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
+        DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
+        DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
+                        CLK_SET_RATE_PARENT, 0),
+        DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
+                        CLK_SET_RATE_PARENT, 0),
 };
 
 static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
-        /* TODO: Re-verify the CG bits for all the gate clocks */
-        GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0,
-                "mct"),
+        /* G2D */
+        GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
+        GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
+        GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
+        GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
+        GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
 
         GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
                         GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
@@ -530,20 +711,42 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
                         GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
         GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
                         GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
+        GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
+                        GATE_BUS_TOP, 5, 0, 0),
         GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
                         GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
         GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
                         GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
-        GATE(0, "pclk66_gpio", "mout_sw_aclk66",
+        GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
+                        GATE_BUS_TOP, 8, 0, 0),
+        GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
                         GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
-        GATE(0, "aclk66_psgen", "mout_aclk66_psgen",
+        GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
                         GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
-        GATE(0, "aclk66_peric", "mout_aclk66_peric",
-                        GATE_BUS_TOP, 11, 0, 0),
+        GATE(CLK_ACLK66_PERIC, "aclk66_peric", "mout_user_aclk66_peric",
+                        GATE_BUS_TOP, 11, CLK_IGNORE_UNUSED, 0),
+        GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
+                        GATE_BUS_TOP, 13, 0, 0),
         GATE(0, "aclk166", "mout_user_aclk166",
                         GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
         GATE(0, "aclk333", "mout_aclk333",
                         GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
+        GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
+                        GATE_BUS_TOP, 16, 0, 0),
+        GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
+                        GATE_BUS_TOP, 17, 0, 0),
+        GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
+                        GATE_BUS_TOP, 18, 0, 0),
+        GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
+                        GATE_BUS_TOP, 28, 0, 0),
+        GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
+                        GATE_BUS_TOP, 29, 0, 0),
+
+        GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
+                        SRC_MASK_TOP2, 24, 0, 0),
+
+        GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
+                        SRC_MASK_TOP7, 20, 0, 0),
 
         /* sclk */
         GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
@@ -554,11 +757,11 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
                 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
         GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
                 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
-        GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_pre_spi0",
+        GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
                 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
-        GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_pre_spi1",
+        GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
                 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
-        GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_pre_spi2",
+        GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
                 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
         GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
                 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
@@ -588,161 +791,188 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
         GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
                 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
 
-        GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro",
-                SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
-
-        GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "aclK333_432_gscl",
-                GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0),
-        GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "aclk333_432_gscl",
-                GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),
-
         /* Display */
         GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
-                GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
+                        GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
         GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
-                GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
+                        GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
         GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
-                GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0),
+                        GATE_TOP_SCLK_DISP1, 9, 0, 0),
         GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
-                GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
+                        GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
         GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
-                GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
+                        GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
 
         /* Maudio Block */
         GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
                 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
         GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
                 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
-        /* FSYS */
+
+        /* FSYS Block */
         GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
         GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
         GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
         GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
-        GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0),
-        GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0),
-        GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0),
-        GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0),
+        GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
+        GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
+        GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
+        GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
         GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
-                        GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0),
-        GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0),
-        GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0),
-        GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0),
-
-        /* UART */
-        GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
-        GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
-        GATE_A(CLK_UART2, "uart2", "aclk66_peric",
-                GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
-        GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
-        /* I2C */
-        GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
-        GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
-        GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
-        GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
-        GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
-        GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
-        GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
-        GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
-        GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0,
-                0),
-        GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
-        /* SPI */
-        GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
-        GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
-        GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
-        GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
-        /* I2S */
-        GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
-        GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
-        /* PCM */
-        GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
-        GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
-        /* PWM */
-        GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
-        /* SPDIF */
-        GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
+                        GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
+        GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
+        GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
+        GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
+                        SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
 
-        GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0),
-        GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0),
-        GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0),
+        /* PERIC Block */
+        GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_IP_PERIC, 0, 0, 0),
+        GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_IP_PERIC, 1, 0, 0),
+        GATE(CLK_UART2, "uart2", "aclk66_peric", GATE_IP_PERIC, 2, 0, 0),
+        GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_IP_PERIC, 3, 0, 0),
+        GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_IP_PERIC, 6, 0, 0),
+        GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_IP_PERIC, 7, 0, 0),
+        GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_IP_PERIC, 8, 0, 0),
+        GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_IP_PERIC, 9, 0, 0),
+        GATE(CLK_USI0, "usi0", "aclk66_peric", GATE_IP_PERIC, 10, 0, 0),
+        GATE(CLK_USI1, "usi1", "aclk66_peric", GATE_IP_PERIC, 11, 0, 0),
+        GATE(CLK_USI2, "usi2", "aclk66_peric", GATE_IP_PERIC, 12, 0, 0),
+        GATE(CLK_USI3, "usi3", "aclk66_peric", GATE_IP_PERIC, 13, 0, 0),
+        GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_IP_PERIC, 14, 0, 0),
+        GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_IP_PERIC, 15, 0, 0),
+        GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_IP_PERIC, 16, 0, 0),
+        GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_IP_PERIC, 17, 0, 0),
+        GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_IP_PERIC, 18, 0, 0),
+        GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_IP_PERIC, 20, 0, 0),
+        GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_IP_PERIC, 21, 0, 0),
+        GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_IP_PERIC, 22, 0, 0),
+        GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_IP_PERIC, 23, 0, 0),
+        GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_IP_PERIC, 24, 0, 0),
+        GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_IP_PERIC, 26, 0, 0),
+        GATE(CLK_USI4, "usi4", "aclk66_peric", GATE_IP_PERIC, 28, 0, 0),
+        GATE(CLK_USI5, "usi5", "aclk66_peric", GATE_IP_PERIC, 30, 0, 0),
+        GATE(CLK_USI6, "usi6", "aclk66_peric", GATE_IP_PERIC, 31, 0, 0),
 
+        GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
+
+        /* PERIS Block */
         GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
-                        GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0),
+                        GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
         GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
-                        GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0),
-        GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0),
-        GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0),
-        GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0),
-        GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0),
-        GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0),
-        GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0),
-        GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0),
-        GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0),
-        GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0),
-        GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0),
-
-        GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0,
-                0),
+                        GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
+        GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
+        GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
+        GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
+        GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
+        GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
+        GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
+        GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
+        GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
+        GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
+        GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
+        GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
+        GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
+        GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
+        GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
+        GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
+        GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
+
         GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
-        GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0),
-        GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0),
-        GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0),
-        GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0),
+
+        /* GEN Block */
+        GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
+        GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
+        GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
+        GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
+        GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
+        GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
+                        GATE_IP_GEN, 6, 0, 0),
+        GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
+        GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
+                        GATE_IP_GEN, 9, 0, 0),
+
+        /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
+        GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
+                        GATE_BUS_GEN, 28, 0, 0),
+        GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
+
+        /* GSCL Block */
+        GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
+                        GATE_TOP_SCLK_GSCL, 6, 0, 0),
+        GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
+                        GATE_TOP_SCLK_GSCL, 7, 0, 0),
 
         GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
         GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
-        GATE(CLK_CLK_3AA, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0),
-
-        GATE(CLK_SMMU_3AA, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0,
-                0),
-        GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "aclk333_432_gscl",
+        GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
+                        GATE_IP_GSCL0, 4, 0, 0),
+        GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
+                        GATE_IP_GSCL0, 5, 0, 0),
+        GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
+                        GATE_IP_GSCL0, 6, 0, 0),
+
+        GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
+                        GATE_IP_GSCL1, 2, 0, 0),
+        GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
                         GATE_IP_GSCL1, 3, 0, 0),
-        GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "aclk333_432_gscl",
+        GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
                         GATE_IP_GSCL1, 4, 0, 0),
-        GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0,
-                0),
-        GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0,
-                0),
-        GATE(CLK_GSCL_WA, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0),
-        GATE(CLK_GSCL_WB, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0),
-        GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "aclk333_432_gscl",
+        GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
+                        GATE_IP_GSCL1, 6, 0, 0),
+        GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
+                        GATE_IP_GSCL1, 7, 0, 0),
+        GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0),
+        GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0),
+        GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
                         GATE_IP_GSCL1, 16, 0, 0),
         GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
                         GATE_IP_GSCL1, 17, 0, 0),
 
+        /* MSCL Block */
+        GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
+        GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
+        GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
+        GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
+                        GATE_IP_MSCL, 8, 0, 0),
+        GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
+                        GATE_IP_MSCL, 9, 0, 0),
+        GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
+                        GATE_IP_MSCL, 10, 0, 0),
+
         GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
         GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
         GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
-        GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0),
+        GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
         GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
-        GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0,
-                0),
+        GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
+                        GATE_IP_DISP1, 7, 0, 0),
+        GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
+                        GATE_IP_DISP1, 8, 0, 0),
+        GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
+                        GATE_IP_DISP1, 9, 0, 0),
+
+        /* ISP */
+        GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
+                        GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
+                        GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
+                        GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
+                        GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
+                        GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
+                        GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
+                        GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
 
         GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
-        GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
-        GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
+        GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
+        GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
 
-        GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
-
-        GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
-        GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
-        GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
-        GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
-        GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
-        GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
-        GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
-
-        GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
-        GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
-        GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
-        GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0,
-                0),
-        GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0,
-                0),
-        GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0,
-                0),
-        GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
-                0),
+        GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
 };
 
 static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 41c1461d2f58..49629c71c9e7 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -54,14 +54,19 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
         struct samsung_clk_provider *ctx;
         struct clk **clk_table;
         int ret;
+        int i;
+
         ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
         if (!ctx)
                 panic("could not allocate clock provider context.\n");
 
-        clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
+        clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
         if (!clk_table)
                 panic("could not allocate clock lookup table\n");
 
+        for (i = 0; i < nr_clks; ++i)
+                clk_table[i] = ERR_PTR(-ENOENT);
+
         ctx->reg_base = base;
         ctx->clk_data.clks = clk_table;
         ctx->clk_data.clk_num = nr_clks;
@@ -288,7 +293,7 @@ void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
         for_each_matching_node_and_match(clk_np, clk_matches, &match) {
                 if (of_property_read_u32(clk_np, "clock-frequency", &freq))
                         continue;
-                fixed_rate_clk[(u32)match->data].fixed_rate = freq;
+                fixed_rate_clk[(unsigned long)match->data].fixed_rate = freq;
         }
         samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
 }
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 75aff336dfb0..1106ca540a96 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -33,6 +33,7 @@
 #define CLK_MOUT_MPLL_USER_C    18 /* Exynos4x12 only */
 #define CLK_MOUT_CORE           19
 #define CLK_MOUT_APLL           20
+#define CLK_SCLK_HDMIPHY        22
 
 /* gate for special clocks (sclk) */
 #define CLK_SCLK_FIMC0          128
@@ -181,7 +182,6 @@
 #define CLK_KEYIF               347
 #define CLK_AUDSS               348
 #define CLK_MIPI_HSI            349 /* Exynos4210 only */
-#define CLK_MDMA2               350 /* Exynos4210 only */
 #define CLK_PIXELASYNCM0        351
 #define CLK_PIXELASYNCM1        352
 #define CLK_FIMC_LITE0          353 /* Exynos4x12 only */
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
index 922f2dca9bf0..415d447e6e29 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -150,11 +150,14 @@
 #define CLK_G2D                 345
 #define CLK_MDMA0               346
 #define CLK_SMMU_MDMA0          347
+#define CLK_SSS                 348
+#define CLK_G3D                 349
 
 /* mux clocks */
 #define CLK_MOUT_HDMI           1024
+#define CLK_MOUT_GPLL           1025
 
 /* must be greater than maximal clock id */
-#define CLK_NR_CLKS             1025
+#define CLK_NR_CLKS             1026
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 5eefd8813f02..7dd1cc3b5c57 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -58,6 +58,9 @@
 #define CLK_SCLK_GSCL_WA        156
 #define CLK_SCLK_GSCL_WB        157
 #define CLK_SCLK_HDMIPHY        158
+#define CLK_MAU_EPLL            159
+#define CLK_SCLK_HSIC_12M       160
+#define CLK_SCLK_MPHY_IXTAL24   161
 
 /* gate clocks */
 #define CLK_ACLK66_PERIC        256
@@ -69,10 +72,10 @@
 #define CLK_I2C1                262
 #define CLK_I2C2                263
 #define CLK_I2C3                264
-#define CLK_I2C4                265
-#define CLK_I2C5                266
-#define CLK_I2C6                267
-#define CLK_I2C7                268
+#define CLK_USI0                265
+#define CLK_USI1                266
+#define CLK_USI2                267
+#define CLK_USI3                268
 #define CLK_I2C_HDMI            269
 #define CLK_TSADC               270
 #define CLK_SPI0                271
@@ -85,9 +88,9 @@
 #define CLK_PCM2                278
 #define CLK_PWM                 279
 #define CLK_SPDIF               280
-#define CLK_I2C8                281
-#define CLK_I2C9                282
-#define CLK_I2C10               283
+#define CLK_USI4                281
+#define CLK_USI5                282
+#define CLK_USI6                283
 #define CLK_ACLK66_PSGEN        300
 #define CLK_CHIPID              301
 #define CLK_SYSREG              302
@@ -140,7 +143,8 @@
 #define CLK_HDMI                413
 #define CLK_ACLK300_DISP1       420
 #define CLK_FIMD1               421
-#define CLK_SMMU_FIMD1          422
+#define CLK_SMMU_FIMD1M0        422
+#define CLK_SMMU_FIMD1M1        423
 #define CLK_ACLK166             430
 #define CLK_MIXER               431
 #define CLK_ACLK266             440
@@ -152,6 +156,7 @@
 #define CLK_JPEG                451
 #define CLK_JPEG2               452
 #define CLK_SMMU_JPEG           453
+#define CLK_SMMU_JPEG2          454
 #define CLK_ACLK300_GSCL        460
 #define CLK_SMMU_GSCL0          461
 #define CLK_SMMU_GSCL1          462
@@ -159,7 +164,7 @@
 #define CLK_GSCL_WB             464
 #define CLK_GSCL0               465
 #define CLK_GSCL1               466
-#define CLK_CLK_3AA             467
+#define CLK_FIMC_3AA            467
 #define CLK_ACLK266_G2D         470
 #define CLK_SSS                 471
 #define CLK_SLIM_SSS            472
@@ -172,12 +177,28 @@
 #define CLK_SMMU_FIMCL1         493
 #define CLK_SMMU_FIMCL3         494
 #define CLK_FIMC_LITE3          495
+#define CLK_FIMC_LITE0          496
+#define CLK_FIMC_LITE1          497
 #define CLK_ACLK_G3D            500
 #define CLK_G3D                 501
 #define CLK_SMMU_MIXER          502
+#define CLK_SMMU_G2D            503
+#define CLK_SMMU_MDMA0          504
+#define CLK_MC                  505
+#define CLK_TOP_RTC             506
+#define CLK_SCLK_UART_ISP       510
+#define CLK_SCLK_SPI0_ISP       511
+#define CLK_SCLK_SPI1_ISP       512
+#define CLK_SCLK_PWM_ISP        513
+#define CLK_SCLK_ISP_SENSOR0    514
+#define CLK_SCLK_ISP_SENSOR1    515
+#define CLK_SCLK_ISP_SENSOR2    516
 
 /* mux clocks */
 #define CLK_MOUT_HDMI           640
+#define CLK_MOUT_G3D            641
+#define CLK_MOUT_VPLL           642
+#define CLK_MOUT_MAUDIO0        643
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL          768