diff options
| -rw-r--r-- | drivers/mfd/sec-irq.c | 8 | ||||
| -rw-r--r-- | include/linux/mfd/samsung/irq.h | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c index 4de494f51d40..e403c293b437 100644 --- a/drivers/mfd/sec-irq.c +++ b/drivers/mfd/sec-irq.c | |||
| @@ -59,13 +59,13 @@ static const struct regmap_irq s2mps11_irqs[] = { | |||
| 59 | .reg_offset = 1, | 59 | .reg_offset = 1, |
| 60 | .mask = S2MPS11_IRQ_RTC60S_MASK, | 60 | .mask = S2MPS11_IRQ_RTC60S_MASK, |
| 61 | }, | 61 | }, |
| 62 | [S2MPS11_IRQ_RTCA1] = { | 62 | [S2MPS11_IRQ_RTCA0] = { |
| 63 | .reg_offset = 1, | 63 | .reg_offset = 1, |
| 64 | .mask = S2MPS11_IRQ_RTCA1_MASK, | 64 | .mask = S2MPS11_IRQ_RTCA0_MASK, |
| 65 | }, | 65 | }, |
| 66 | [S2MPS11_IRQ_RTCA2] = { | 66 | [S2MPS11_IRQ_RTCA1] = { |
| 67 | .reg_offset = 1, | 67 | .reg_offset = 1, |
| 68 | .mask = S2MPS11_IRQ_RTCA2_MASK, | 68 | .mask = S2MPS11_IRQ_RTCA1_MASK, |
| 69 | }, | 69 | }, |
| 70 | [S2MPS11_IRQ_SMPL] = { | 70 | [S2MPS11_IRQ_SMPL] = { |
| 71 | .reg_offset = 1, | 71 | .reg_offset = 1, |
diff --git a/include/linux/mfd/samsung/irq.h b/include/linux/mfd/samsung/irq.h index d43b4f9e7fb2..abe1a6aae3b7 100644 --- a/include/linux/mfd/samsung/irq.h +++ b/include/linux/mfd/samsung/irq.h | |||
| @@ -24,8 +24,8 @@ enum s2mps11_irq { | |||
| 24 | S2MPS11_IRQ_MRB, | 24 | S2MPS11_IRQ_MRB, |
| 25 | 25 | ||
| 26 | S2MPS11_IRQ_RTC60S, | 26 | S2MPS11_IRQ_RTC60S, |
| 27 | S2MPS11_IRQ_RTCA0, | ||
| 27 | S2MPS11_IRQ_RTCA1, | 28 | S2MPS11_IRQ_RTCA1, |
| 28 | S2MPS11_IRQ_RTCA2, | ||
| 29 | S2MPS11_IRQ_SMPL, | 29 | S2MPS11_IRQ_SMPL, |
| 30 | S2MPS11_IRQ_RTC1S, | 30 | S2MPS11_IRQ_RTC1S, |
| 31 | S2MPS11_IRQ_WTSR, | 31 | S2MPS11_IRQ_WTSR, |
| @@ -47,7 +47,7 @@ enum s2mps11_irq { | |||
| 47 | 47 | ||
| 48 | #define S2MPS11_IRQ_RTC60S_MASK (1 << 0) | 48 | #define S2MPS11_IRQ_RTC60S_MASK (1 << 0) |
| 49 | #define S2MPS11_IRQ_RTCA1_MASK (1 << 1) | 49 | #define S2MPS11_IRQ_RTCA1_MASK (1 << 1) |
| 50 | #define S2MPS11_IRQ_RTCA2_MASK (1 << 2) | 50 | #define S2MPS11_IRQ_RTCA0_MASK (1 << 2) |
| 51 | #define S2MPS11_IRQ_SMPL_MASK (1 << 3) | 51 | #define S2MPS11_IRQ_SMPL_MASK (1 << 3) |
| 52 | #define S2MPS11_IRQ_RTC1S_MASK (1 << 4) | 52 | #define S2MPS11_IRQ_RTC1S_MASK (1 << 4) |
| 53 | #define S2MPS11_IRQ_WTSR_MASK (1 << 5) | 53 | #define S2MPS11_IRQ_WTSR_MASK (1 << 5) |
