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authorKrzysztof Kozlowski <k.kozlowski@samsung.com>2014-02-28 05:41:43 -0500
committerLee Jones <lee.jones@linaro.org>2014-03-18 06:49:52 -0400
commit677620952a0fd1b1618bed57c1ebd94bf3c710f3 (patch)
treec34df7a35aaefbdffef34070f50a3a0d1d2d44cc
parent3e5a45f7f16e9f71c0e2ce4f8f5827a8298a8362 (diff)
mfd: sec-irq: Use consistent S2MPS11 RTC alarm interrupt indexes
The S2MPS11 RTC has two alarms: alarm0 and alarm1 (corresponding interrupts are named similarly). Use consistent names for interrupts to limit possible errors. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
-rw-r--r--drivers/mfd/sec-irq.c8
-rw-r--r--include/linux/mfd/samsung/irq.h4
2 files changed, 6 insertions, 6 deletions
diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c
index 4de494f51d40..e403c293b437 100644
--- a/drivers/mfd/sec-irq.c
+++ b/drivers/mfd/sec-irq.c
@@ -59,13 +59,13 @@ static const struct regmap_irq s2mps11_irqs[] = {
59 .reg_offset = 1, 59 .reg_offset = 1,
60 .mask = S2MPS11_IRQ_RTC60S_MASK, 60 .mask = S2MPS11_IRQ_RTC60S_MASK,
61 }, 61 },
62 [S2MPS11_IRQ_RTCA1] = { 62 [S2MPS11_IRQ_RTCA0] = {
63 .reg_offset = 1, 63 .reg_offset = 1,
64 .mask = S2MPS11_IRQ_RTCA1_MASK, 64 .mask = S2MPS11_IRQ_RTCA0_MASK,
65 }, 65 },
66 [S2MPS11_IRQ_RTCA2] = { 66 [S2MPS11_IRQ_RTCA1] = {
67 .reg_offset = 1, 67 .reg_offset = 1,
68 .mask = S2MPS11_IRQ_RTCA2_MASK, 68 .mask = S2MPS11_IRQ_RTCA1_MASK,
69 }, 69 },
70 [S2MPS11_IRQ_SMPL] = { 70 [S2MPS11_IRQ_SMPL] = {
71 .reg_offset = 1, 71 .reg_offset = 1,
diff --git a/include/linux/mfd/samsung/irq.h b/include/linux/mfd/samsung/irq.h
index d43b4f9e7fb2..abe1a6aae3b7 100644
--- a/include/linux/mfd/samsung/irq.h
+++ b/include/linux/mfd/samsung/irq.h
@@ -24,8 +24,8 @@ enum s2mps11_irq {
24 S2MPS11_IRQ_MRB, 24 S2MPS11_IRQ_MRB,
25 25
26 S2MPS11_IRQ_RTC60S, 26 S2MPS11_IRQ_RTC60S,
27 S2MPS11_IRQ_RTCA0,
27 S2MPS11_IRQ_RTCA1, 28 S2MPS11_IRQ_RTCA1,
28 S2MPS11_IRQ_RTCA2,
29 S2MPS11_IRQ_SMPL, 29 S2MPS11_IRQ_SMPL,
30 S2MPS11_IRQ_RTC1S, 30 S2MPS11_IRQ_RTC1S,
31 S2MPS11_IRQ_WTSR, 31 S2MPS11_IRQ_WTSR,
@@ -47,7 +47,7 @@ enum s2mps11_irq {
47 47
48#define S2MPS11_IRQ_RTC60S_MASK (1 << 0) 48#define S2MPS11_IRQ_RTC60S_MASK (1 << 0)
49#define S2MPS11_IRQ_RTCA1_MASK (1 << 1) 49#define S2MPS11_IRQ_RTCA1_MASK (1 << 1)
50#define S2MPS11_IRQ_RTCA2_MASK (1 << 2) 50#define S2MPS11_IRQ_RTCA0_MASK (1 << 2)
51#define S2MPS11_IRQ_SMPL_MASK (1 << 3) 51#define S2MPS11_IRQ_SMPL_MASK (1 << 3)
52#define S2MPS11_IRQ_RTC1S_MASK (1 << 4) 52#define S2MPS11_IRQ_RTC1S_MASK (1 << 4)
53#define S2MPS11_IRQ_WTSR_MASK (1 << 5) 53#define S2MPS11_IRQ_WTSR_MASK (1 << 5)