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-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index 1668ee57acb9..21732c306635 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -63,6 +63,28 @@ skip:
63 li v1, ~(7 << 7) 63 li v1, ~(7 << 7)
64 and v0, v0, v1 64 and v0, v0, v1
65 ori v0, v0, (6 << 7) 65 ori v0, v0, (6 << 7)
66
67 mfc0 v1, CP0_PRID_REG
68 and t1, v1, 0xfff8
69 xor t1, t1, 0x9000 # 63-P1
70 beqz t1, 4f
71 and t1, v1, 0xfff8
72 xor t1, t1, 0x9008 # 63-P2
73 beqz t1, 4f
74 and t1, v1, 0xfff8
75 xor t1, t1, 0x9100 # 68-P1
76 beqz t1, 4f
77 and t1, v1, 0xff00
78 xor t1, t1, 0x9200 # 66-PX
79 bnez t1, 5f # Skip WAR for others.
80 and t1, v1, 0x00ff
81 slti t1, t1, 2 # 66-P1.2 and later good.
82 beqz t1, 5f
83
844: # core-16057 work around
85 or v0, v0, 0x2000 # Set IPREF bit.
86
875: # No core-16057 work around
66 # Write the cavium control register 88 # Write the cavium control register
67 dmtc0 v0, CP0_CVMCTL_REG 89 dmtc0 v0, CP0_CVMCTL_REG
68 sync 90 sync