MIPS: OCTEON: Implement the core-16057 workaround

Disable ICache prefetch for certian Octeon II processors.

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8938/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 22 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index 1668ee57acb9..21732c306635 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -63,6 +63,28 @@ skip:
         li      v1, ~(7 << 7)
         and     v0, v0, v1
         ori     v0, v0, (6 << 7)
+
+        mfc0    v1, CP0_PRID_REG
+        and     t1, v1, 0xfff8
+        xor     t1, t1, 0x9000          # 63-P1
+        beqz    t1, 4f
+        and     t1, v1, 0xfff8
+        xor     t1, t1, 0x9008          # 63-P2
+        beqz    t1, 4f
+        and     t1, v1, 0xfff8
+        xor     t1, t1, 0x9100          # 68-P1
+        beqz    t1, 4f
+        and     t1, v1, 0xff00
+        xor     t1, t1, 0x9200          # 66-PX
+        bnez    t1, 5f                  # Skip WAR for others.
+        and     t1, v1, 0x00ff
+        slti    t1, t1, 2               # 66-P1.2 and later good.
+        beqz    t1, 5f
+
+4:      # core-16057 work around
+        or      v0, v0, 0x2000          # Set IPREF bit.
+
+5:      # No core-16057 work around
         # Write the cavium control register
         dmtc0   v0, CP0_CVMCTL_REG
         sync