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-rw-r--r--drivers/gpu/drm/i915/intel_dsi_cmd.c259
-rw-r--r--drivers/gpu/drm/i915/intel_dsi_cmd.h72
2 files changed, 0 insertions, 331 deletions
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
index 17b892a365ee..6baaa374fc89 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -96,11 +96,6 @@ static void print_stat(struct intel_dsi *intel_dsi, enum port port)
96#undef STAT_BIT 96#undef STAT_BIT
97} 97}
98 98
99enum dsi_type {
100 DSI_DCS,
101 DSI_GENERIC,
102};
103
104/* enable or disable command mode hs transmissions */ 99/* enable or disable command mode hs transmissions */
105void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable, 100void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
106 enum port port) 101 enum port port)
@@ -121,260 +116,6 @@ void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
121 intel_dsi->hs = enable; 116 intel_dsi->hs = enable;
122} 117}
123 118
124static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
125 u8 data_type, u16 data, enum port port)
126{
127 struct drm_encoder *encoder = &intel_dsi->base.base;
128 struct drm_device *dev = encoder->dev;
129 struct drm_i915_private *dev_priv = dev->dev_private;
130 u32 ctrl_reg;
131 u32 ctrl;
132 u32 mask;
133
134 DRM_DEBUG_KMS("channel %d, data_type %d, data %04x\n",
135 channel, data_type, data);
136
137 if (intel_dsi->hs) {
138 ctrl_reg = MIPI_HS_GEN_CTRL(port);
139 mask = HS_CTRL_FIFO_FULL;
140 } else {
141 ctrl_reg = MIPI_LP_GEN_CTRL(port);
142 mask = LP_CTRL_FIFO_FULL;
143 }
144
145 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50)) {
146 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
147 print_stat(intel_dsi, port);
148 }
149
150 /*
151 * Note: This function is also used for long packets, with length passed
152 * as data, since SHORT_PACKET_PARAM_SHIFT ==
153 * LONG_PACKET_WORD_COUNT_SHIFT.
154 */
155 ctrl = data << SHORT_PACKET_PARAM_SHIFT |
156 channel << VIRTUAL_CHANNEL_SHIFT |
157 data_type << DATA_TYPE_SHIFT;
158
159 I915_WRITE(ctrl_reg, ctrl);
160
161 return 0;
162}
163
164static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
165 u8 data_type, const u8 *data, int len, enum port port)
166{
167 struct drm_encoder *encoder = &intel_dsi->base.base;
168 struct drm_device *dev = encoder->dev;
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 u32 data_reg;
171 int i, j, n;
172 u32 mask;
173
174 DRM_DEBUG_KMS("channel %d, data_type %d, len %04x\n",
175 channel, data_type, len);
176
177 if (intel_dsi->hs) {
178 data_reg = MIPI_HS_GEN_DATA(port);
179 mask = HS_DATA_FIFO_FULL;
180 } else {
181 data_reg = MIPI_LP_GEN_DATA(port);
182 mask = LP_DATA_FIFO_FULL;
183 }
184
185 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50))
186 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
187
188 for (i = 0; i < len; i += n) {
189 u32 val = 0;
190 n = min_t(int, len - i, 4);
191
192 for (j = 0; j < n; j++)
193 val |= *data++ << 8 * j;
194
195 I915_WRITE(data_reg, val);
196 /* XXX: check for data fifo full, once that is set, write 4
197 * dwords, then wait for not set, then continue. */
198 }
199
200 return dsi_vc_send_short(intel_dsi, channel, data_type, len, port);
201}
202
203static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
204 int channel, const u8 *data, int len,
205 enum dsi_type type, enum port port)
206{
207 int ret;
208
209 if (len == 0) {
210 BUG_ON(type == DSI_GENERIC);
211 ret = dsi_vc_send_short(intel_dsi, channel,
212 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM,
213 0, port);
214 } else if (len == 1) {
215 ret = dsi_vc_send_short(intel_dsi, channel,
216 type == DSI_GENERIC ?
217 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
218 MIPI_DSI_DCS_SHORT_WRITE, data[0],
219 port);
220 } else if (len == 2) {
221 ret = dsi_vc_send_short(intel_dsi, channel,
222 type == DSI_GENERIC ?
223 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
224 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
225 (data[1] << 8) | data[0], port);
226 } else {
227 ret = dsi_vc_send_long(intel_dsi, channel,
228 type == DSI_GENERIC ?
229 MIPI_DSI_GENERIC_LONG_WRITE :
230 MIPI_DSI_DCS_LONG_WRITE, data, len,
231 port);
232 }
233
234 return ret;
235}
236
237int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
238 const u8 *data, int len, enum port port)
239{
240 return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS,
241 port);
242}
243
244int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
245 const u8 *data, int len, enum port port)
246{
247 return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC,
248 port);
249}
250
251static int dsi_vc_dcs_send_read_request(struct intel_dsi *intel_dsi,
252 int channel, u8 dcs_cmd, enum port port)
253{
254 return dsi_vc_send_short(intel_dsi, channel, MIPI_DSI_DCS_READ,
255 dcs_cmd, port);
256}
257
258static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
259 int channel, u8 *reqdata,
260 int reqlen, enum port port)
261{
262 u16 data;
263 u8 data_type;
264
265 switch (reqlen) {
266 case 0:
267 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
268 data = 0;
269 break;
270 case 1:
271 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
272 data = reqdata[0];
273 break;
274 case 2:
275 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
276 data = (reqdata[1] << 8) | reqdata[0];
277 break;
278 default:
279 BUG();
280 }
281
282 return dsi_vc_send_short(intel_dsi, channel, data_type, data, port);
283}
284
285static int dsi_read_data_return(struct intel_dsi *intel_dsi,
286 u8 *buf, int buflen, enum port port)
287{
288 struct drm_encoder *encoder = &intel_dsi->base.base;
289 struct drm_device *dev = encoder->dev;
290 struct drm_i915_private *dev_priv = dev->dev_private;
291 int i, len = 0;
292 u32 data_reg, val;
293
294 if (intel_dsi->hs) {
295 data_reg = MIPI_HS_GEN_DATA(port);
296 } else {
297 data_reg = MIPI_LP_GEN_DATA(port);
298 }
299
300 while (len < buflen) {
301 val = I915_READ(data_reg);
302 for (i = 0; i < 4 && len < buflen; i++, len++)
303 buf[len] = val >> 8 * i;
304 }
305
306 return len;
307}
308
309int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
310 u8 *buf, int buflen, enum port port)
311{
312 struct drm_encoder *encoder = &intel_dsi->base.base;
313 struct drm_device *dev = encoder->dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315 u32 mask;
316 int ret;
317
318 /*
319 * XXX: should issue multiple read requests and reads if request is
320 * longer than MIPI_MAX_RETURN_PKT_SIZE
321 */
322
323 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
324
325 ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd, port);
326 if (ret)
327 return ret;
328
329 mask = GEN_READ_DATA_AVAIL;
330 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50))
331 DRM_ERROR("Timeout waiting for read data.\n");
332
333 ret = dsi_read_data_return(intel_dsi, buf, buflen, port);
334 if (ret < 0)
335 return ret;
336
337 if (ret != buflen)
338 return -EIO;
339
340 return 0;
341}
342
343int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
344 u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port)
345{
346 struct drm_encoder *encoder = &intel_dsi->base.base;
347 struct drm_device *dev = encoder->dev;
348 struct drm_i915_private *dev_priv = dev->dev_private;
349 u32 mask;
350 int ret;
351
352 /*
353 * XXX: should issue multiple read requests and reads if request is
354 * longer than MIPI_MAX_RETURN_PKT_SIZE
355 */
356
357 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
358
359 ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata,
360 reqlen, port);
361 if (ret)
362 return ret;
363
364 mask = GEN_READ_DATA_AVAIL;
365 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50))
366 DRM_ERROR("Timeout waiting for read data.\n");
367
368 ret = dsi_read_data_return(intel_dsi, buf, buflen, port);
369 if (ret < 0)
370 return ret;
371
372 if (ret != buflen)
373 return -EIO;
374
375 return 0;
376}
377
378/* 119/*
379 * send a video mode command 120 * send a video mode command
380 * 121 *
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.h b/drivers/gpu/drm/i915/intel_dsi_cmd.h
index 70f24666a1f9..9a28ff58a92b 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.h
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.h
@@ -39,78 +39,6 @@
39void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable, 39void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
40 enum port port); 40 enum port port);
41 41
42int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
43 const u8 *data, int len, enum port port);
44
45int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
46 const u8 *data, int len, enum port port);
47
48int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
49 u8 *buf, int buflen, enum port port);
50
51int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
52 u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port);
53
54int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, enum port port); 42int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, enum port port);
55 43
56/* XXX: questionable write helpers */
57static inline int dsi_vc_dcs_write_0(struct intel_dsi *intel_dsi,
58 int channel, u8 dcs_cmd, enum port port)
59{
60 return dsi_vc_dcs_write(intel_dsi, channel, &dcs_cmd, 1, port);
61}
62
63static inline int dsi_vc_dcs_write_1(struct intel_dsi *intel_dsi,
64 int channel, u8 dcs_cmd, u8 param, enum port port)
65{
66 u8 buf[2] = { dcs_cmd, param };
67 return dsi_vc_dcs_write(intel_dsi, channel, buf, 2, port);
68}
69
70static inline int dsi_vc_generic_write_0(struct intel_dsi *intel_dsi,
71 int channel, enum port port)
72{
73 return dsi_vc_generic_write(intel_dsi, channel, NULL, 0, port);
74}
75
76static inline int dsi_vc_generic_write_1(struct intel_dsi *intel_dsi,
77 int channel, u8 param, enum port port)
78{
79 return dsi_vc_generic_write(intel_dsi, channel, &param, 1, port);
80}
81
82static inline int dsi_vc_generic_write_2(struct intel_dsi *intel_dsi,
83 int channel, u8 param1, u8 param2, enum port port)
84{
85 u8 buf[2] = { param1, param2 };
86 return dsi_vc_generic_write(intel_dsi, channel, buf, 2, port);
87}
88
89/* XXX: questionable read helpers */
90static inline int dsi_vc_generic_read_0(struct intel_dsi *intel_dsi,
91 int channel, u8 *buf, int buflen, enum port port)
92{
93 return dsi_vc_generic_read(intel_dsi, channel, NULL, 0, buf, buflen,
94 port);
95}
96
97static inline int dsi_vc_generic_read_1(struct intel_dsi *intel_dsi,
98 int channel, u8 param, u8 *buf,
99 int buflen, enum port port)
100{
101 return dsi_vc_generic_read(intel_dsi, channel, &param, 1, buf, buflen,
102 port);
103}
104
105static inline int dsi_vc_generic_read_2(struct intel_dsi *intel_dsi,
106 int channel, u8 param1, u8 param2,
107 u8 *buf, int buflen, enum port port)
108{
109 u8 req[2] = { param1, param2 };
110
111 return dsi_vc_generic_read(intel_dsi, channel, req, 2, buf, buflen,
112 port);
113}
114
115
116#endif /* _INTEL_DSI_DSI_H */ 44#endif /* _INTEL_DSI_DSI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-29 22:48:52 -0500