diff options
-rw-r--r-- | arch/arm/mach-iop32x/irq.c | 23 | ||||
-rw-r--r-- | arch/arm/mach-iop33x/irq.c | 27 | ||||
-rw-r--r-- | arch/arm/plat-iop/time.c | 4 | ||||
-rw-r--r-- | include/asm-arm/arch-iop32x/entry-macro.S | 3 | ||||
-rw-r--r-- | include/asm-arm/arch-iop33x/entry-macro.S | 5 |
5 files changed, 23 insertions, 39 deletions
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index 76f2d561dbc1..cdd6943ce768 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c | |||
@@ -27,12 +27,16 @@ static u32 iop321_mask /* = 0 */; | |||
27 | 27 | ||
28 | static inline void intctl_write(u32 val) | 28 | static inline void intctl_write(u32 val) |
29 | { | 29 | { |
30 | iop3xx_cp6_enable(); | ||
30 | asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); | 31 | asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); |
32 | iop3xx_cp6_disable(); | ||
31 | } | 33 | } |
32 | 34 | ||
33 | static inline void intstr_write(u32 val) | 35 | static inline void intstr_write(u32 val) |
34 | { | 36 | { |
37 | iop3xx_cp6_enable(); | ||
35 | asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val)); | 38 | asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val)); |
39 | iop3xx_cp6_disable(); | ||
36 | } | 40 | } |
37 | 41 | ||
38 | static void | 42 | static void |
@@ -61,24 +65,7 @@ struct irq_chip ext_chip = { | |||
61 | 65 | ||
62 | void __init iop321_init_irq(void) | 66 | void __init iop321_init_irq(void) |
63 | { | 67 | { |
64 | unsigned int i, tmp; | 68 | unsigned int i; |
65 | |||
66 | /* Enable access to coprocessor 6 for dealing with IRQs. | ||
67 | * From RMK: | ||
68 | * Basically, the Intel documentation here is poor. It appears that | ||
69 | * you need to set the bit to be able to access the coprocessor from | ||
70 | * SVC mode. Whether that allows access from user space or not is | ||
71 | * unclear. | ||
72 | */ | ||
73 | asm volatile ( | ||
74 | "mrc p15, 0, %0, c15, c1, 0\n\t" | ||
75 | "orr %0, %0, %1\n\t" | ||
76 | "mcr p15, 0, %0, c15, c1, 0\n\t" | ||
77 | /* The action is delayed, so we have to do this: */ | ||
78 | "mrc p15, 0, %0, c15, c1, 0\n\t" | ||
79 | "mov %0, %0\n\t" | ||
80 | "sub pc, pc, #4" | ||
81 | : "=r" (tmp) : "i" (1 << 6) ); | ||
82 | 69 | ||
83 | intctl_write(0); // disable all interrupts | 70 | intctl_write(0); // disable all interrupts |
84 | intstr_write(0); // treat all as IRQ | 71 | intstr_write(0); // treat all as IRQ |
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index bcffc33a5be8..d667439c8573 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c | |||
@@ -28,25 +28,33 @@ static u32 iop331_mask1 = 0; | |||
28 | static inline void intctl_write0(u32 val) | 28 | static inline void intctl_write0(u32 val) |
29 | { | 29 | { |
30 | // INTCTL0 | 30 | // INTCTL0 |
31 | iop3xx_cp6_enable(); | ||
31 | asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); | 32 | asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val)); |
33 | iop3xx_cp6_disable(); | ||
32 | } | 34 | } |
33 | 35 | ||
34 | static inline void intctl_write1(u32 val) | 36 | static inline void intctl_write1(u32 val) |
35 | { | 37 | { |
36 | // INTCTL1 | 38 | // INTCTL1 |
39 | iop3xx_cp6_enable(); | ||
37 | asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val)); | 40 | asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val)); |
41 | iop3xx_cp6_disable(); | ||
38 | } | 42 | } |
39 | 43 | ||
40 | static inline void intstr_write0(u32 val) | 44 | static inline void intstr_write0(u32 val) |
41 | { | 45 | { |
42 | // INTSTR0 | 46 | // INTSTR0 |
47 | iop3xx_cp6_enable(); | ||
43 | asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val)); | 48 | asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val)); |
49 | iop3xx_cp6_disable(); | ||
44 | } | 50 | } |
45 | 51 | ||
46 | static inline void intstr_write1(u32 val) | 52 | static inline void intstr_write1(u32 val) |
47 | { | 53 | { |
48 | // INTSTR1 | 54 | // INTSTR1 |
55 | iop3xx_cp6_enable(); | ||
49 | asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val)); | 56 | asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val)); |
57 | iop3xx_cp6_disable(); | ||
50 | } | 58 | } |
51 | 59 | ||
52 | static void | 60 | static void |
@@ -93,24 +101,7 @@ struct irq_chip iop331_irqchip2 = { | |||
93 | 101 | ||
94 | void __init iop331_init_irq(void) | 102 | void __init iop331_init_irq(void) |
95 | { | 103 | { |
96 | unsigned int i, tmp; | 104 | unsigned int i; |
97 | |||
98 | /* Enable access to coprocessor 6 for dealing with IRQs. | ||
99 | * From RMK: | ||
100 | * Basically, the Intel documentation here is poor. It appears that | ||
101 | * you need to set the bit to be able to access the coprocessor from | ||
102 | * SVC mode. Whether that allows access from user space or not is | ||
103 | * unclear. | ||
104 | */ | ||
105 | asm volatile ( | ||
106 | "mrc p15, 0, %0, c15, c1, 0\n\t" | ||
107 | "orr %0, %0, %1\n\t" | ||
108 | "mcr p15, 0, %0, c15, c1, 0\n\t" | ||
109 | /* The action is delayed, so we have to do this: */ | ||
110 | "mrc p15, 0, %0, c15, c1, 0\n\t" | ||
111 | "mov %0, %0\n\t" | ||
112 | "sub pc, pc, #4" | ||
113 | : "=r" (tmp) : "i" (1 << 6) ); | ||
114 | 105 | ||
115 | intctl_write0(0); // disable all interrupts | 106 | intctl_write0(0); // disable all interrupts |
116 | intctl_write1(0); | 107 | intctl_write1(0); |
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index 5730a0d7ed67..bed20f3669f4 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c | |||
@@ -51,7 +51,9 @@ iop3xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |||
51 | { | 51 | { |
52 | write_seqlock(&xtime_lock); | 52 | write_seqlock(&xtime_lock); |
53 | 53 | ||
54 | iop3xx_cp6_enable(); | ||
54 | asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1)); | 55 | asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1)); |
56 | iop3xx_cp6_disable(); | ||
55 | 57 | ||
56 | while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1) | 58 | while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1) |
57 | >= ticks_per_jiffy) { | 59 | >= ticks_per_jiffy) { |
@@ -85,10 +87,12 @@ void __init iop3xx_init_time(unsigned long tick_rate) | |||
85 | * We use timer 0 for our timer interrupt, and timer 1 as | 87 | * We use timer 0 for our timer interrupt, and timer 1 as |
86 | * monotonic counter for tracking missed jiffies. | 88 | * monotonic counter for tracking missed jiffies. |
87 | */ | 89 | */ |
90 | iop3xx_cp6_enable(); | ||
88 | asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1)); | 91 | asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1)); |
89 | asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); | 92 | asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); |
90 | asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff)); | 93 | asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff)); |
91 | asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl)); | 94 | asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl)); |
95 | iop3xx_cp6_disable(); | ||
92 | 96 | ||
93 | setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq); | 97 | setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq); |
94 | } | 98 | } |
diff --git a/include/asm-arm/arch-iop32x/entry-macro.S b/include/asm-arm/arch-iop32x/entry-macro.S index 52d9435c6a34..00038c17317a 100644 --- a/include/asm-arm/arch-iop32x/entry-macro.S +++ b/include/asm-arm/arch-iop32x/entry-macro.S | |||
@@ -17,7 +17,8 @@ | |||
17 | */ | 17 | */ |
18 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 18 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
19 | mov \irqnr, #0 | 19 | mov \irqnr, #0 |
20 | mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC | 20 | ldr \base, =IOP3XX_REG_ADDR(0x07D8) |
21 | ldr \irqstat, [\base] @ Read IINTSRC | ||
21 | cmp \irqstat, #0 | 22 | cmp \irqstat, #0 |
22 | beq 1001f | 23 | beq 1001f |
23 | clz \irqnr, \irqstat | 24 | clz \irqnr, \irqstat |
diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S index 980ec9b1ac83..57f6ea0069e4 100644 --- a/include/asm-arm/arch-iop33x/entry-macro.S +++ b/include/asm-arm/arch-iop33x/entry-macro.S | |||
@@ -17,10 +17,11 @@ | |||
17 | */ | 17 | */ |
18 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 18 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
19 | mov \irqnr, #0 | 19 | mov \irqnr, #0 |
20 | mrc p6, 0, \irqstat, c4, c0, 0 @ Read IINTSRC0 | 20 | ldr \base, =IOP3XX_REG_ADDR(0x7A0) |
21 | ldr \irqstat, [\base] @ Read IINTSRC0 | ||
21 | cmp \irqstat, #0 | 22 | cmp \irqstat, #0 |
22 | bne 1002f | 23 | bne 1002f |
23 | mrc p6, 0, \irqstat, c5, c0, 0 @ Read IINTSRC1 | 24 | ldr \irqstat, [\base, #4] @ Read IINTSRC1 |
24 | cmp \irqstat, #0 | 25 | cmp \irqstat, #0 |
25 | beq 1001f | 26 | beq 1001f |
26 | clz \irqnr, \irqstat | 27 | clz \irqnr, \irqstat |