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-rw-r--r--Documentation/devicetree/bindings/spi/spi-octeon.txt33
-rw-r--r--arch/mips/Kconfig13
-rw-r--r--arch/mips/bcm63xx/irq.c22
-rw-r--r--arch/mips/bcm63xx/setup.c6
-rw-r--r--arch/mips/configs/nlm_xlp_defconfig133
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h8
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h1
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mpi-defs.h328
-rw-r--r--arch/mips/kernel/Makefile19
-rw-r--r--arch/mips/kernel/smp-mt.c2
-rw-r--r--arch/mips/lantiq/xway/sysctrl.c2
-rw-r--r--arch/mips/lib/Makefile21
-rw-r--r--arch/mips/mm/Makefile17
-rw-r--r--arch/mips/netlogic/Kconfig15
-rw-r--r--arch/mips/netlogic/Makefile1
-rw-r--r--arch/mips/netlogic/dts/Makefile4
-rw-r--r--arch/mips/netlogic/dts/xlp_evp.dts124
-rw-r--r--arch/mips/netlogic/xlp/Makefile3
-rw-r--r--arch/mips/netlogic/xlp/of.c34
-rw-r--r--arch/mips/netlogic/xlp/platform.c108
-rw-r--r--arch/mips/netlogic/xlp/setup.c32
-rw-r--r--drivers/spi/Kconfig7
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/spi-octeon.c362
24 files changed, 1045 insertions, 251 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-octeon.txt b/Documentation/devicetree/bindings/spi/spi-octeon.txt
new file mode 100644
index 000000000000..431add192342
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-octeon.txt
@@ -0,0 +1,33 @@
1Cavium, Inc. OCTEON SOC SPI master controller.
2
3Required properties:
4- compatible : "cavium,octeon-3010-spi"
5- reg : The register base for the controller.
6- interrupts : One interrupt, used by the controller.
7- #address-cells : <1>, as required by generic SPI binding.
8- #size-cells : <0>, also as required by generic SPI binding.
9
10Child nodes as per the generic SPI binding.
11
12Example:
13
14 spi@1070000001000 {
15 compatible = "cavium,octeon-3010-spi";
16 reg = <0x10700 0x00001000 0x0 0x100>;
17 interrupts = <0 58>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 eeprom@0 {
22 compatible = "st,m95256", "atmel,at25";
23 reg = <0>;
24 spi-max-frequency = <5000000>;
25 spi-cpha;
26 spi-cpol;
27
28 pagesize = <64>;
29 size = <32768>;
30 address-width = <16>;
31 };
32 };
33
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index bbd193b9dfbb..4cd538b42a3f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -844,6 +844,7 @@ config NLM_XLP_BOARD
844 select ZONE_DMA if 64BIT 844 select ZONE_DMA if 64BIT
845 select SYNC_R4K 845 select SYNC_R4K
846 select SYS_HAS_EARLY_PRINTK 846 select SYS_HAS_EARLY_PRINTK
847 select USE_OF
847 help 848 help
848 This board is based on Netlogic XLP Processor. 849 This board is based on Netlogic XLP Processor.
849 Say Y here if you have a XLP based board. 850 Say Y here if you have a XLP based board.
@@ -1892,6 +1893,18 @@ config SIBYTE_DMA_PAGEOPS
1892config CPU_HAS_PREFETCH 1893config CPU_HAS_PREFETCH
1893 bool 1894 bool
1894 1895
1896config CPU_GENERIC_DUMP_TLB
1897 bool
1898 default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX)
1899
1900config CPU_R4K_FPU
1901 bool
1902 default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1903
1904config CPU_R4K_CACHE_TLB
1905 bool
1906 default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
1907
1895choice 1908choice
1896 prompt "MIPS MT options" 1909 prompt "MIPS MT options"
1897 1910
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 18e051ad18a5..da24c2bd9b7c 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -56,8 +56,8 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
56#define is_ext_irq_cascaded 0 56#define is_ext_irq_cascaded 0
57#define ext_irq_start 0 57#define ext_irq_start 0
58#define ext_irq_end 0 58#define ext_irq_end 0
59#define ext_irq_count 0 59#define ext_irq_count 4
60#define ext_irq_cfg_reg1 0 60#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6345
61#define ext_irq_cfg_reg2 0 61#define ext_irq_cfg_reg2 0
62#endif 62#endif
63#ifdef CONFIG_BCM63XX_CPU_6348 63#ifdef CONFIG_BCM63XX_CPU_6348
@@ -143,11 +143,15 @@ static void bcm63xx_init_irq(void)
143 irq_stat_addr += PERF_IRQSTAT_6338_REG; 143 irq_stat_addr += PERF_IRQSTAT_6338_REG;
144 irq_mask_addr += PERF_IRQMASK_6338_REG; 144 irq_mask_addr += PERF_IRQMASK_6338_REG;
145 irq_bits = 32; 145 irq_bits = 32;
146 ext_irq_count = 4;
147 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
146 break; 148 break;
147 case BCM6345_CPU_ID: 149 case BCM6345_CPU_ID:
148 irq_stat_addr += PERF_IRQSTAT_6345_REG; 150 irq_stat_addr += PERF_IRQSTAT_6345_REG;
149 irq_mask_addr += PERF_IRQMASK_6345_REG; 151 irq_mask_addr += PERF_IRQMASK_6345_REG;
150 irq_bits = 32; 152 irq_bits = 32;
153 ext_irq_count = 4;
154 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
151 break; 155 break;
152 case BCM6348_CPU_ID: 156 case BCM6348_CPU_ID:
153 irq_stat_addr += PERF_IRQSTAT_6348_REG; 157 irq_stat_addr += PERF_IRQSTAT_6348_REG;
@@ -434,7 +438,8 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
434 reg = bcm_perf_readl(regaddr); 438 reg = bcm_perf_readl(regaddr);
435 irq %= 4; 439 irq %= 4;
436 440
437 if (BCMCPU_IS_6348()) { 441 switch (bcm63xx_get_cpu_id()) {
442 case BCM6348_CPU_ID:
438 if (levelsense) 443 if (levelsense)
439 reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq); 444 reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
440 else 445 else
@@ -447,9 +452,13 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
447 reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq); 452 reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
448 else 453 else
449 reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); 454 reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
450 } 455 break;
451 456
452 if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) { 457 case BCM6328_CPU_ID:
458 case BCM6338_CPU_ID:
459 case BCM6345_CPU_ID:
460 case BCM6358_CPU_ID:
461 case BCM6368_CPU_ID:
453 if (levelsense) 462 if (levelsense)
454 reg |= EXTIRQ_CFG_LEVELSENSE(irq); 463 reg |= EXTIRQ_CFG_LEVELSENSE(irq);
455 else 464 else
@@ -462,6 +471,9 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
462 reg |= EXTIRQ_CFG_BOTHEDGE(irq); 471 reg |= EXTIRQ_CFG_BOTHEDGE(irq);
463 else 472 else
464 reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); 473 reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
474 break;
475 default:
476 BUG();
465 } 477 }
466 478
467 bcm_perf_writel(reg, regaddr); 479 bcm_perf_writel(reg, regaddr);
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index 0e74a13639cd..314231be788c 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -74,6 +74,9 @@ void bcm63xx_machine_reboot(void)
74 case BCM6338_CPU_ID: 74 case BCM6338_CPU_ID:
75 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338; 75 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
76 break; 76 break;
77 case BCM6345_CPU_ID:
78 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6345;
79 break;
77 case BCM6348_CPU_ID: 80 case BCM6348_CPU_ID:
78 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348; 81 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348;
79 break; 82 break;
@@ -83,6 +86,9 @@ void bcm63xx_machine_reboot(void)
83 } 86 }
84 87
85 for (i = 0; i < 2; i++) { 88 for (i = 0; i < 2; i++) {
89 if (!perf_regs[i])
90 break;
91
86 reg = bcm_perf_readl(perf_regs[i]); 92 reg = bcm_perf_readl(perf_regs[i]);
87 if (BCMCPU_IS_6348()) { 93 if (BCMCPU_IS_6348()) {
88 reg &= ~EXTIRQ_CFG_MASK_ALL_6348; 94 reg &= ~EXTIRQ_CFG_MASK_ALL_6348;
diff --git a/arch/mips/configs/nlm_xlp_defconfig b/arch/mips/configs/nlm_xlp_defconfig
index 28c6b276c216..43b67a7bb279 100644
--- a/arch/mips/configs/nlm_xlp_defconfig
+++ b/arch/mips/configs/nlm_xlp_defconfig
@@ -1,14 +1,12 @@
1CONFIG_NLM_XLP_BOARD=y 1CONFIG_NLM_XLP_BOARD=y
2CONFIG_64BIT=y 2CONFIG_64BIT=y
3CONFIG_PAGE_SIZE_16KB=y
4# CONFIG_HW_PERF_EVENTS is not set
3CONFIG_KSM=y 5CONFIG_KSM=y
4CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 6CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
5CONFIG_SMP=y 7CONFIG_SMP=y
6CONFIG_NO_HZ=y
7CONFIG_HIGH_RES_TIMERS=y
8# CONFIG_SECCOMP is not set 8# CONFIG_SECCOMP is not set
9CONFIG_USE_OF=y
10CONFIG_EXPERIMENTAL=y 9CONFIG_EXPERIMENTAL=y
11CONFIG_CROSS_COMPILE=""
12# CONFIG_LOCALVERSION_AUTO is not set 10# CONFIG_LOCALVERSION_AUTO is not set
13CONFIG_SYSVIPC=y 11CONFIG_SYSVIPC=y
14CONFIG_POSIX_MQUEUE=y 12CONFIG_POSIX_MQUEUE=y
@@ -19,13 +17,13 @@ CONFIG_TASK_DELAY_ACCT=y
19CONFIG_TASK_XACCT=y 17CONFIG_TASK_XACCT=y
20CONFIG_TASK_IO_ACCOUNTING=y 18CONFIG_TASK_IO_ACCOUNTING=y
21CONFIG_AUDIT=y 19CONFIG_AUDIT=y
20CONFIG_NO_HZ=y
21CONFIG_HIGH_RES_TIMERS=y
22CONFIG_CGROUPS=y 22CONFIG_CGROUPS=y
23CONFIG_NAMESPACES=y 23CONFIG_NAMESPACES=y
24CONFIG_BLK_DEV_INITRD=y 24CONFIG_BLK_DEV_INITRD=y
25CONFIG_INITRAMFS_SOURCE=""
26CONFIG_RD_BZIP2=y 25CONFIG_RD_BZIP2=y
27CONFIG_RD_LZMA=y 26CONFIG_RD_LZMA=y
28CONFIG_INITRAMFS_COMPRESSION_LZMA=y
29CONFIG_KALLSYMS_ALL=y 27CONFIG_KALLSYMS_ALL=y
30CONFIG_EMBEDDED=y 28CONFIG_EMBEDDED=y
31# CONFIG_COMPAT_BRK is not set 29# CONFIG_COMPAT_BRK is not set
@@ -35,6 +33,29 @@ CONFIG_MODULE_UNLOAD=y
35CONFIG_MODVERSIONS=y 33CONFIG_MODVERSIONS=y
36CONFIG_MODULE_SRCVERSION_ALL=y 34CONFIG_MODULE_SRCVERSION_ALL=y
37CONFIG_BLK_DEV_INTEGRITY=y 35CONFIG_BLK_DEV_INTEGRITY=y
36CONFIG_PARTITION_ADVANCED=y
37CONFIG_ACORN_PARTITION=y
38CONFIG_ACORN_PARTITION_ICS=y
39CONFIG_ACORN_PARTITION_RISCIX=y
40CONFIG_OSF_PARTITION=y
41CONFIG_AMIGA_PARTITION=y
42CONFIG_ATARI_PARTITION=y
43CONFIG_MAC_PARTITION=y
44CONFIG_BSD_DISKLABEL=y
45CONFIG_MINIX_SUBPARTITION=y
46CONFIG_SOLARIS_X86_PARTITION=y
47CONFIG_UNIXWARE_DISKLABEL=y
48CONFIG_LDM_PARTITION=y
49CONFIG_SGI_PARTITION=y
50CONFIG_ULTRIX_PARTITION=y
51CONFIG_SUN_PARTITION=y
52CONFIG_KARMA_PARTITION=y
53CONFIG_EFI_PARTITION=y
54CONFIG_SYSV68_PARTITION=y
55CONFIG_PCI=y
56CONFIG_PCI_DEBUG=y
57CONFIG_PCI_REALLOC_ENABLE_AUTO=y
58CONFIG_PCI_STUB=y
38# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 59# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
39CONFIG_BINFMT_MISC=y 60CONFIG_BINFMT_MISC=y
40CONFIG_MIPS32_COMPAT=y 61CONFIG_MIPS32_COMPAT=y
@@ -170,7 +191,6 @@ CONFIG_IP_NF_MATCH_ECN=m
170CONFIG_IP_NF_MATCH_TTL=m 191CONFIG_IP_NF_MATCH_TTL=m
171CONFIG_IP_NF_FILTER=m 192CONFIG_IP_NF_FILTER=m
172CONFIG_IP_NF_TARGET_REJECT=m 193CONFIG_IP_NF_TARGET_REJECT=m
173CONFIG_IP_NF_TARGET_LOG=m
174CONFIG_IP_NF_TARGET_ULOG=m 194CONFIG_IP_NF_TARGET_ULOG=m
175CONFIG_NF_NAT=m 195CONFIG_NF_NAT=m
176CONFIG_IP_NF_TARGET_MASQUERADE=m 196CONFIG_IP_NF_TARGET_MASQUERADE=m
@@ -186,7 +206,6 @@ CONFIG_IP_NF_ARPTABLES=m
186CONFIG_IP_NF_ARPFILTER=m 206CONFIG_IP_NF_ARPFILTER=m
187CONFIG_IP_NF_ARP_MANGLE=m 207CONFIG_IP_NF_ARP_MANGLE=m
188CONFIG_NF_CONNTRACK_IPV6=m 208CONFIG_NF_CONNTRACK_IPV6=m
189CONFIG_IP6_NF_QUEUE=m
190CONFIG_IP6_NF_IPTABLES=m 209CONFIG_IP6_NF_IPTABLES=m
191CONFIG_IP6_NF_MATCH_AH=m 210CONFIG_IP6_NF_MATCH_AH=m
192CONFIG_IP6_NF_MATCH_EUI64=m 211CONFIG_IP6_NF_MATCH_EUI64=m
@@ -197,7 +216,6 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
197CONFIG_IP6_NF_MATCH_MH=m 216CONFIG_IP6_NF_MATCH_MH=m
198CONFIG_IP6_NF_MATCH_RT=m 217CONFIG_IP6_NF_MATCH_RT=m
199CONFIG_IP6_NF_TARGET_HL=m 218CONFIG_IP6_NF_TARGET_HL=m
200CONFIG_IP6_NF_TARGET_LOG=m
201CONFIG_IP6_NF_FILTER=m 219CONFIG_IP6_NF_FILTER=m
202CONFIG_IP6_NF_TARGET_REJECT=m 220CONFIG_IP6_NF_TARGET_REJECT=m
203CONFIG_IP6_NF_MANGLE=m 221CONFIG_IP6_NF_MANGLE=m
@@ -248,9 +266,6 @@ CONFIG_IPDDP_ENCAP=y
248CONFIG_IPDDP_DECAP=y 266CONFIG_IPDDP_DECAP=y
249CONFIG_X25=m 267CONFIG_X25=m
250CONFIG_LAPB=m 268CONFIG_LAPB=m
251CONFIG_ECONET=m
252CONFIG_ECONET_AUNUDP=y
253CONFIG_ECONET_NATIVE=y
254CONFIG_WAN_ROUTER=m 269CONFIG_WAN_ROUTER=m
255CONFIG_PHONET=m 270CONFIG_PHONET=m
256CONFIG_IEEE802154=m 271CONFIG_IEEE802154=m
@@ -297,11 +312,21 @@ CONFIG_NET_ACT_SIMP=m
297CONFIG_NET_ACT_SKBEDIT=m 312CONFIG_NET_ACT_SKBEDIT=m
298CONFIG_DCB=y 313CONFIG_DCB=y
299CONFIG_NET_PKTGEN=m 314CONFIG_NET_PKTGEN=m
300# CONFIG_WIRELESS is not set
301CONFIG_DEVTMPFS=y 315CONFIG_DEVTMPFS=y
302CONFIG_DEVTMPFS_MOUNT=y 316CONFIG_DEVTMPFS_MOUNT=y
303# CONFIG_STANDALONE is not set 317# CONFIG_STANDALONE is not set
304CONFIG_CONNECTOR=y 318CONFIG_CONNECTOR=y
319CONFIG_MTD=y
320CONFIG_MTD_CMDLINE_PARTS=y
321CONFIG_MTD_CHAR=y
322CONFIG_MTD_BLOCK=y
323CONFIG_MTD_CFI=y
324CONFIG_MTD_CFI_ADV_OPTIONS=y
325CONFIG_MTD_CFI_LE_BYTE_SWAP=y
326CONFIG_MTD_CFI_GEOMETRY=y
327CONFIG_MTD_CFI_INTELEXT=y
328CONFIG_MTD_PHYSMAP=y
329CONFIG_MTD_PHYSMAP_OF=y
305CONFIG_BLK_DEV_LOOP=y 330CONFIG_BLK_DEV_LOOP=y
306CONFIG_BLK_DEV_CRYPTOLOOP=m 331CONFIG_BLK_DEV_CRYPTOLOOP=m
307CONFIG_BLK_DEV_NBD=m 332CONFIG_BLK_DEV_NBD=m
@@ -310,7 +335,6 @@ CONFIG_BLK_DEV_RAM=y
310CONFIG_BLK_DEV_RAM_SIZE=65536 335CONFIG_BLK_DEV_RAM_SIZE=65536
311CONFIG_CDROM_PKTCDVD=y 336CONFIG_CDROM_PKTCDVD=y
312CONFIG_RAID_ATTRS=m 337CONFIG_RAID_ATTRS=m
313CONFIG_SCSI=y
314CONFIG_SCSI_TGT=m 338CONFIG_SCSI_TGT=m
315CONFIG_BLK_DEV_SD=y 339CONFIG_BLK_DEV_SD=y
316CONFIG_CHR_DEV_ST=m 340CONFIG_CHR_DEV_ST=m
@@ -337,6 +361,48 @@ CONFIG_SCSI_DH_EMC=m
337CONFIG_SCSI_DH_ALUA=m 361CONFIG_SCSI_DH_ALUA=m
338CONFIG_SCSI_OSD_INITIATOR=m 362CONFIG_SCSI_OSD_INITIATOR=m
339CONFIG_SCSI_OSD_ULD=m 363CONFIG_SCSI_OSD_ULD=m
364CONFIG_ATA=y
365CONFIG_SATA_AHCI=y
366CONFIG_SATA_SIL24=y
367# CONFIG_ATA_SFF is not set
368CONFIG_NETDEVICES=y
369# CONFIG_NET_VENDOR_3COM is not set
370# CONFIG_NET_VENDOR_ADAPTEC is not set
371# CONFIG_NET_VENDOR_ALTEON is not set
372# CONFIG_NET_VENDOR_AMD is not set
373# CONFIG_NET_VENDOR_ATHEROS is not set
374# CONFIG_NET_VENDOR_BROADCOM is not set
375# CONFIG_NET_VENDOR_BROCADE is not set
376# CONFIG_NET_VENDOR_CHELSIO is not set
377# CONFIG_NET_VENDOR_DEC is not set
378# CONFIG_NET_VENDOR_DLINK is not set
379# CONFIG_NET_VENDOR_EMULEX is not set
380# CONFIG_NET_VENDOR_EXAR is not set
381# CONFIG_NET_VENDOR_HP is not set
382CONFIG_E1000E=y
383# CONFIG_NET_VENDOR_I825XX is not set
384CONFIG_SKY2=y
385# CONFIG_NET_VENDOR_MELLANOX is not set
386# CONFIG_NET_VENDOR_MICREL is not set
387# CONFIG_NET_VENDOR_MYRI is not set
388# CONFIG_NET_VENDOR_NATSEMI is not set
389# CONFIG_NET_VENDOR_NVIDIA is not set
390# CONFIG_NET_VENDOR_OKI is not set
391# CONFIG_NET_PACKET_ENGINE is not set
392# CONFIG_NET_VENDOR_QLOGIC is not set
393# CONFIG_NET_VENDOR_REALTEK is not set
394# CONFIG_NET_VENDOR_RDC is not set
395# CONFIG_NET_VENDOR_SEEQ is not set
396# CONFIG_NET_VENDOR_SILAN is not set
397# CONFIG_NET_VENDOR_SIS is not set
398# CONFIG_NET_VENDOR_SMSC is not set
399# CONFIG_NET_VENDOR_STMICRO is not set
400# CONFIG_NET_VENDOR_SUN is not set
401# CONFIG_NET_VENDOR_TEHUTI is not set
402# CONFIG_NET_VENDOR_TI is not set
403# CONFIG_NET_VENDOR_TOSHIBA is not set
404# CONFIG_NET_VENDOR_VIA is not set
405# CONFIG_NET_VENDOR_WIZNET is not set
340# CONFIG_INPUT_MOUSEDEV is not set 406# CONFIG_INPUT_MOUSEDEV is not set
341CONFIG_INPUT_EVDEV=y 407CONFIG_INPUT_EVDEV=y
342CONFIG_INPUT_EVBUG=m 408CONFIG_INPUT_EVBUG=m
@@ -360,16 +426,23 @@ CONFIG_SERIAL_8250_EXTENDED=y
360CONFIG_SERIAL_8250_MANY_PORTS=y 426CONFIG_SERIAL_8250_MANY_PORTS=y
361CONFIG_SERIAL_8250_SHARE_IRQ=y 427CONFIG_SERIAL_8250_SHARE_IRQ=y
362CONFIG_SERIAL_8250_RSA=y 428CONFIG_SERIAL_8250_RSA=y
429CONFIG_SERIAL_OF_PLATFORM=y
363CONFIG_HW_RANDOM=y 430CONFIG_HW_RANDOM=y
364CONFIG_HW_RANDOM_TIMERIOMEM=m 431CONFIG_HW_RANDOM_TIMERIOMEM=m
365CONFIG_RAW_DRIVER=m 432CONFIG_RAW_DRIVER=m
366# CONFIG_HWMON is not set 433CONFIG_I2C=y
434CONFIG_I2C_CHARDEV=y
435CONFIG_I2C_OCORES=y
436CONFIG_SENSORS_LM90=y
437CONFIG_THERMAL=y
367# CONFIG_VGA_CONSOLE is not set 438# CONFIG_VGA_CONSOLE is not set
368# CONFIG_HID_SUPPORT is not set
369# CONFIG_USB_SUPPORT is not set 439# CONFIG_USB_SUPPORT is not set
440CONFIG_RTC_CLASS=y
441CONFIG_RTC_DRV_DS1374=y
370CONFIG_UIO=y 442CONFIG_UIO=y
371CONFIG_UIO_PDRV=m 443CONFIG_UIO_PDRV=m
372CONFIG_UIO_PDRV_GENIRQ=m 444CONFIG_UIO_PDRV_GENIRQ=m
445# CONFIG_IOMMU_SUPPORT is not set
373CONFIG_EXT2_FS=y 446CONFIG_EXT2_FS=y
374CONFIG_EXT2_FS_XATTR=y 447CONFIG_EXT2_FS_XATTR=y
375CONFIG_EXT2_FS_POSIX_ACL=y 448CONFIG_EXT2_FS_POSIX_ACL=y
@@ -381,15 +454,10 @@ CONFIG_EXT4_FS=y
381CONFIG_EXT4_FS_POSIX_ACL=y 454CONFIG_EXT4_FS_POSIX_ACL=y
382CONFIG_EXT4_FS_SECURITY=y 455CONFIG_EXT4_FS_SECURITY=y
383CONFIG_GFS2_FS=m 456CONFIG_GFS2_FS=m
384CONFIG_GFS2_FS_LOCKING_DLM=y
385CONFIG_OCFS2_FS=m
386CONFIG_BTRFS_FS=m 457CONFIG_BTRFS_FS=m
387CONFIG_BTRFS_FS_POSIX_ACL=y 458CONFIG_BTRFS_FS_POSIX_ACL=y
388CONFIG_NILFS2_FS=m 459CONFIG_NILFS2_FS=m
389CONFIG_QUOTA_NETLINK_INTERFACE=y 460CONFIG_QUOTA_NETLINK_INTERFACE=y
390# CONFIG_PRINT_QUOTA_WARNING is not set
391CONFIG_QFMT_V1=m
392CONFIG_QFMT_V2=m
393CONFIG_AUTOFS4_FS=m 461CONFIG_AUTOFS4_FS=m
394CONFIG_FUSE_FS=y 462CONFIG_FUSE_FS=y
395CONFIG_CUSE=m 463CONFIG_CUSE=m
@@ -415,6 +483,7 @@ CONFIG_HFSPLUS_FS=m
415CONFIG_BEFS_FS=m 483CONFIG_BEFS_FS=m
416CONFIG_BFS_FS=m 484CONFIG_BFS_FS=m
417CONFIG_EFS_FS=m 485CONFIG_EFS_FS=m
486CONFIG_JFFS2_FS=y
418CONFIG_CRAMFS=m 487CONFIG_CRAMFS=m
419CONFIG_SQUASHFS=m 488CONFIG_SQUASHFS=m
420CONFIG_VXFS_FS=m 489CONFIG_VXFS_FS=m
@@ -427,7 +496,6 @@ CONFIG_SYSV_FS=m
427CONFIG_UFS_FS=m 496CONFIG_UFS_FS=m
428CONFIG_EXOFS_FS=m 497CONFIG_EXOFS_FS=m
429CONFIG_NFS_FS=m 498CONFIG_NFS_FS=m
430CONFIG_NFS_V3=y
431CONFIG_NFS_V3_ACL=y 499CONFIG_NFS_V3_ACL=y
432CONFIG_NFS_V4=y 500CONFIG_NFS_V4=y
433CONFIG_NFS_FSCACHE=y 501CONFIG_NFS_FSCACHE=y
@@ -450,25 +518,6 @@ CONFIG_NCPFS_NLS=y
450CONFIG_NCPFS_EXTRAS=y 518CONFIG_NCPFS_EXTRAS=y
451CONFIG_CODA_FS=m 519CONFIG_CODA_FS=m
452CONFIG_AFS_FS=m 520CONFIG_AFS_FS=m
453CONFIG_PARTITION_ADVANCED=y
454CONFIG_ACORN_PARTITION=y
455CONFIG_ACORN_PARTITION_ICS=y
456CONFIG_ACORN_PARTITION_RISCIX=y
457CONFIG_OSF_PARTITION=y
458CONFIG_AMIGA_PARTITION=y
459CONFIG_ATARI_PARTITION=y
460CONFIG_MAC_PARTITION=y
461CONFIG_BSD_DISKLABEL=y
462CONFIG_MINIX_SUBPARTITION=y
463CONFIG_SOLARIS_X86_PARTITION=y
464CONFIG_UNIXWARE_DISKLABEL=y
465CONFIG_LDM_PARTITION=y
466CONFIG_SGI_PARTITION=y
467CONFIG_ULTRIX_PARTITION=y
468CONFIG_SUN_PARTITION=y
469CONFIG_KARMA_PARTITION=y
470CONFIG_EFI_PARTITION=y
471CONFIG_SYSV68_PARTITION=y
472CONFIG_NLS=y 521CONFIG_NLS=y
473CONFIG_NLS_DEFAULT="cp437" 522CONFIG_NLS_DEFAULT="cp437"
474CONFIG_NLS_CODEPAGE_437=m 523CONFIG_NLS_CODEPAGE_437=m
@@ -518,12 +567,10 @@ CONFIG_SCHEDSTATS=y
518CONFIG_TIMER_STATS=y 567CONFIG_TIMER_STATS=y
519CONFIG_DEBUG_INFO=y 568CONFIG_DEBUG_INFO=y
520CONFIG_DEBUG_MEMORY_INIT=y 569CONFIG_DEBUG_MEMORY_INIT=y
521CONFIG_SYSCTL_SYSCALL_CHECK=y
522CONFIG_SCHED_TRACER=y 570CONFIG_SCHED_TRACER=y
523CONFIG_BLK_DEV_IO_TRACE=y 571CONFIG_BLK_DEV_IO_TRACE=y
524CONFIG_KGDB=y 572CONFIG_KGDB=y
525CONFIG_SECURITY=y 573CONFIG_SECURITY=y
526CONFIG_SECURITY_NETWORK=y
527CONFIG_LSM_MMAP_MIN_ADDR=0 574CONFIG_LSM_MMAP_MIN_ADDR=0
528CONFIG_SECURITY_SELINUX=y 575CONFIG_SECURITY_SELINUX=y
529CONFIG_SECURITY_SELINUX_BOOTPARAM=y 576CONFIG_SECURITY_SELINUX_BOOTPARAM=y
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 1ac5704623f2..dbd5b5ad07a5 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -646,10 +646,10 @@ enum bcm63xx_irq {
646#define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1) 646#define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1)
647#define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2) 647#define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2)
648#define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3) 648#define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3)
649#define BCM_6328_ENETSW_TXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 4) 649#define BCM_6328_ENETSW_TXDMA0_IRQ 0
650#define BCM_6328_ENETSW_TXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 5) 650#define BCM_6328_ENETSW_TXDMA1_IRQ 0
651#define BCM_6328_ENETSW_TXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 6) 651#define BCM_6328_ENETSW_TXDMA2_IRQ 0
652#define BCM_6328_ENETSW_TXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 7) 652#define BCM_6328_ENETSW_TXDMA3_IRQ 0
653#define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31) 653#define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31)
654#define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11) 654#define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11)
655 655
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 5e4b91866586..12963d05da86 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -161,6 +161,7 @@
161/* External Interrupt Configuration register */ 161/* External Interrupt Configuration register */
162#define PERF_EXTIRQ_CFG_REG_6328 0x18 162#define PERF_EXTIRQ_CFG_REG_6328 0x18
163#define PERF_EXTIRQ_CFG_REG_6338 0x14 163#define PERF_EXTIRQ_CFG_REG_6338 0x14
164#define PERF_EXTIRQ_CFG_REG_6345 0x14
164#define PERF_EXTIRQ_CFG_REG_6348 0x14 165#define PERF_EXTIRQ_CFG_REG_6348 0x14
165#define PERF_EXTIRQ_CFG_REG_6358 0x14 166#define PERF_EXTIRQ_CFG_REG_6358 0x14
166#define PERF_EXTIRQ_CFG_REG_6368 0x18 167#define PERF_EXTIRQ_CFG_REG_6368 0x18
diff --git a/arch/mips/include/asm/octeon/cvmx-mpi-defs.h b/arch/mips/include/asm/octeon/cvmx-mpi-defs.h
new file mode 100644
index 000000000000..4615b102625b
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-mpi-defs.h
@@ -0,0 +1,328 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2012 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_MPI_DEFS_H__
29#define __CVMX_MPI_DEFS_H__
30
31#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
32#define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
33#define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))
34#define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))
35
36union cvmx_mpi_cfg {
37 uint64_t u64;
38 struct cvmx_mpi_cfg_s {
39#ifdef __BIG_ENDIAN_BITFIELD
40 uint64_t reserved_29_63:35;
41 uint64_t clkdiv:13;
42 uint64_t csena3:1;
43 uint64_t csena2:1;
44 uint64_t csena1:1;
45 uint64_t csena0:1;
46 uint64_t cslate:1;
47 uint64_t tritx:1;
48 uint64_t idleclks:2;
49 uint64_t cshi:1;
50 uint64_t csena:1;
51 uint64_t int_ena:1;
52 uint64_t lsbfirst:1;
53 uint64_t wireor:1;
54 uint64_t clk_cont:1;
55 uint64_t idlelo:1;
56 uint64_t enable:1;
57#else
58 uint64_t enable:1;
59 uint64_t idlelo:1;
60 uint64_t clk_cont:1;
61 uint64_t wireor:1;
62 uint64_t lsbfirst:1;
63 uint64_t int_ena:1;
64 uint64_t csena:1;
65 uint64_t cshi:1;
66 uint64_t idleclks:2;
67 uint64_t tritx:1;
68 uint64_t cslate:1;
69 uint64_t csena0:1;
70 uint64_t csena1:1;
71 uint64_t csena2:1;
72 uint64_t csena3:1;
73 uint64_t clkdiv:13;
74 uint64_t reserved_29_63:35;
75#endif
76 } s;
77 struct cvmx_mpi_cfg_cn30xx {
78#ifdef __BIG_ENDIAN_BITFIELD
79 uint64_t reserved_29_63:35;
80 uint64_t clkdiv:13;
81 uint64_t reserved_12_15:4;
82 uint64_t cslate:1;
83 uint64_t tritx:1;
84 uint64_t idleclks:2;
85 uint64_t cshi:1;
86 uint64_t csena:1;
87 uint64_t int_ena:1;
88 uint64_t lsbfirst:1;
89 uint64_t wireor:1;
90 uint64_t clk_cont:1;
91 uint64_t idlelo:1;
92 uint64_t enable:1;
93#else
94 uint64_t enable:1;
95 uint64_t idlelo:1;
96 uint64_t clk_cont:1;
97 uint64_t wireor:1;
98 uint64_t lsbfirst:1;
99 uint64_t int_ena:1;
100 uint64_t csena:1;
101 uint64_t cshi:1;
102 uint64_t idleclks:2;
103 uint64_t tritx:1;
104 uint64_t cslate:1;
105 uint64_t reserved_12_15:4;
106 uint64_t clkdiv:13;
107 uint64_t reserved_29_63:35;
108#endif
109 } cn30xx;
110 struct cvmx_mpi_cfg_cn31xx {
111#ifdef __BIG_ENDIAN_BITFIELD
112 uint64_t reserved_29_63:35;
113 uint64_t clkdiv:13;
114 uint64_t reserved_11_15:5;
115 uint64_t tritx:1;
116 uint64_t idleclks:2;
117 uint64_t cshi:1;
118 uint64_t csena:1;
119 uint64_t int_ena:1;
120 uint64_t lsbfirst:1;
121 uint64_t wireor:1;
122 uint64_t clk_cont:1;
123 uint64_t idlelo:1;
124 uint64_t enable:1;
125#else
126 uint64_t enable:1;
127 uint64_t idlelo:1;
128 uint64_t clk_cont:1;
129 uint64_t wireor:1;
130 uint64_t lsbfirst:1;
131 uint64_t int_ena:1;
132 uint64_t csena:1;
133 uint64_t cshi:1;
134 uint64_t idleclks:2;
135 uint64_t tritx:1;
136 uint64_t reserved_11_15:5;
137 uint64_t clkdiv:13;
138 uint64_t reserved_29_63:35;
139#endif
140 } cn31xx;
141 struct cvmx_mpi_cfg_cn30xx cn50xx;
142 struct cvmx_mpi_cfg_cn61xx {
143#ifdef __BIG_ENDIAN_BITFIELD
144 uint64_t reserved_29_63:35;
145 uint64_t clkdiv:13;
146 uint64_t reserved_14_15:2;
147 uint64_t csena1:1;
148 uint64_t csena0:1;
149 uint64_t cslate:1;
150 uint64_t tritx:1;
151 uint64_t idleclks:2;
152 uint64_t cshi:1;
153 uint64_t reserved_6_6:1;
154 uint64_t int_ena:1;
155 uint64_t lsbfirst:1;
156 uint64_t wireor:1;
157 uint64_t clk_cont:1;
158 uint64_t idlelo:1;
159 uint64_t enable:1;
160#else
161 uint64_t enable:1;
162 uint64_t idlelo:1;
163 uint64_t clk_cont:1;
164 uint64_t wireor:1;
165 uint64_t lsbfirst:1;
166 uint64_t int_ena:1;
167 uint64_t reserved_6_6:1;
168 uint64_t cshi:1;
169 uint64_t idleclks:2;
170 uint64_t tritx:1;
171 uint64_t cslate:1;
172 uint64_t csena0:1;
173 uint64_t csena1:1;
174 uint64_t reserved_14_15:2;
175 uint64_t clkdiv:13;
176 uint64_t reserved_29_63:35;
177#endif
178 } cn61xx;
179 struct cvmx_mpi_cfg_cn66xx {
180#ifdef __BIG_ENDIAN_BITFIELD
181 uint64_t reserved_29_63:35;
182 uint64_t clkdiv:13;
183 uint64_t csena3:1;
184 uint64_t csena2:1;
185 uint64_t reserved_12_13:2;
186 uint64_t cslate:1;
187 uint64_t tritx:1;
188 uint64_t idleclks:2;
189 uint64_t cshi:1;
190 uint64_t reserved_6_6:1;
191 uint64_t int_ena:1;
192 uint64_t lsbfirst:1;
193 uint64_t wireor:1;
194 uint64_t clk_cont:1;
195 uint64_t idlelo:1;
196 uint64_t enable:1;
197#else
198 uint64_t enable:1;
199 uint64_t idlelo:1;
200 uint64_t clk_cont:1;
201 uint64_t wireor:1;
202 uint64_t lsbfirst:1;
203 uint64_t int_ena:1;
204 uint64_t reserved_6_6:1;
205 uint64_t cshi:1;
206 uint64_t idleclks:2;
207 uint64_t tritx:1;
208 uint64_t cslate:1;
209 uint64_t reserved_12_13:2;
210 uint64_t csena2:1;
211 uint64_t csena3:1;
212 uint64_t clkdiv:13;
213 uint64_t reserved_29_63:35;
214#endif
215 } cn66xx;
216 struct cvmx_mpi_cfg_cn61xx cnf71xx;
217};
218
219union cvmx_mpi_datx {
220 uint64_t u64;
221 struct cvmx_mpi_datx_s {
222#ifdef __BIG_ENDIAN_BITFIELD
223 uint64_t reserved_8_63:56;
224 uint64_t data:8;
225#else
226 uint64_t data:8;
227 uint64_t reserved_8_63:56;
228#endif
229 } s;
230 struct cvmx_mpi_datx_s cn30xx;
231 struct cvmx_mpi_datx_s cn31xx;
232 struct cvmx_mpi_datx_s cn50xx;
233 struct cvmx_mpi_datx_s cn61xx;
234 struct cvmx_mpi_datx_s cn66xx;
235 struct cvmx_mpi_datx_s cnf71xx;
236};
237
238union cvmx_mpi_sts {
239 uint64_t u64;
240 struct cvmx_mpi_sts_s {
241#ifdef __BIG_ENDIAN_BITFIELD
242 uint64_t reserved_13_63:51;
243 uint64_t rxnum:5;
244 uint64_t reserved_1_7:7;
245 uint64_t busy:1;
246#else
247 uint64_t busy:1;
248 uint64_t reserved_1_7:7;
249 uint64_t rxnum:5;
250 uint64_t reserved_13_63:51;
251#endif
252 } s;
253 struct cvmx_mpi_sts_s cn30xx;
254 struct cvmx_mpi_sts_s cn31xx;
255 struct cvmx_mpi_sts_s cn50xx;
256 struct cvmx_mpi_sts_s cn61xx;
257 struct cvmx_mpi_sts_s cn66xx;
258 struct cvmx_mpi_sts_s cnf71xx;
259};
260
261union cvmx_mpi_tx {
262 uint64_t u64;
263 struct cvmx_mpi_tx_s {
264#ifdef __BIG_ENDIAN_BITFIELD
265 uint64_t reserved_22_63:42;
266 uint64_t csid:2;
267 uint64_t reserved_17_19:3;
268 uint64_t leavecs:1;
269 uint64_t reserved_13_15:3;
270 uint64_t txnum:5;
271 uint64_t reserved_5_7:3;
272 uint64_t totnum:5;
273#else
274 uint64_t totnum:5;
275 uint64_t reserved_5_7:3;
276 uint64_t txnum:5;
277 uint64_t reserved_13_15:3;
278 uint64_t leavecs:1;
279 uint64_t reserved_17_19:3;
280 uint64_t csid:2;
281 uint64_t reserved_22_63:42;
282#endif
283 } s;
284 struct cvmx_mpi_tx_cn30xx {
285#ifdef __BIG_ENDIAN_BITFIELD
286 uint64_t reserved_17_63:47;
287 uint64_t leavecs:1;
288 uint64_t reserved_13_15:3;
289 uint64_t txnum:5;
290 uint64_t reserved_5_7:3;
291 uint64_t totnum:5;
292#else
293 uint64_t totnum:5;
294 uint64_t reserved_5_7:3;
295 uint64_t txnum:5;
296 uint64_t reserved_13_15:3;
297 uint64_t leavecs:1;
298 uint64_t reserved_17_63:47;
299#endif
300 } cn30xx;
301 struct cvmx_mpi_tx_cn30xx cn31xx;
302 struct cvmx_mpi_tx_cn30xx cn50xx;
303 struct cvmx_mpi_tx_cn61xx {
304#ifdef __BIG_ENDIAN_BITFIELD
305 uint64_t reserved_21_63:43;
306 uint64_t csid:1;
307 uint64_t reserved_17_19:3;
308 uint64_t leavecs:1;
309 uint64_t reserved_13_15:3;
310 uint64_t txnum:5;
311 uint64_t reserved_5_7:3;
312 uint64_t totnum:5;
313#else
314 uint64_t totnum:5;
315 uint64_t reserved_5_7:3;
316 uint64_t txnum:5;
317 uint64_t reserved_13_15:3;
318 uint64_t leavecs:1;
319 uint64_t reserved_17_19:3;
320 uint64_t csid:1;
321 uint64_t reserved_21_63:43;
322#endif
323 } cn61xx;
324 struct cvmx_mpi_tx_s cn66xx;
325 struct cvmx_mpi_tx_cn61xx cnf71xx;
326};
327
328#endif
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index fdaf65e1a99d..ab51dc99c03f 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -34,28 +34,11 @@ obj-$(CONFIG_MODULES) += mips_ksyms.o module.o
34 34
35obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o 35obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
36 36
37obj-$(CONFIG_CPU_LOONGSON2) += r4k_fpu.o r4k_switch.o 37obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o
38obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o
39obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o
40obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o 38obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
41obj-$(CONFIG_CPU_R4300) += r4k_fpu.o r4k_switch.o
42obj-$(CONFIG_CPU_R4X00) += r4k_fpu.o r4k_switch.o
43obj-$(CONFIG_CPU_R5000) += r4k_fpu.o r4k_switch.o
44obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o 39obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
45obj-$(CONFIG_CPU_R5432) += r4k_fpu.o r4k_switch.o
46obj-$(CONFIG_CPU_R5500) += r4k_fpu.o r4k_switch.o
47obj-$(CONFIG_CPU_R8000) += r4k_fpu.o r4k_switch.o
48obj-$(CONFIG_CPU_RM7000) += r4k_fpu.o r4k_switch.o
49obj-$(CONFIG_CPU_RM9000) += r4k_fpu.o r4k_switch.o
50obj-$(CONFIG_CPU_NEVADA) += r4k_fpu.o r4k_switch.o
51obj-$(CONFIG_CPU_R10000) += r4k_fpu.o r4k_switch.o
52obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o
53obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o 40obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
54obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o
55obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o
56obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o 41obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
57obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o
58obj-$(CONFIG_CPU_XLP) += r4k_fpu.o r4k_switch.o
59 42
60obj-$(CONFIG_SMP) += smp.o 43obj-$(CONFIG_SMP) += smp.o
61obj-$(CONFIG_SMP_UP) += smp-up.o 44obj-$(CONFIG_SMP_UP) += smp-up.o
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index ff17868734cf..2defa2bbdaa7 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -150,6 +150,7 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
150 150
151static void __cpuinit vsmp_init_secondary(void) 151static void __cpuinit vsmp_init_secondary(void)
152{ 152{
153#ifdef CONFIG_IRQ_GIC
153 extern int gic_present; 154 extern int gic_present;
154 155
155 /* This is Malta specific: IPI,performance and timer interrupts */ 156 /* This is Malta specific: IPI,performance and timer interrupts */
@@ -157,6 +158,7 @@ static void __cpuinit vsmp_init_secondary(void)
157 change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | 158 change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
158 STATUSF_IP6 | STATUSF_IP7); 159 STATUSF_IP6 | STATUSF_IP7);
159 else 160 else
161#endif
160 change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 | 162 change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
161 STATUSF_IP6 | STATUSF_IP7); 163 STATUSF_IP6 | STATUSF_IP7);
162} 164}
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 67c3a91e54e7..2917b56b6b25 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -188,10 +188,12 @@ static int clkout_enable(struct clk *clk)
188 for (i = 0; i < 4; i++) { 188 for (i = 0; i < 4; i++) {
189 if (clk->rates[i] == clk->rate) { 189 if (clk->rates[i] == clk->rate) {
190 int shift = 14 - (2 * clk->module); 190 int shift = 14 - (2 * clk->module);
191 int enable = 7 - clk->module;
191 unsigned int val = ltq_cgu_r32(ifccr); 192 unsigned int val = ltq_cgu_r32(ifccr);
192 193
193 val &= ~(3 << shift); 194 val &= ~(3 << shift);
194 val |= i << shift; 195 val |= i << shift;
196 val |= enable;
195 ltq_cgu_w32(val, ifccr); 197 ltq_cgu_w32(val, ifccr);
196 return 0; 198 return 0;
197 } 199 }
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 399a50a541d4..c4a82e841c73 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -8,28 +8,9 @@ lib-y += csum_partial.o delay.o memcpy.o memset.o \
8obj-y += iomap.o 8obj-y += iomap.o
9obj-$(CONFIG_PCI) += iomap-pci.o 9obj-$(CONFIG_PCI) += iomap-pci.o
10 10
11obj-$(CONFIG_CPU_LOONGSON2) += dump_tlb.o 11obj-$(CONFIG_CPU_GENERIC_DUMP_TLB) += dump_tlb.o
12obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
13obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
14obj-$(CONFIG_CPU_NEVADA) += dump_tlb.o
15obj-$(CONFIG_CPU_R10000) += dump_tlb.o
16obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o 12obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o
17obj-$(CONFIG_CPU_R4300) += dump_tlb.o
18obj-$(CONFIG_CPU_R4X00) += dump_tlb.o
19obj-$(CONFIG_CPU_R5000) += dump_tlb.o
20obj-$(CONFIG_CPU_R5432) += dump_tlb.o
21obj-$(CONFIG_CPU_R5500) += dump_tlb.o
22obj-$(CONFIG_CPU_R6000) +=
23obj-$(CONFIG_CPU_R8000) +=
24obj-$(CONFIG_CPU_RM7000) += dump_tlb.o
25obj-$(CONFIG_CPU_RM9000) += dump_tlb.o
26obj-$(CONFIG_CPU_SB1) += dump_tlb.o
27obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o 13obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o
28obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o
29obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o
30obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o
31obj-$(CONFIG_CPU_XLR) += dump_tlb.o
32obj-$(CONFIG_CPU_XLP) += dump_tlb.o
33 14
34# libgcc-style stuff needed in the kernel 15# libgcc-style stuff needed in the kernel
35obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o 16obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index fd6203f14f1f..90ceb963aaf1 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -11,27 +11,12 @@ obj-$(CONFIG_64BIT) += pgtable-64.o
11obj-$(CONFIG_HIGHMEM) += highmem.o 11obj-$(CONFIG_HIGHMEM) += highmem.o
12obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o 12obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
13 13
14obj-$(CONFIG_CPU_LOONGSON2) += c-r4k.o cex-gen.o tlb-r4k.o 14obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
15obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o tlb-r4k.o
16obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o tlb-r4k.o
17obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o tlb-r4k.o
18obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o tlb-r4k.o
19obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o 15obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o
20obj-$(CONFIG_CPU_R4300) += c-r4k.o cex-gen.o tlb-r4k.o
21obj-$(CONFIG_CPU_R4X00) += c-r4k.o cex-gen.o tlb-r4k.o
22obj-$(CONFIG_CPU_R5000) += c-r4k.o cex-gen.o tlb-r4k.o
23obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o tlb-r4k.o
24obj-$(CONFIG_CPU_R5500) += c-r4k.o cex-gen.o tlb-r4k.o
25obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o tlb-r8k.o 16obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o tlb-r8k.o
26obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o tlb-r4k.o
27obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o tlb-r4k.o
28obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o 17obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
29obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o 18obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o
30obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o
31obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o
32obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o 19obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
33obj-$(CONFIG_CPU_XLR) += c-r4k.o tlb-r4k.o cex-gen.o
34obj-$(CONFIG_CPU_XLP) += c-r4k.o tlb-r4k.o cex-gen.o
35 20
36obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o 21obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
37obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o 22obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig
index 75bec44b5856..8059eb76f8eb 100644
--- a/arch/mips/netlogic/Kconfig
+++ b/arch/mips/netlogic/Kconfig
@@ -1,2 +1,17 @@
1if NLM_XLP_BOARD || NLM_XLR_BOARD
2
3if NLM_XLP_BOARD
4config DT_XLP_EVP
5 bool "Built-in device tree for XLP EVP/SVP boards"
6 default y
7 help
8 Add an FDT blob for XLP EVP and SVP boards into the kernel.
9 This DTB will be used if the firmware does not pass in a DTB
10 pointer to the kernel. The corresponding DTS file is at
11 arch/mips/netlogic/dts/xlp_evp.dts
12endif
13
1config NLM_COMMON 14config NLM_COMMON
2 bool 15 bool
16
17endif
diff --git a/arch/mips/netlogic/Makefile b/arch/mips/netlogic/Makefile
index 36d169b2ca6d..7602d1386614 100644
--- a/arch/mips/netlogic/Makefile
+++ b/arch/mips/netlogic/Makefile
@@ -1,3 +1,4 @@
1obj-$(CONFIG_NLM_COMMON) += common/ 1obj-$(CONFIG_NLM_COMMON) += common/
2obj-$(CONFIG_CPU_XLR) += xlr/ 2obj-$(CONFIG_CPU_XLR) += xlr/
3obj-$(CONFIG_CPU_XLP) += xlp/ 3obj-$(CONFIG_CPU_XLP) += xlp/
4obj-$(CONFIG_CPU_XLP) += dts/
diff --git a/arch/mips/netlogic/dts/Makefile b/arch/mips/netlogic/dts/Makefile
new file mode 100644
index 000000000000..67ae3fe296f0
--- /dev/null
+++ b/arch/mips/netlogic/dts/Makefile
@@ -0,0 +1,4 @@
1obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o
2
3$(obj)/%.dtb: $(obj)/%.dts
4 $(call if_changed,dtc)
diff --git a/arch/mips/netlogic/dts/xlp_evp.dts b/arch/mips/netlogic/dts/xlp_evp.dts
new file mode 100644
index 000000000000..e14f42308064
--- /dev/null
+++ b/arch/mips/netlogic/dts/xlp_evp.dts
@@ -0,0 +1,124 @@
1/*
2 * XLP8XX Device Tree Source for EVP boards
3 */
4
5/dts-v1/;
6/ {
7 model = "netlogic,XLP-EVP";
8 compatible = "netlogic,xlp";
9 #address-cells = <2>;
10 #size-cells = <2>;
11
12 memory {
13 device_type = "memory";
14 reg = <0 0x00100000 0 0x0FF00000 // 255M at 1M
15 0 0x20000000 0 0xa0000000 // 2560M at 512M
16 0 0xe0000000 1 0x00000000>;
17 };
18
19 soc {
20 #address-cells = <2>;
21 #size-cells = <1>;
22 compatible = "simple-bus";
23 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
24 1 0 0 0x16000000 0x01000000>; // GBU chipselects
25
26 serial0: serial@30000 {
27 device_type = "serial";
28 compatible = "ns16550";
29 reg = <0 0x30100 0xa00>;
30 reg-shift = <2>;
31 reg-io-width = <4>;
32 clock-frequency = <133333333>;
33 interrupt-parent = <&pic>;
34 interrupts = <17>;
35 };
36 serial1: serial@31000 {
37 device_type = "serial";
38 compatible = "ns16550";
39 reg = <0 0x31100 0xa00>;
40 reg-shift = <2>;
41 reg-io-width = <4>;
42 clock-frequency = <133333333>;
43 interrupt-parent = <&pic>;
44 interrupts = <18>;
45 };
46 i2c0: ocores@32000 {
47 compatible = "opencores,i2c-ocores";
48 #address-cells = <1>;
49 #size-cells = <0>;
50 reg = <0 0x32100 0xa00>;
51 reg-shift = <2>;
52 reg-io-width = <4>;
53 clock-frequency = <32000000>;
54 interrupt-parent = <&pic>;
55 interrupts = <30>;
56 };
57 i2c1: ocores@33000 {
58 compatible = "opencores,i2c-ocores";
59 #address-cells = <1>;
60 #size-cells = <0>;
61 reg = <0 0x33100 0xa00>;
62 reg-shift = <2>;
63 reg-io-width = <4>;
64 clock-frequency = <32000000>;
65 interrupt-parent = <&pic>;
66 interrupts = <31>;
67
68 rtc@68 {
69 compatible = "dallas,ds1374";
70 reg = <0x68>;
71 };
72
73 dtt@4c {
74 compatible = "national,lm90";
75 reg = <0x4c>;
76 };
77 };
78 pic: pic@4000 {
79 interrupt-controller;
80 #address-cells = <0>;
81 #interrupt-cells = <1>;
82 reg = <0 0x4000 0x200>;
83 };
84
85 nor_flash@1,0 {
86 compatible = "cfi-flash";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 bank-width = <2>;
90 reg = <1 0 0x1000000>;
91
92 partition@0 {
93 label = "x-loader";
94 reg = <0x0 0x100000>; /* 1M */
95 read-only;
96 };
97
98 partition@100000 {
99 label = "u-boot";
100 reg = <0x100000 0x100000>; /* 1M */
101 };
102
103 partition@200000 {
104 label = "kernel";
105 reg = <0x200000 0x500000>; /* 5M */
106 };
107
108 partition@700000 {
109 label = "rootfs";
110 reg = <0x700000 0x800000>; /* 8M */
111 };
112
113 partition@f00000 {
114 label = "env";
115 reg = <0xf00000 0x100000>; /* 1M */
116 read-only;
117 };
118 };
119 };
120
121 chosen {
122 bootargs = "console=ttyS0,115200 rdinit=/sbin/init";
123 };
124};
diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile
index 6b4b972218f0..a84d6ed3746c 100644
--- a/arch/mips/netlogic/xlp/Makefile
+++ b/arch/mips/netlogic/xlp/Makefile
@@ -1,4 +1,3 @@
1obj-y += setup.o platform.o nlm_hal.o 1obj-y += setup.o nlm_hal.o
2obj-$(CONFIG_OF) += of.o
3obj-$(CONFIG_SMP) += wakeup.o 2obj-$(CONFIG_SMP) += wakeup.o
4obj-$(CONFIG_USB) += usb-init.o 3obj-$(CONFIG_USB) += usb-init.o
diff --git a/arch/mips/netlogic/xlp/of.c b/arch/mips/netlogic/xlp/of.c
deleted file mode 100644
index 8e3921c0c201..000000000000
--- a/arch/mips/netlogic/xlp/of.c
+++ /dev/null
@@ -1,34 +0,0 @@
1#include <linux/bootmem.h>
2#include <linux/init.h>
3#include <linux/io.h>
4#include <linux/of_fdt.h>
5#include <asm/byteorder.h>
6
7static int __init reserve_mem_mach(unsigned long addr, unsigned long size)
8{
9 return reserve_bootmem(addr, size, BOOTMEM_DEFAULT);
10}
11
12void __init free_mem_mach(unsigned long addr, unsigned long size)
13{
14 return free_bootmem(addr, size);
15}
16
17void __init device_tree_init(void)
18{
19 unsigned long base, size;
20
21 if (!initial_boot_params)
22 return;
23
24 base = virt_to_phys((void *)initial_boot_params);
25 size = be32_to_cpu(initial_boot_params->totalsize);
26
27 /* Before we do anything, lets reserve the dt blob */
28 reserve_mem_mach(base, size);
29
30 unflatten_device_tree();
31
32 /* free the space reserved for the dt blob */
33 free_mem_mach(base, size);
34}
diff --git a/arch/mips/netlogic/xlp/platform.c b/arch/mips/netlogic/xlp/platform.c
deleted file mode 100644
index 2c510d585447..000000000000
--- a/arch/mips/netlogic/xlp/platform.c
+++ /dev/null
@@ -1,108 +0,0 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/dma-mapping.h>
36#include <linux/kernel.h>
37#include <linux/delay.h>
38#include <linux/init.h>
39#include <linux/platform_device.h>
40#include <linux/serial.h>
41#include <linux/serial_8250.h>
42#include <linux/pci.h>
43#include <linux/serial_reg.h>
44#include <linux/spinlock.h>
45
46#include <asm/time.h>
47#include <asm/addrspace.h>
48#include <asm/netlogic/haldefs.h>
49#include <asm/netlogic/xlp-hal/iomap.h>
50#include <asm/netlogic/xlp-hal/xlp.h>
51#include <asm/netlogic/xlp-hal/pic.h>
52#include <asm/netlogic/xlp-hal/uart.h>
53
54static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset)
55{
56 return nlm_read_reg(p->iobase, offset);
57}
58
59static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value)
60{
61 nlm_write_reg(p->iobase, offset, value);
62}
63
64#define PORT(_irq) \
65 { \
66 .irq = _irq, \
67 .regshift = 2, \
68 .iotype = UPIO_MEM32, \
69 .flags = (UPF_SKIP_TEST|UPF_FIXED_TYPE|\
70 UPF_BOOT_AUTOCONF), \
71 .uartclk = XLP_IO_CLK, \
72 .type = PORT_16550A, \
73 .serial_in = nlm_xlp_uart_in, \
74 .serial_out = nlm_xlp_uart_out, \
75 }
76
77static struct plat_serial8250_port xlp_uart_data[] = {
78 PORT(PIC_UART_0_IRQ),
79 PORT(PIC_UART_1_IRQ),
80 {},
81};
82
83static struct platform_device uart_device = {
84 .name = "serial8250",
85 .id = PLAT8250_DEV_PLATFORM,
86 .dev = {
87 .platform_data = xlp_uart_data,
88 },
89};
90
91static int __init nlm_platform_uart_init(void)
92{
93 unsigned long mmio;
94
95 mmio = (unsigned long)nlm_get_uart_regbase(0, 0);
96 xlp_uart_data[0].iobase = mmio;
97 xlp_uart_data[0].membase = (void __iomem *)mmio;
98 xlp_uart_data[0].mapbase = mmio;
99
100 mmio = (unsigned long)nlm_get_uart_regbase(0, 1);
101 xlp_uart_data[1].iobase = mmio;
102 xlp_uart_data[1].membase = (void __iomem *)mmio;
103 xlp_uart_data[1].mapbase = mmio;
104
105 return platform_device_register(&uart_device);
106}
107
108arch_initcall(nlm_platform_uart_init);
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
index 3dec9f28b65b..d8997098defd 100644
--- a/arch/mips/netlogic/xlp/setup.c
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -35,6 +35,7 @@
35#include <linux/kernel.h> 35#include <linux/kernel.h>
36#include <linux/serial_8250.h> 36#include <linux/serial_8250.h>
37#include <linux/pm.h> 37#include <linux/pm.h>
38#include <linux/bootmem.h>
38 39
39#include <asm/reboot.h> 40#include <asm/reboot.h>
40#include <asm/time.h> 41#include <asm/time.h>
@@ -56,6 +57,7 @@ unsigned long nlm_common_ebase = 0x0;
56/* default to uniprocessor */ 57/* default to uniprocessor */
57uint32_t nlm_coremask = 1, nlm_cpumask = 1; 58uint32_t nlm_coremask = 1, nlm_cpumask = 1;
58int nlm_threads_per_core = 1; 59int nlm_threads_per_core = 1;
60extern u32 __dtb_start[];
59 61
60static void nlm_linux_exit(void) 62static void nlm_linux_exit(void)
61{ 63{
@@ -96,9 +98,18 @@ void __init prom_init(void)
96{ 98{
97 void *fdtp; 99 void *fdtp;
98 100
99 fdtp = (void *)(long)fw_arg0;
100 xlp_mmu_init(); 101 xlp_mmu_init();
101 nlm_hal_init(); 102 nlm_hal_init();
103
104 /*
105 * If no FDT pointer is passed in, use the built-in FDT.
106 * device_tree_init() does not handle CKSEG0 pointers in
107 * 64-bit, so convert pointer.
108 */
109 fdtp = (void *)(long)fw_arg0;
110 if (!fdtp)
111 fdtp = __dtb_start;
112 fdtp = phys_to_virt(__pa(fdtp));
102 early_init_devtree(fdtp); 113 early_init_devtree(fdtp);
103 114
104 nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1)); 115 nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
@@ -112,6 +123,25 @@ void __init prom_init(void)
112#endif 123#endif
113} 124}
114 125
126void __init device_tree_init(void)
127{
128 unsigned long base, size;
129
130 if (!initial_boot_params)
131 return;
132
133 base = virt_to_phys((void *)initial_boot_params);
134 size = be32_to_cpu(initial_boot_params->totalsize);
135
136 /* Before we do anything, lets reserve the dt blob */
137 reserve_bootmem(base, size, BOOTMEM_DEFAULT);
138
139 unflatten_device_tree();
140
141 /* free the space reserved for the dt blob */
142 free_bootmem(base, size);
143}
144
115static struct of_device_id __initdata xlp_ids[] = { 145static struct of_device_id __initdata xlp_ids[] = {
116 { .compatible = "simple-bus", }, 146 { .compatible = "simple-bus", },
117 {}, 147 {},
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 5f84b5563c2d..d654f88f4cfb 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -237,6 +237,13 @@ config SPI_OC_TINY
237 help 237 help
238 This is the driver for OpenCores tiny SPI master controller. 238 This is the driver for OpenCores tiny SPI master controller.
239 239
240config SPI_OCTEON
241 tristate "Cavium OCTEON SPI controller"
242 depends on CPU_CAVIUM_OCTEON
243 help
244 SPI host driver for the hardware found on some Cavium OCTEON
245 SOCs.
246
240config SPI_OMAP_UWIRE 247config SPI_OMAP_UWIRE
241 tristate "OMAP1 MicroWire" 248 tristate "OMAP1 MicroWire"
242 depends on ARCH_OMAP1 249 depends on ARCH_OMAP1
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3920dcf4c740..93d87bcdf3f5 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
38obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o 38obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
39obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o 39obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
40obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o 40obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
41obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o
41obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o 42obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o
42obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o 43obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o
43obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o 44obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o
diff --git a/drivers/spi/spi-octeon.c b/drivers/spi/spi-octeon.c
new file mode 100644
index 000000000000..ea8fb2efb0f8
--- /dev/null
+++ b/drivers/spi/spi-octeon.c
@@ -0,0 +1,362 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011, 2012 Cavium, Inc.
7 */
8
9#include <linux/platform_device.h>
10#include <linux/interrupt.h>
11#include <linux/spi/spi.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/of.h>
17
18#include <asm/octeon/octeon.h>
19#include <asm/octeon/cvmx-mpi-defs.h>
20
21#define OCTEON_SPI_CFG 0
22#define OCTEON_SPI_STS 0x08
23#define OCTEON_SPI_TX 0x10
24#define OCTEON_SPI_DAT0 0x80
25
26#define OCTEON_SPI_MAX_BYTES 9
27
28#define OCTEON_SPI_MAX_CLOCK_HZ 16000000
29
30struct octeon_spi {
31 struct spi_master *my_master;
32 u64 register_base;
33 u64 last_cfg;
34 u64 cs_enax;
35};
36
37struct octeon_spi_setup {
38 u32 max_speed_hz;
39 u8 chip_select;
40 u8 mode;
41 u8 bits_per_word;
42};
43
44static void octeon_spi_wait_ready(struct octeon_spi *p)
45{
46 union cvmx_mpi_sts mpi_sts;
47 unsigned int loops = 0;
48
49 do {
50 if (loops++)
51 __delay(500);
52 mpi_sts.u64 = cvmx_read_csr(p->register_base + OCTEON_SPI_STS);
53 } while (mpi_sts.s.busy);
54}
55
56static int octeon_spi_do_transfer(struct octeon_spi *p,
57 struct spi_message *msg,
58 struct spi_transfer *xfer,
59 bool last_xfer)
60{
61 union cvmx_mpi_cfg mpi_cfg;
62 union cvmx_mpi_tx mpi_tx;
63 unsigned int clkdiv;
64 unsigned int speed_hz;
65 int mode;
66 bool cpha, cpol;
67 int bits_per_word;
68 const u8 *tx_buf;
69 u8 *rx_buf;
70 int len;
71 int i;
72
73 struct octeon_spi_setup *msg_setup = spi_get_ctldata(msg->spi);
74
75 speed_hz = msg_setup->max_speed_hz;
76 mode = msg_setup->mode;
77 cpha = mode & SPI_CPHA;
78 cpol = mode & SPI_CPOL;
79 bits_per_word = msg_setup->bits_per_word;
80
81 if (xfer->speed_hz)
82 speed_hz = xfer->speed_hz;
83 if (xfer->bits_per_word)
84 bits_per_word = xfer->bits_per_word;
85
86 if (speed_hz > OCTEON_SPI_MAX_CLOCK_HZ)
87 speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
88
89 clkdiv = octeon_get_io_clock_rate() / (2 * speed_hz);
90
91 mpi_cfg.u64 = 0;
92
93 mpi_cfg.s.clkdiv = clkdiv;
94 mpi_cfg.s.cshi = (mode & SPI_CS_HIGH) ? 1 : 0;
95 mpi_cfg.s.lsbfirst = (mode & SPI_LSB_FIRST) ? 1 : 0;
96 mpi_cfg.s.wireor = (mode & SPI_3WIRE) ? 1 : 0;
97 mpi_cfg.s.idlelo = cpha != cpol;
98 mpi_cfg.s.cslate = cpha ? 1 : 0;
99 mpi_cfg.s.enable = 1;
100
101 if (msg_setup->chip_select < 4)
102 p->cs_enax |= 1ull << (12 + msg_setup->chip_select);
103 mpi_cfg.u64 |= p->cs_enax;
104
105 if (mpi_cfg.u64 != p->last_cfg) {
106 p->last_cfg = mpi_cfg.u64;
107 cvmx_write_csr(p->register_base + OCTEON_SPI_CFG, mpi_cfg.u64);
108 }
109 tx_buf = xfer->tx_buf;
110 rx_buf = xfer->rx_buf;
111 len = xfer->len;
112 while (len > OCTEON_SPI_MAX_BYTES) {
113 for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
114 u8 d;
115 if (tx_buf)
116 d = *tx_buf++;
117 else
118 d = 0;
119 cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d);
120 }
121 mpi_tx.u64 = 0;
122 mpi_tx.s.csid = msg_setup->chip_select;
123 mpi_tx.s.leavecs = 1;
124 mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
125 mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
126 cvmx_write_csr(p->register_base + OCTEON_SPI_TX, mpi_tx.u64);
127
128 octeon_spi_wait_ready(p);
129 if (rx_buf)
130 for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
131 u64 v = cvmx_read_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
132 *rx_buf++ = (u8)v;
133 }
134 len -= OCTEON_SPI_MAX_BYTES;
135 }
136
137 for (i = 0; i < len; i++) {
138 u8 d;
139 if (tx_buf)
140 d = *tx_buf++;
141 else
142 d = 0;
143 cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d);
144 }
145
146 mpi_tx.u64 = 0;
147 mpi_tx.s.csid = msg_setup->chip_select;
148 if (last_xfer)
149 mpi_tx.s.leavecs = xfer->cs_change;
150 else
151 mpi_tx.s.leavecs = !xfer->cs_change;
152 mpi_tx.s.txnum = tx_buf ? len : 0;
153 mpi_tx.s.totnum = len;
154 cvmx_write_csr(p->register_base + OCTEON_SPI_TX, mpi_tx.u64);
155
156 octeon_spi_wait_ready(p);
157 if (rx_buf)
158 for (i = 0; i < len; i++) {
159 u64 v = cvmx_read_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
160 *rx_buf++ = (u8)v;
161 }
162
163 if (xfer->delay_usecs)
164 udelay(xfer->delay_usecs);
165
166 return xfer->len;
167}
168
169static int octeon_spi_validate_bpw(struct spi_device *spi, u32 speed)
170{
171 switch (speed) {
172 case 8:
173 break;
174 default:
175 dev_err(&spi->dev, "Error: %d bits per word not supported\n",
176 speed);
177 return -EINVAL;
178 }
179 return 0;
180}
181
182static int octeon_spi_transfer_one_message(struct spi_master *master,
183 struct spi_message *msg)
184{
185 struct octeon_spi *p = spi_master_get_devdata(master);
186 unsigned int total_len = 0;
187 int status = 0;
188 struct spi_transfer *xfer;
189
190 /*
191 * We better have set the configuration via a call to .setup
192 * before we get here.
193 */
194 if (spi_get_ctldata(msg->spi) == NULL) {
195 status = -EINVAL;
196 goto err;
197 }
198
199 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
200 if (xfer->bits_per_word) {
201 status = octeon_spi_validate_bpw(msg->spi,
202 xfer->bits_per_word);
203 if (status)
204 goto err;
205 }
206 }
207
208 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
209 bool last_xfer = &xfer->transfer_list == msg->transfers.prev;
210 int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer);
211 if (r < 0) {
212 status = r;
213 goto err;
214 }
215 total_len += r;
216 }
217err:
218 msg->status = status;
219 msg->actual_length = total_len;
220 spi_finalize_current_message(master);
221 return status;
222}
223
224static struct octeon_spi_setup *octeon_spi_new_setup(struct spi_device *spi)
225{
226 struct octeon_spi_setup *setup = kzalloc(sizeof(*setup), GFP_KERNEL);
227 if (!setup)
228 return NULL;
229
230 setup->max_speed_hz = spi->max_speed_hz;
231 setup->chip_select = spi->chip_select;
232 setup->mode = spi->mode;
233 setup->bits_per_word = spi->bits_per_word;
234 return setup;
235}
236
237static int octeon_spi_setup(struct spi_device *spi)
238{
239 int r;
240 struct octeon_spi_setup *new_setup;
241 struct octeon_spi_setup *old_setup = spi_get_ctldata(spi);
242
243 r = octeon_spi_validate_bpw(spi, spi->bits_per_word);
244 if (r)
245 return r;
246
247 new_setup = octeon_spi_new_setup(spi);
248 if (!new_setup)
249 return -ENOMEM;
250
251 spi_set_ctldata(spi, new_setup);
252 kfree(old_setup);
253
254 return 0;
255}
256
257static void octeon_spi_cleanup(struct spi_device *spi)
258{
259 struct octeon_spi_setup *old_setup = spi_get_ctldata(spi);
260 spi_set_ctldata(spi, NULL);
261 kfree(old_setup);
262}
263
264static int octeon_spi_nop_transfer_hardware(struct spi_master *master)
265{
266 return 0;
267}
268
269static int __devinit octeon_spi_probe(struct platform_device *pdev)
270{
271
272 struct resource *res_mem;
273 struct spi_master *master;
274 struct octeon_spi *p;
275 int err = -ENOENT;
276
277 master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi));
278 if (!master)
279 return -ENOMEM;
280 p = spi_master_get_devdata(master);
281 platform_set_drvdata(pdev, p);
282 p->my_master = master;
283
284 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
285
286 if (res_mem == NULL) {
287 dev_err(&pdev->dev, "found no memory resource\n");
288 err = -ENXIO;
289 goto fail;
290 }
291 if (!devm_request_mem_region(&pdev->dev, res_mem->start,
292 resource_size(res_mem), res_mem->name)) {
293 dev_err(&pdev->dev, "request_mem_region failed\n");
294 goto fail;
295 }
296 p->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start,
297 resource_size(res_mem));
298
299 /* Dynamic bus numbering */
300 master->bus_num = -1;
301 master->num_chipselect = 4;
302 master->mode_bits = SPI_CPHA |
303 SPI_CPOL |
304 SPI_CS_HIGH |
305 SPI_LSB_FIRST |
306 SPI_3WIRE;
307
308 master->setup = octeon_spi_setup;
309 master->cleanup = octeon_spi_cleanup;
310 master->prepare_transfer_hardware = octeon_spi_nop_transfer_hardware;
311 master->transfer_one_message = octeon_spi_transfer_one_message;
312 master->unprepare_transfer_hardware = octeon_spi_nop_transfer_hardware;
313
314 master->dev.of_node = pdev->dev.of_node;
315 err = spi_register_master(master);
316 if (err) {
317 dev_err(&pdev->dev, "register master failed: %d\n", err);
318 goto fail;
319 }
320
321 dev_info(&pdev->dev, "OCTEON SPI bus driver\n");
322
323 return 0;
324fail:
325 spi_master_put(master);
326 return err;
327}
328
329static int __devexit octeon_spi_remove(struct platform_device *pdev)
330{
331 struct octeon_spi *p = platform_get_drvdata(pdev);
332 u64 register_base = p->register_base;
333
334 spi_unregister_master(p->my_master);
335
336 /* Clear the CSENA* and put everything in a known state. */
337 cvmx_write_csr(register_base + OCTEON_SPI_CFG, 0);
338
339 return 0;
340}
341
342static struct of_device_id octeon_spi_match[] = {
343 { .compatible = "cavium,octeon-3010-spi", },
344 {},
345};
346MODULE_DEVICE_TABLE(of, octeon_spi_match);
347
348static struct platform_driver octeon_spi_driver = {
349 .driver = {
350 .name = "spi-octeon",
351 .owner = THIS_MODULE,
352 .of_match_table = octeon_spi_match,
353 },
354 .probe = octeon_spi_probe,
355 .remove = __devexit_p(octeon_spi_remove),
356};
357
358module_platform_driver(octeon_spi_driver);
359
360MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
361MODULE_AUTHOR("David Daney");
362MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-30 06:56:50 -0500