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-rw-r--r--arch/mips/Kconfig26
-rw-r--r--arch/mips/Makefile7
-rw-r--r--arch/mips/basler/excite/Makefile9
-rw-r--r--arch/mips/basler/excite/excite_dbg_io.c122
-rw-r--r--arch/mips/basler/excite/excite_device.c404
-rw-r--r--arch/mips/basler/excite/excite_flashtest.c294
-rw-r--r--arch/mips/basler/excite/excite_fpga.h80
-rw-r--r--arch/mips/basler/excite/excite_iodev.c183
-rw-r--r--arch/mips/basler/excite/excite_iodev.h10
-rw-r--r--arch/mips/basler/excite/excite_irq.c129
-rw-r--r--arch/mips/basler/excite/excite_procfs.c81
-rw-r--r--arch/mips/basler/excite/excite_prom.c148
-rw-r--r--arch/mips/basler/excite/excite_setup.c307
-rw-r--r--arch/mips/configs/excite_defconfig1211
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-excite.c36
-rw-r--r--arch/mips/pci/ops-titan.c25
-rw-r--r--arch/mips/pci/pci-excite.c149
-rw-r--r--include/asm-mips/bootinfo.h1
-rw-r--r--include/asm-mips/mach-excite/cpu-feature-overrides.h40
-rw-r--r--include/asm-mips/mach-excite/excite.h155
-rw-r--r--include/asm-mips/mach-excite/excite_nandflash.h7
-rw-r--r--include/asm-mips/mach-excite/rm9k_eth.h23
-rw-r--r--include/asm-mips/mach-excite/rm9k_wdt.h12
-rw-r--r--include/asm-mips/mach-excite/rm9k_xicap.h16
-rw-r--r--include/asm-mips/rm9k-ocd.h56
-rw-r--r--include/asm-mips/war.h5
27 files changed, 3528 insertions, 9 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index db3d008732c6..50274fcacde0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -119,6 +119,32 @@ config MIPS_MIRAGE
119 select SYS_HAS_CPU_MIPS32_R1 119 select SYS_HAS_CPU_MIPS32_R1
120 select SYS_SUPPORTS_LITTLE_ENDIAN 120 select SYS_SUPPORTS_LITTLE_ENDIAN
121 121
122config BASLER_EXCITE
123 bool "Basler eXcite smart camera support"
124 select DMA_COHERENT
125 select HW_HAS_PCI
126 select IRQ_CPU
127 select IRQ_CPU_RM7K
128 select IRQ_CPU_RM9K
129 select SERIAL_RM9000
130 select SYS_HAS_CPU_RM9000
131 select SYS_SUPPORTS_32BIT_KERNEL
132 select SYS_SUPPORTS_64BIT_KERNEL
133 select SYS_SUPPORTS_BIG_ENDIAN
134 help
135 The eXcite is a smart camera platform manufactured by
136 Basler Vision Technologies AG
137
138config BASLER_EXCITE_PROTOTYPE
139 bool "Support for pre-release units"
140 depends on BASLER_EXCITE
141 default n
142 help
143 Pre-series (prototype) units are different from later ones in
144 some ways. Select this option if you have one of these. Please
145 note that a kernel built with this option selected will not be
146 able to run on normal units.
147
122config MIPS_COBALT 148config MIPS_COBALT
123 bool "Cobalt Server" 149 bool "Cobalt Server"
124 select DMA_NONCOHERENT 150 select DMA_NONCOHERENT
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 207197b91a53..d5930148495a 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -388,6 +388,13 @@ cflags-$(CONFIG_MOMENCO_OCELOT_3) += -Iinclude/asm-mips/mach-ocelot3
388load-$(CONFIG_MOMENCO_OCELOT_3) += 0xffffffff80100000 388load-$(CONFIG_MOMENCO_OCELOT_3) += 0xffffffff80100000
389 389
390# 390#
391# Basler eXcite
392#
393core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/
394cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite
395load-$(CONFIG_BASLER_EXCITE) += 0x80100000
396
397#
391# Momentum Jaguar ATX 398# Momentum Jaguar ATX
392# 399#
393core-$(CONFIG_MOMENCO_JAGUAR_ATX) += arch/mips/momentum/jaguar_atx/ 400core-$(CONFIG_MOMENCO_JAGUAR_ATX) += arch/mips/momentum/jaguar_atx/
diff --git a/arch/mips/basler/excite/Makefile b/arch/mips/basler/excite/Makefile
new file mode 100644
index 000000000000..519142c2e4ef
--- /dev/null
+++ b/arch/mips/basler/excite/Makefile
@@ -0,0 +1,9 @@
1#
2# Makefile for Basler eXcite
3#
4
5obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \
6 excite_device.o excite_procfs.o
7
8obj-$(CONFIG_KGDB) += excite_dbg_io.o
9obj-m += excite_iodev.o
diff --git a/arch/mips/basler/excite/excite_dbg_io.c b/arch/mips/basler/excite/excite_dbg_io.c
new file mode 100644
index 000000000000..83f6bddf578b
--- /dev/null
+++ b/arch/mips/basler/excite/excite_dbg_io.c
@@ -0,0 +1,122 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/config.h>
21#include <linux/linkage.h>
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <asm/gdb-stub.h>
25#include <asm/rm9k-ocd.h>
26#include <excite.h>
27
28#if defined(CONFIG_SERIAL_8250) && CONFIG_SERIAL_8250_NR_UARTS > 1
29#error Debug port used by serial driver
30#endif
31
32#define UART_CLK 25000000
33#define BASE_BAUD (UART_CLK / 16)
34#define REGISTER_BASE_0 0x0208UL
35#define REGISTER_BASE_1 0x0238UL
36
37#define REGISTER_BASE_DBG REGISTER_BASE_1
38
39#define CPRR 0x0004
40#define UACFG 0x0200
41#define UAINTS 0x0204
42#define UARBR (REGISTER_BASE_DBG + 0x0000)
43#define UATHR (REGISTER_BASE_DBG + 0x0004)
44#define UADLL (REGISTER_BASE_DBG + 0x0008)
45#define UAIER (REGISTER_BASE_DBG + 0x000c)
46#define UADLH (REGISTER_BASE_DBG + 0x0010)
47#define UAIIR (REGISTER_BASE_DBG + 0x0014)
48#define UAFCR (REGISTER_BASE_DBG + 0x0018)
49#define UALCR (REGISTER_BASE_DBG + 0x001c)
50#define UAMCR (REGISTER_BASE_DBG + 0x0020)
51#define UALSR (REGISTER_BASE_DBG + 0x0024)
52#define UAMSR (REGISTER_BASE_DBG + 0x0028)
53#define UASCR (REGISTER_BASE_DBG + 0x002c)
54
55#define PARITY_NONE 0
56#define PARITY_ODD 0x08
57#define PARITY_EVEN 0x18
58#define PARITY_MARK 0x28
59#define PARITY_SPACE 0x38
60
61#define DATA_5BIT 0x0
62#define DATA_6BIT 0x1
63#define DATA_7BIT 0x2
64#define DATA_8BIT 0x3
65
66#define STOP_1BIT 0x0
67#define STOP_2BIT 0x4
68
69#define BAUD_DBG 57600
70#define PARITY_DBG PARITY_NONE
71#define DATA_DBG DATA_8BIT
72#define STOP_DBG STOP_1BIT
73
74/* Initialize the serial port for KGDB debugging */
75void __init excite_kgdb_init(void)
76{
77 const u32 divisor = BASE_BAUD / BAUD_DBG;
78
79 /* Take the UART out of reset */
80 titan_writel(0x00ff1cff, CPRR);
81 titan_writel(0x00000000, UACFG);
82 titan_writel(0x00000002, UACFG);
83
84 titan_writel(0x0, UALCR);
85 titan_writel(0x0, UAIER);
86
87 /* Disable FIFOs */
88 titan_writel(0x00, UAFCR);
89
90 titan_writel(0x80, UALCR);
91 titan_writel(divisor & 0xff, UADLL);
92 titan_writel((divisor & 0xff00) >> 8, UADLH);
93 titan_writel(0x0, UALCR);
94
95 titan_writel(DATA_DBG | PARITY_DBG | STOP_DBG, UALCR);
96
97 /* Enable receiver interrupt */
98 titan_readl(UARBR);
99 titan_writel(0x1, UAIER);
100}
101
102int getDebugChar(void)
103{
104 while (!(titan_readl(UALSR) & 0x1));
105 return titan_readl(UARBR);
106}
107
108int putDebugChar(int data)
109{
110 while (!(titan_readl(UALSR) & 0x20));
111 titan_writel(data, UATHR);
112 return 1;
113}
114
115/* KGDB interrupt handler */
116asmlinkage void excite_kgdb_inthdl(struct pt_regs *regs)
117{
118 if (unlikely(
119 ((titan_readl(UAIIR) & 0x7) == 4)
120 && ((titan_readl(UARBR) & 0xff) == 0x3)))
121 set_async_breakpoint(&regs->cp0_epc);
122}
diff --git a/arch/mips/basler/excite/excite_device.c b/arch/mips/basler/excite/excite_device.c
new file mode 100644
index 000000000000..34ec76716fa0
--- /dev/null
+++ b/arch/mips/basler/excite/excite_device.c
@@ -0,0 +1,404 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/config.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/ioport.h>
25#include <linux/err.h>
26#include <linux/jiffies.h>
27#include <linux/sched.h>
28#include <asm/types.h>
29#include <asm/rm9k-ocd.h>
30
31#include <excite.h>
32#include <rm9k_eth.h>
33#include <rm9k_wdt.h>
34#include <rm9k_xicap.h>
35#include <excite_nandflash.h>
36
37#include "excite_iodev.h"
38
39#define RM9K_GE_UNIT 0
40#define XICAP_UNIT 0
41#define NAND_UNIT 0
42
43#define DLL_TIMEOUT 3 /* seconds */
44
45
46#define RINIT(__start__, __end__, __name__, __parent__) { \
47 .name = __name__ "_0", \
48 .start = (__start__), \
49 .end = (__end__), \
50 .flags = 0, \
51 .parent = (__parent__) \
52}
53
54#define RINIT_IRQ(__irq__, __name__) { \
55 .name = __name__ "_0", \
56 .start = (__irq__), \
57 .end = (__irq__), \
58 .flags = IORESOURCE_IRQ, \
59 .parent = NULL \
60}
61
62
63
64enum {
65 slice_xicap,
66 slice_eth
67};
68
69
70
71static struct resource
72 excite_ctr_resource = {
73 .name = "GPI counters",
74 .start = 0,
75 .end = 5,
76 .flags = 0,
77 .parent = NULL,
78 .sibling = NULL,
79 .child = NULL
80 },
81 excite_gpislice_resource = {
82 .name = "GPI slices",
83 .start = 0,
84 .end = 1,
85 .flags = 0,
86 .parent = NULL,
87 .sibling = NULL,
88 .child = NULL
89 },
90 excite_mdio_channel_resource = {
91 .name = "MDIO channels",
92 .start = 0,
93 .end = 1,
94 .flags = 0,
95 .parent = NULL,
96 .sibling = NULL,
97 .child = NULL
98 },
99 excite_fifomem_resource = {
100 .name = "FIFO memory",
101 .start = 0,
102 .end = 767,
103 .flags = 0,
104 .parent = NULL,
105 .sibling = NULL,
106 .child = NULL
107 },
108 excite_scram_resource = {
109 .name = "Scratch RAM",
110 .start = EXCITE_PHYS_SCRAM,
111 .end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
112 .flags = IORESOURCE_MEM,
113 .parent = NULL,
114 .sibling = NULL,
115 .child = NULL
116 },
117 excite_fpga_resource = {
118 .name = "System FPGA",
119 .start = EXCITE_PHYS_FPGA,
120 .end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
121 .flags = IORESOURCE_MEM,
122 .parent = NULL,
123 .sibling = NULL,
124 .child = NULL
125 },
126 excite_nand_resource = {
127 .name = "NAND flash control",
128 .start = EXCITE_PHYS_NAND,
129 .end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
130 .flags = IORESOURCE_MEM,
131 .parent = NULL,
132 .sibling = NULL,
133 .child = NULL
134 },
135 excite_titan_resource = {
136 .name = "TITAN registers",
137 .start = EXCITE_PHYS_TITAN,
138 .end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
139 .flags = IORESOURCE_MEM,
140 .parent = NULL,
141 .sibling = NULL,
142 .child = NULL
143 };
144
145
146
147static void adjust_resources(struct resource *res, unsigned int n)
148{
149 struct resource *p;
150 const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM
151 | IORESOURCE_IRQ | IORESOURCE_DMA;
152
153 for (p = res; p < res + n; p++) {
154 const struct resource * const parent = p->parent;
155 if (parent) {
156 p->start += parent->start;
157 p->end += parent->start;
158 p->flags = parent->flags & mask;
159 }
160 }
161}
162
163
164
165#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE)
166static struct resource xicap_rsrc[] = {
167 RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource),
168 RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource),
169 RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource),
170 RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource),
171 RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource),
172 RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource),
173 RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
174 RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource),
175 RINIT_IRQ(TITAN_IRQ, XICAP_RESOURCE_IRQ)
176};
177
178static struct platform_device xicap_pdev = {
179 .name = XICAP_NAME,
180 .id = XICAP_UNIT,
181 .num_resources = ARRAY_SIZE(xicap_rsrc),
182 .resource = xicap_rsrc
183};
184
185/*
186 * Create a platform device for the GPI port that receives the
187 * image data from the embedded camera.
188 */
189static int __init xicap_devinit(void)
190{
191 unsigned long tend;
192 u32 reg;
193 int retval;
194
195 adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc));
196
197 /* Power up the slice and configure it. */
198 reg = titan_readl(CPTC1R);
199 reg &= ~(0x11100 << slice_xicap);
200 titan_writel(reg, CPTC1R);
201
202 /* Enable slice & DLL. */
203 reg= titan_readl(CPRR);
204 reg &= ~(0x00030003 << (slice_xicap * 2));
205 titan_writel(reg, CPRR);
206
207 /* Wait for DLLs to lock */
208 tend = jiffies + DLL_TIMEOUT * HZ;
209 while (time_before(jiffies, tend)) {
210 if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))))
211 break;
212 yield();
213 }
214
215 if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) {
216 printk(KERN_ERR "%s: DLL not locked after %u seconds\n",
217 xicap_pdev.name, DLL_TIMEOUT);
218 retval = -ETIME;
219 } else {
220 /* Register platform device */
221 retval = platform_device_register(&xicap_pdev);
222 }
223
224 return retval;
225}
226
227device_initcall(xicap_devinit);
228#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */
229
230
231
232#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE)
233static struct resource wdt_rsrc[] = {
234 RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource),
235 RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource),
236 RINIT_IRQ(TITAN_IRQ, WDT_RESOURCE_IRQ)
237};
238
239static struct platform_device wdt_pdev = {
240 .name = WDT_NAME,
241 .id = -1,
242 .num_resources = ARRAY_SIZE(wdt_rsrc),
243 .resource = wdt_rsrc
244};
245
246/*
247 * Create a platform device for the GPI port that receives the
248 * image data from the embedded camera.
249 */
250static int __init wdt_devinit(void)
251{
252 adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc));
253 return platform_device_register(&wdt_pdev);
254}
255
256device_initcall(wdt_devinit);
257#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */
258
259
260
261static struct resource excite_nandflash_rsrc[] = {
262 RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS, &excite_nand_resource)
263};
264
265static struct platform_device excite_nandflash_pdev = {
266 .name = "excite_nand",
267 .id = NAND_UNIT,
268 .num_resources = ARRAY_SIZE(excite_nandflash_rsrc),
269 .resource = excite_nandflash_rsrc
270};
271
272/*
273 * Create a platform device for the access to the nand-flash
274 * port
275 */
276static int __init excite_nandflash_devinit(void)
277{
278 adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc));
279
280 /* nothing to be done here */
281
282 /* Register platform device */
283 return platform_device_register(&excite_nandflash_pdev);
284}
285
286device_initcall(excite_nandflash_devinit);
287
288
289
290static struct resource iodev_rsrc[] = {
291 RINIT_IRQ(FPGA1_IRQ, IODEV_RESOURCE_IRQ)
292};
293
294static struct platform_device io_pdev = {
295 .name = IODEV_NAME,
296 .id = -1,
297 .num_resources = ARRAY_SIZE(iodev_rsrc),
298 .resource = iodev_rsrc
299};
300
301/*
302 * Create a platform device for the external I/O ports.
303 */
304static int __init io_devinit(void)
305{
306 adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc));
307 return platform_device_register(&io_pdev);
308}
309
310device_initcall(io_devinit);
311
312
313
314
315#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE)
316static struct resource rm9k_ge_rsrc[] = {
317 RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource),
318 RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource),
319 RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource),
320 RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource),
321 RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource),
322 RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource),
323 RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource),
324 RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource),
325 RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource),
326 RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource),
327 RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource),
328 RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
329 RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource),
330 RINIT_IRQ(TITAN_IRQ, RM9K_GE_RESOURCE_IRQ_MAIN),
331 RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY)
332};
333
334static struct platform_device rm9k_ge_pdev = {
335 .name = RM9K_GE_NAME,
336 .id = RM9K_GE_UNIT,
337 .num_resources = ARRAY_SIZE(rm9k_ge_rsrc),
338 .resource = rm9k_ge_rsrc
339};
340
341
342
343/*
344 * Create a platform device for the Ethernet port.
345 */
346static int __init rm9k_ge_devinit(void)
347{
348 u32 reg;
349
350 adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc));
351
352 /* Power up the slice and configure it. */
353 reg = titan_readl(CPTC1R);
354 reg &= ~(0x11000 << slice_eth);
355 reg |= 0x100 << slice_eth;
356 titan_writel(reg, CPTC1R);
357
358 /* Take the MAC out of reset, reset the DLLs. */
359 reg = titan_readl(CPRR);
360 reg &= ~(0x00030000 << (slice_eth * 2));
361 reg |= 0x3 << (slice_eth * 2);
362 titan_writel(reg, CPRR);
363
364 return platform_device_register(&rm9k_ge_pdev);
365}
366
367device_initcall(rm9k_ge_devinit);
368#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */
369
370
371
372static int __init excite_setup_devs(void)
373{
374 int res;
375 u32 reg;
376
377 /* Enable xdma and fifo interrupts */
378 reg = titan_readl(0x0050);
379 titan_writel(reg | 0x18000000, 0x0050);
380
381 res = request_resource(&iomem_resource, &excite_titan_resource);
382 if (res)
383 return res;
384 res = request_resource(&iomem_resource, &excite_scram_resource);
385 if (res)
386 return res;
387 res = request_resource(&iomem_resource, &excite_fpga_resource);
388 if (res)
389 return res;
390 res = request_resource(&iomem_resource, &excite_nand_resource);
391 if (res)
392 return res;
393 excite_fpga_resource.flags = excite_fpga_resource.parent->flags &
394 ( IORESOURCE_IO | IORESOURCE_MEM
395 | IORESOURCE_IRQ | IORESOURCE_DMA);
396 excite_nand_resource.flags = excite_nand_resource.parent->flags &
397 ( IORESOURCE_IO | IORESOURCE_MEM
398 | IORESOURCE_IRQ | IORESOURCE_DMA);
399
400 return 0;
401}
402
403arch_initcall(excite_setup_devs);
404
diff --git a/arch/mips/basler/excite/excite_flashtest.c b/arch/mips/basler/excite/excite_flashtest.c
new file mode 100644
index 000000000000..f0024a8e3294
--- /dev/null
+++ b/arch/mips/basler/excite/excite_flashtest.c
@@ -0,0 +1,294 @@
1/*
2* Copyright (C) 2005 by Basler Vision Technologies AG
3* Author: Thies Moeller <thies.moeller@baslerweb.com>
4*
5* This program is free software; you can redistribute it and/or modify
6* it under the terms of the GNU General Public License as published by
7* the Free Software Foundation; either version 2 of the License, or
8* (at your option) any later version.
9*
10* This program is distributed in the hope that it will be useful,
11* but WITHOUT ANY WARRANTY; without even the implied warranty of
12* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13* GNU General Public License for more details.
14*
15* You should have received a copy of the GNU General Public License
16* along with this program; if not, write to the Free Software
17* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18*/
19
20#include <linux/module.h>
21#include <linux/types.h>
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <linux/string.h>
25#include <linux/ioport.h>
26#include <linux/device.h>
27#include <linux/delay.h>
28#include <linux/err.h>
29#include <linux/kernel.h>
30
31#include <excite.h>
32
33#include <asm/io.h>
34
35#include <linux/mtd/mtd.h>
36#include <linux/mtd/nand.h>
37#include <linux/mtd/nand_ecc.h>
38#include <linux/mtd/partitions.h>
39#include <asm/rm9k-ocd.h> // for ocd_write
40#include <linux/workqueue.h> // for queue
41
42#include "excite_nandflash.h"
43#include "nandflash.h"
44
45#define PFX "excite flashtest: "
46typedef void __iomem *io_reg_t;
47
48#define io_readb(__a__) __raw_readb((__a__))
49#define io_writeb(__v__, __a__) __raw_writeb((__v__), (__a__))
50
51
52
53static inline const struct resource *excite_nandflash_get_resource(
54 struct platform_device *d, unsigned long flags, const char *basename)
55{
56 const char fmt[] = "%s_%u";
57 char buf[80];
58
59 if (unlikely(snprintf(buf, sizeof buf, fmt, basename, d->id) >= sizeof buf))
60 return NULL;
61
62 return platform_get_resource_byname(d, flags, buf);
63}
64
65static inline io_reg_t
66excite_nandflash_map_regs(struct platform_device *d, const char *basename)
67{
68 void *result = NULL;
69 const struct resource *const r =
70 excite_nandflash_get_resource(d, IORESOURCE_MEM, basename);
71 if (r)
72 result = ioremap_nocache(r->start, r->end + 1 - r->start);
73 return result;
74}
75
76/* controller and mtd information */
77
78struct excite_nandflash_drvdata {
79 struct mtd_info board_mtd;
80 struct nand_chip board_chip;
81 io_reg_t regs;
82};
83
84
85/* command and control functions */
86static void excite_nandflash_hwcontrol(struct mtd_info *mtd, int cmd)
87{
88 struct nand_chip *this = mtd->priv;
89 io_reg_t regs = container_of(mtd,struct excite_nandflash_drvdata,board_mtd)->regs;
90
91 switch (cmd) {
92 /* Select the command latch */
93 case NAND_CTL_SETCLE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_CMD;
94 break;
95 /* Deselect the command latch */
96 case NAND_CTL_CLRCLE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_DATA;
97 break;
98 /* Select the address latch */
99 case NAND_CTL_SETALE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_ADDR;
100 break;
101 /* Deselect the address latch */
102 case NAND_CTL_CLRALE: this->IO_ADDR_W = regs + EXCITE_NANDFLASH_DATA;
103 break;
104 /* Select the chip -- not used */
105 case NAND_CTL_SETNCE:
106 break;
107 /* Deselect the chip -- not used */
108 case NAND_CTL_CLRNCE:
109 break;
110 }
111
112 this->IO_ADDR_R = this->IO_ADDR_W;
113}
114
115/* excite_nandflash_devready()
116 *
117 * returns 0 if the nand is busy, 1 if it is ready
118 */
119static int excite_nandflash_devready(struct mtd_info *mtd)
120{
121 struct excite_nandflash_drvdata *drvdata =
122 container_of(mtd, struct excite_nandflash_drvdata, board_mtd);
123
124 return io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
125}
126
127/* device management functions */
128
129/* excite_nandflash_remove
130 *
131 * called by device layer to remove the driver
132 * the binding to the mtd and all allocated
133 * resources are released
134 */
135static int excite_nandflash_remove(struct device *dev)
136{
137 struct excite_nandflash_drvdata *this = dev_get_drvdata(dev);
138
139 pr_info(PFX "remove");
140
141 dev_set_drvdata(dev, NULL);
142
143 if (this == NULL) {
144 pr_debug(PFX "call remove without private data!!");
145 return 0;
146 }
147
148
149 /* free the common resources */
150 if (this->regs != NULL) {
151 iounmap(this->regs);
152 this->regs = NULL;
153 }
154
155 kfree(this);
156
157 return 0;
158}
159
160static int elapsed;
161
162void my_workqueue_handler(void *arg)
163{
164 elapsed = 1;
165}
166
167DECLARE_WORK(sigElapsed, my_workqueue_handler, 0);
168
169
170/* excite_nandflash_probe
171 *
172 * called by device layer when it finds a device matching
173 * one our driver can handled. This code checks to see if
174 * it can allocate all necessary resources then calls the
175 * nand layer to look for devices
176*/
177static int excite_nandflash_probe(struct device *dev)
178{
179 struct platform_device *pdev = to_platform_device(dev);
180
181 struct excite_nandflash_drvdata *drvdata; /* private driver data */
182 struct nand_chip *board_chip; /* private flash chip data */
183 struct mtd_info *board_mtd; /* mtd info for this board */
184
185 int err = 0;
186 int count = 0;
187 struct timeval tv,endtv;
188 unsigned int dt;
189
190 pr_info(PFX "probe dev: (%p)\n", dev);
191
192 pr_info(PFX "adjust LB timing\n");
193 ocd_writel(0x00000330, LDP2);
194
195 drvdata = kmalloc(sizeof(*drvdata), GFP_KERNEL);
196 if (unlikely(!drvdata)) {
197 printk(KERN_ERR PFX "no memory for drvdata\n");
198 err = -ENOMEM;
199 goto mem_error;
200 }
201
202 /* Initialize structures */
203 memset(drvdata, 0, sizeof(*drvdata));
204
205 /* bind private data into driver */
206 dev_set_drvdata(dev, drvdata);
207
208 /* allocate and map the resource */
209 drvdata->regs =
210 excite_nandflash_map_regs(pdev, EXCITE_NANDFLASH_RESOURCE_REGS);
211
212 if (unlikely(!drvdata->regs)) {
213 printk(KERN_ERR PFX "cannot reserve register region\n");
214 err = -ENXIO;
215 goto io_error;
216 }
217
218 /* initialise our chip */
219 board_chip = &drvdata->board_chip;
220
221 board_chip->IO_ADDR_R = drvdata->regs + EXCITE_NANDFLASH_DATA;
222 board_chip->IO_ADDR_W = drvdata->regs + EXCITE_NANDFLASH_DATA;
223
224 board_chip->hwcontrol = excite_nandflash_hwcontrol;
225 board_chip->dev_ready = excite_nandflash_devready;
226
227 board_chip->chip_delay = 25;
228 #if 0
229 /* TODO: speedup the initial scan */
230 board_chip->options = NAND_USE_FLASH_BBT;
231 #endif
232 board_chip->eccmode = NAND_ECC_SOFT;
233
234 /* link chip to mtd */
235 board_mtd = &drvdata->board_mtd;
236 board_mtd->priv = board_chip;
237
238
239 pr_info(PFX "FlashTest\n");
240 elapsed = 0;
241/* schedule_delayed_work(&sigElapsed, 1*HZ);
242 while (!elapsed) {
243 io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
244 count++;
245 }
246 pr_info(PFX "reads in 1 sec --> %d\n",count);
247*/
248 do_gettimeofday(&tv);
249 for (count = 0 ; count < 1000000; count ++) {
250 io_readb(drvdata->regs + EXCITE_NANDFLASH_STATUS);
251 }
252 do_gettimeofday(&endtv);
253 dt = (endtv.tv_sec - tv.tv_sec) * 1000000 + endtv.tv_usec - tv.tv_usec;
254 pr_info(PFX "%8d us timeval\n",dt);
255 pr_info(PFX "EndFlashTest\n");
256
257/* return with error to unload everything
258*/
259io_error:
260 iounmap(drvdata->regs);
261
262mem_error:
263 kfree(drvdata);
264
265 if (err == 0)
266 err = -EINVAL;
267 return err;
268}
269
270static struct device_driver excite_nandflash_driver = {
271 .name = "excite_nand",
272 .bus = &platform_bus_type,
273 .probe = excite_nandflash_probe,
274 .remove = excite_nandflash_remove,
275};
276
277static int __init excite_nandflash_init(void)
278{
279 pr_info(PFX "register Driver (Rev: $Revision:$)\n");
280 return driver_register(&excite_nandflash_driver);
281}
282
283static void __exit excite_nandflash_exit(void)
284{
285 driver_unregister(&excite_nandflash_driver);
286 pr_info(PFX "Driver unregistered");
287}
288
289module_init(excite_nandflash_init);
290module_exit(excite_nandflash_exit);
291
292MODULE_AUTHOR("Thies Moeller <thies.moeller@baslerweb.com>");
293MODULE_DESCRIPTION("Basler eXcite NAND-Flash driver");
294MODULE_LICENSE("GPL");
diff --git a/arch/mips/basler/excite/excite_fpga.h b/arch/mips/basler/excite/excite_fpga.h
new file mode 100644
index 000000000000..38fcda703a0b
--- /dev/null
+++ b/arch/mips/basler/excite/excite_fpga.h
@@ -0,0 +1,80 @@
1#ifndef EXCITE_FPGA_H_INCLUDED
2#define EXCITE_FPGA_H_INCLUDED
3
4
5/**
6 * Adress alignment of the individual FPGA bytes.
7 * The address arrangement of the individual bytes of the FPGA is two
8 * byte aligned at the embedded MK2 platform.
9 */
10#ifdef EXCITE_CCI_FPGA_MK2
11typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
12#else
13typedef unsigned char excite_cci_fpga_align_t;
14#endif
15
16
17/**
18 * Size of Dual Ported RAM.
19 */
20#define EXCITE_DPR_SIZE 263
21
22
23/**
24 * Size of Reserved Status Fields in Dual Ported RAM.
25 */
26#define EXCITE_DPR_STATUS_SIZE 7
27
28
29
30/**
31 * FPGA.
32 * Hardware register layout of the FPGA interface. The FPGA must accessed
33 * byte wise solely.
34 * @see EXCITE_CCI_DPR_MK2
35 */
36typedef struct excite_fpga {
37
38 /**
39 * Dual Ported RAM.
40 */
41 excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
42
43 /**
44 * Status.
45 */
46 excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
47
48#ifdef EXCITE_CCI_FPGA_MK2
49 /**
50 * RM9000 Interrupt.
51 * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
52 */
53 excite_cci_fpga_align_t rm9k_int;
54#else
55 /**
56 * MK2 Interrupt.
57 * Write access initiates interrupt at the ARM processor of the MK2.
58 */
59 excite_cci_fpga_align_t mk2_int;
60
61 excite_cci_fpga_align_t gap[0x1000-0x10f];
62
63 /**
64 * IRQ Source/Acknowledge.
65 */
66 excite_cci_fpga_align_t rm9k_irq_src;
67
68 /**
69 * IRQ Mask.
70 * Set bits enable the related interrupt.
71 */
72 excite_cci_fpga_align_t rm9k_irq_mask;
73#endif
74
75
76} excite_fpga;
77
78
79
80#endif /* ndef EXCITE_FPGA_H_INCLUDED */
diff --git a/arch/mips/basler/excite/excite_iodev.c b/arch/mips/basler/excite/excite_iodev.c
new file mode 100644
index 000000000000..91121e523043
--- /dev/null
+++ b/arch/mips/basler/excite/excite_iodev.c
@@ -0,0 +1,183 @@
1/*
2 * Copyright (C) 2005 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/config.h>
21#include <linux/compiler.h>
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/sched.h>
25#include <linux/wait.h>
26#include <linux/poll.h>
27#include <linux/interrupt.h>
28#include <linux/platform_device.h>
29#include <linux/miscdevice.h>
30
31#include "excite_iodev.h"
32
33
34
35static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int);
36static int __init iodev_probe(struct device *);
37static int __exit iodev_remove(struct device *);
38static int iodev_open(struct inode *, struct file *);
39static int iodev_release(struct inode *, struct file *);
40static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *);
41static unsigned int iodev_poll(struct file *, struct poll_table_struct *);
42static irqreturn_t iodev_irqhdl(int, void *, struct pt_regs *);
43
44
45
46static const char iodev_name[] = "iodev";
47static unsigned int iodev_irq;
48static DECLARE_WAIT_QUEUE_HEAD(wq);
49
50
51
52static struct file_operations fops =
53{
54 .owner = THIS_MODULE,
55 .open = iodev_open,
56 .release = iodev_release,
57 .read = iodev_read,
58 .poll = iodev_poll
59};
60
61static struct miscdevice miscdev =
62{
63 .minor = MISC_DYNAMIC_MINOR,
64 .name = iodev_name,
65 .fops = &fops
66};
67
68static struct device_driver iodev_driver =
69{
70 .name = (char *) iodev_name,
71 .bus = &platform_bus_type,
72 .owner = THIS_MODULE,
73 .probe = iodev_probe,
74 .remove = __exit_p(iodev_remove)
75};
76
77
78
79static const struct resource *
80iodev_get_resource(struct platform_device *pdv, const char *name,
81 unsigned int type)
82{
83 char buf[80];
84 if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf)
85 return NULL;
86 return platform_get_resource_byname(pdv, type, buf);
87}
88
89
90
91/* No hotplugging on the platform bus - use __init */
92static int __init iodev_probe(struct device *dev)
93{
94 struct platform_device * const pdv = to_platform_device(dev);
95 const struct resource * const ri =
96 iodev_get_resource(pdv, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ);
97
98 if (unlikely(!ri))
99 return -ENXIO;
100
101 iodev_irq = ri->start;
102 return misc_register(&miscdev);
103}
104
105
106
107static int __exit iodev_remove(struct device *dev)
108{
109 return misc_deregister(&miscdev);
110}
111
112
113
114static int iodev_open(struct inode *i, struct file *f)
115{
116 return request_irq(iodev_irq, iodev_irqhdl, SA_INTERRUPT,
117 iodev_name, &miscdev);
118}
119
120
121
122static int iodev_release(struct inode *i, struct file *f)
123{
124 free_irq(iodev_irq, &miscdev);
125 return 0;
126}
127
128
129
130
131static ssize_t
132iodev_read(struct file *f, char __user *d, size_t s, loff_t *o)
133{
134 ssize_t ret;
135 DEFINE_WAIT(w);
136
137 prepare_to_wait(&wq, &w, TASK_INTERRUPTIBLE);
138 if (!signal_pending(current))
139 schedule();
140 ret = signal_pending(current) ? -ERESTARTSYS : 0;
141 finish_wait(&wq, &w);
142 return ret;
143}
144
145
146static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p)
147{
148 poll_wait(f, &wq, p);
149 return POLLOUT | POLLWRNORM;
150}
151
152
153
154
155static irqreturn_t iodev_irqhdl(int irq, void *ctxt, struct pt_regs *regs)
156{
157 wake_up(&wq);
158 return IRQ_HANDLED;
159}
160
161
162
163static int __init iodev_init_module(void)
164{
165 return driver_register(&iodev_driver);
166}
167
168
169
170static void __exit iodev_cleanup_module(void)
171{
172 driver_unregister(&iodev_driver);
173}
174
175module_init(iodev_init_module);
176module_exit(iodev_cleanup_module);
177
178
179
180MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
181MODULE_DESCRIPTION("Basler eXcite i/o interrupt handler");
182MODULE_VERSION("0.0");
183MODULE_LICENSE("GPL");
diff --git a/arch/mips/basler/excite/excite_iodev.h b/arch/mips/basler/excite/excite_iodev.h
new file mode 100644
index 000000000000..cbfbb5d2ee62
--- /dev/null
+++ b/arch/mips/basler/excite/excite_iodev.h
@@ -0,0 +1,10 @@
1#ifndef __EXCITE_IODEV_H__
2#define __EXCITE_IODEV_H__
3
4/* Device name */
5#define IODEV_NAME "iodev"
6
7/* Resource names */
8#define IODEV_RESOURCE_IRQ "excite_iodev_irq"
9
10#endif /* __EXCITE_IODEV_H__ */
diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c
new file mode 100644
index 000000000000..511ad8730f54
--- /dev/null
+++ b/arch/mips/basler/excite/excite_irq.c
@@ -0,0 +1,129 @@
1/*
2 * Copyright (C) by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslereb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/kernel_stat.h>
23#include <linux/module.h>
24#include <linux/signal.h>
25#include <linux/sched.h>
26#include <linux/types.h>
27#include <linux/interrupt.h>
28#include <linux/ioport.h>
29#include <linux/timex.h>
30#include <linux/slab.h>
31#include <linux/random.h>
32#include <asm/bitops.h>
33#include <asm/bootinfo.h>
34#include <asm/io.h>
35#include <asm/irq.h>
36#include <asm/irq_cpu.h>
37#include <asm/mipsregs.h>
38#include <asm/system.h>
39#include <asm/rm9k-ocd.h>
40
41#include <excite.h>
42
43extern asmlinkage void excite_handle_int(void);
44
45/*
46 * Initialize the interrupt handler
47 */
48void __init arch_init_irq(void)
49{
50 mips_cpu_irq_init(0);
51 rm7k_cpu_irq_init(8);
52 rm9k_cpu_irq_init(12);
53
54#ifdef CONFIG_KGDB
55 excite_kgdb_init();
56#endif
57}
58
59asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
60{
61 const u32
62 interrupts = read_c0_cause() >> 8,
63 mask = ((read_c0_status() >> 8) & 0x000000ff) |
64 (read_c0_intcontrol() & 0x0000ff00),
65 pending = interrupts & mask;
66 u32 msgintflags, msgintmask, msgint;
67
68 /* process timer interrupt */
69 if (pending & (1 << TIMER_IRQ)) {
70 do_IRQ(TIMER_IRQ, regs);
71 return;
72 }
73
74 /* Process PCI interrupts */
75#if USB_IRQ < 10
76 msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10));
77 msgintmask = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10));
78 msgint = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20));
79 if ((pending & (1 << USB_IRQ)) && msgint) {
80#else
81 if (pending & (1 << USB_IRQ)) {
82#endif
83 do_IRQ(USB_IRQ, regs);
84 return;
85 }
86
87 /* Process TITAN interrupts */
88 msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10));
89 msgintmask = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10));
90 msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
91 if ((pending & (1 << TITAN_IRQ)) && msgint) {
92 ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
93#if defined(CONFIG_KGDB)
94 excite_kgdb_inthdl(regs);
95#endif
96 do_IRQ(TITAN_IRQ, regs);
97 return;
98 }
99
100 /* Process FPGA line #0 interrupts */
101 msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10));
102 msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
103 msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
104 if ((pending & (1 << FPGA0_IRQ)) && msgint) {
105 do_IRQ(FPGA0_IRQ, regs);
106 return;
107 }
108
109 /* Process FPGA line #1 interrupts */
110 msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10));
111 msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
112 msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
113 if ((pending & (1 << FPGA1_IRQ)) && msgint) {
114 do_IRQ(FPGA1_IRQ, regs);
115 return;
116 }
117
118 /* Process PHY interrupts */
119 msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10));
120 msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
121 msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
122 if ((pending & (1 << PHY_IRQ)) && msgint) {
123 do_IRQ(PHY_IRQ, regs);
124 return;
125 }
126
127 /* Process spurious interrupts */
128 spurious_interrupt(regs);
129}
diff --git a/arch/mips/basler/excite/excite_procfs.c b/arch/mips/basler/excite/excite_procfs.c
new file mode 100644
index 000000000000..c62be0341fb8
--- /dev/null
+++ b/arch/mips/basler/excite/excite_procfs.c
@@ -0,0 +1,81 @@
1/*
2 * Copyright (C) 2004, 2005 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * Procfs support for Basler eXcite
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/config.h>
23#include <linux/proc_fs.h>
24#include <linux/stat.h>
25#include <asm/page.h>
26#include <asm/io.h>
27#include <asm/system.h>
28#include <asm/rm9k-ocd.h>
29
30#include <excite.h>
31
32static int excite_get_unit_id(char *buf, char **addr, off_t offs, int size)
33{
34 const int len = snprintf(buf, PAGE_SIZE, "%06x", unit_id);
35 const int w = len - offs;
36 *addr = buf + offs;
37 return w < size ? w : size;
38}
39
40static int
41excite_bootrom_read(char *page, char **start, off_t off, int count,
42 int *eof, void *data)
43{
44 void __iomem * src;
45
46 if (off >= EXCITE_SIZE_BOOTROM) {
47 *eof = 1;
48 return 0;
49 }
50
51 if ((off + count) > EXCITE_SIZE_BOOTROM)
52 count = EXCITE_SIZE_BOOTROM - off;
53
54 src = ioremap(EXCITE_PHYS_BOOTROM + off, count);
55 if (src) {
56 memcpy_fromio(page, src, count);
57 iounmap(src);
58 *start = page;
59 } else {
60 count = -ENOMEM;
61 }
62
63 return count;
64}
65
66void excite_procfs_init(void)
67{
68 /* Create & populate /proc/excite */
69 struct proc_dir_entry * const pdir = proc_mkdir("excite", &proc_root);
70 if (pdir) {
71 struct proc_dir_entry * e;
72
73 e = create_proc_info_entry("unit_id", S_IRUGO, pdir,
74 excite_get_unit_id);
75 if (e) e->size = 6;
76
77 e = create_proc_read_entry("bootrom", S_IRUGO, pdir,
78 excite_bootrom_read, NULL);
79 if (e) e->size = EXCITE_SIZE_BOOTROM;
80 }
81}
diff --git a/arch/mips/basler/excite/excite_prom.c b/arch/mips/basler/excite/excite_prom.c
new file mode 100644
index 000000000000..84724b270753
--- /dev/null
+++ b/arch/mips/basler/excite/excite_prom.c
@@ -0,0 +1,148 @@
1/*
2 * Copyright (C) 2004, 2005 by Thomas Koeller (thomas.koeller@baslerweb.com)
3 * Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
4 * Manish Lachwani.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/config.h>
22#include <linux/init.h>
23#include <linux/sched.h>
24#include <linux/mm.h>
25#include <linux/delay.h>
26#include <linux/smp.h>
27#include <linux/module.h>
28#include <asm/io.h>
29#include <asm/pgtable.h>
30#include <asm/processor.h>
31#include <asm/reboot.h>
32#include <asm/system.h>
33#include <asm/bootinfo.h>
34#include <asm/string.h>
35
36#include <excite.h>
37
38/* This struct is used by Redboot to pass arguments to the kernel */
39typedef struct
40{
41 char *name;
42 char *val;
43} t_env_var;
44
45struct parmblock {
46 t_env_var memsize;
47 t_env_var modetty0;
48 t_env_var ethaddr;
49 t_env_var env_end;
50 char *argv[2];
51 char text[0];
52};
53
54static unsigned int prom_argc;
55static const char ** prom_argv;
56static const t_env_var * prom_env;
57
58static void prom_halt(void) __attribute__((noreturn));
59static void prom_exit(void) __attribute__((noreturn));
60
61
62
63const char *get_system_type(void)
64{
65 return "Basler eXcite";
66}
67
68/*
69 * Halt the system
70 */
71static void prom_halt(void)
72{
73 printk(KERN_NOTICE "\n** System halted.\n");
74 while (1)
75 asm volatile (
76 "\t.set\tmips3\n"
77 "\twait\n"
78 "\t.set\tmips0\n"
79 );
80}
81
82/*
83 * Reset the CPU and re-enter Redboot
84 */
85static void prom_exit(void)
86{
87 unsigned int i;
88 volatile unsigned char * const flg =
89 (volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_DPR);
90
91 /* Clear the watchdog reset flag, set the reboot flag */
92 *flg &= ~0x01;
93 *flg |= 0x80;
94
95 for (i = 0; i < 10; i++) {
96 *(volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_SYSCTL) = 0x02;
97 iob();
98 mdelay(1000);
99 }
100
101 printk(KERN_NOTICE "Reset failed\n");
102 prom_halt();
103}
104
105static const char __init *prom_getenv(char *name)
106{
107 const t_env_var * p;
108 for (p = prom_env; p->name != NULL; p++)
109 if(strcmp(name, p->name) == 0)
110 break;
111 return p->val;
112}
113
114/*
115 * Init routine which accepts the variables from Redboot
116 */
117void __init prom_init(void)
118{
119 const struct parmblock * const pb = (struct parmblock *) fw_arg2;
120
121 prom_argc = fw_arg0;
122 prom_argv = (const char **) fw_arg1;
123 prom_env = &pb->memsize;
124
125 /* Callbacks for halt, restart */
126 _machine_restart = (void (*)(char *)) prom_exit;
127 _machine_halt = prom_halt;
128
129#ifdef CONFIG_32BIT
130 /* copy command line */
131 strcpy(arcs_cmdline, prom_argv[1]);
132 memsize = simple_strtol(prom_getenv("memsize"), NULL, 16);
133 strcpy(modetty, prom_getenv("modetty0"));
134#endif /* CONFIG_32BIT */
135
136#ifdef CONFIG_64BIT
137# error 64 bit support not implemented
138#endif /* CONFIG_64BIT */
139
140 mips_machgroup = MACH_GROUP_TITAN;
141 mips_machtype = MACH_TITAN_EXCITE;
142}
143
144/* This is called from free_initmem(), so we need to provide it */
145void __init prom_free_prom_memory(void)
146{
147 /* Nothing to do */
148}
diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c
new file mode 100644
index 000000000000..005b025605e6
--- /dev/null
+++ b/arch/mips/basler/excite/excite_setup.c
@@ -0,0 +1,307 @@
1/*
2 * Copyright (C) 2004, 2005 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 * Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
5 * Manish Lachwani.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/config.h>
23#include <linux/types.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/string.h>
27#include <linux/tty.h>
28#include <linux/serial_core.h>
29#include <linux/serial.h>
30#include <linux/ioport.h>
31#include <linux/spinlock.h>
32#include <asm/bootinfo.h>
33#include <asm/mipsregs.h>
34#include <asm/pgtable-32.h>
35#include <asm/io.h>
36#include <asm/time.h>
37#include <asm/rm9k-ocd.h>
38
39#include <excite.h>
40
41#define TITAN_UART_CLK 25000000
42
43#if 1
44/* normal serial port assignment */
45#define REGBASE_SER0 0x0208
46#define REGBASE_SER1 0x0238
47#define MASK_SER0 0x1
48#define MASK_SER1 0x2
49#else
50/* serial ports swapped */
51#define REGBASE_SER0 0x0238
52#define REGBASE_SER1 0x0208
53#define MASK_SER0 0x2
54#define MASK_SER1 0x1
55#endif
56
57unsigned long memsize;
58char modetty[30];
59unsigned int titan_irq = TITAN_IRQ;
60static void __iomem * ctl_regs;
61u32 unit_id;
62
63volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD);
64volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN);
65
66/* Protect access to shared GPI registers */
67spinlock_t titan_lock = SPIN_LOCK_UNLOCKED;
68int titan_irqflags;
69
70
71static void excite_timer_init(void)
72{
73 const u32 modebit5 = ocd_readl(0x00e4);
74 unsigned int
75 mult = ((modebit5 >> 11) & 0x1f) + 2,
76 div = ((modebit5 >> 16) & 0x1f) + 2;
77
78 if (div == 33) div = 1;
79 mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2;
80}
81
82static void excite_timer_setup(struct irqaction *irq)
83{
84 /* The eXcite platform uses the alternate timer interrupt */
85 set_c0_intcontrol(0x80);
86 setup_irq(TIMER_IRQ, irq);
87}
88
89static int __init excite_init_console(void)
90{
91#if defined(CONFIG_SERIAL_8250)
92 static __initdata char serr[] =
93 KERN_ERR "Serial port #%u setup failed\n";
94 struct uart_port up;
95
96 /* Take the DUART out of reset */
97 titan_writel(0x00ff1cff, CPRR);
98
99#if defined(CONFIG_KGDB) || (CONFIG_SERIAL_8250_NR_UARTS > 1)
100 /* Enable both ports */
101 titan_writel(MASK_SER0 | MASK_SER1, UACFG);
102#else
103 /* Enable port #0 only */
104 titan_writel(MASK_SER0, UACFG);
105#endif /* defined(CONFIG_KGDB) */
106
107 /*
108 * Set up serial port #0. Do not use autodetection; the result is
109 * not what we want.
110 */
111 memset(&up, 0, sizeof(up));
112 up.membase = (char *) titan_addr(REGBASE_SER0);
113 up.irq = TITAN_IRQ;
114 up.uartclk = TITAN_UART_CLK;
115 up.regshift = 0;
116 up.iotype = UPIO_MEM32;
117 up.type = PORT_RM9000;
118 up.flags = UPF_SHARE_IRQ;
119 up.line = 0;
120 if (early_serial_setup(&up))
121 printk(serr, up.line);
122
123#if CONFIG_SERIAL_8250_NR_UARTS > 1
124 /* And now for port #1. */
125 up.membase = (char *) titan_addr(REGBASE_SER1);
126 up.line = 1;
127 if (early_serial_setup(&up))
128 printk(serr, up.line);
129#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */
130#else
131 /* Leave the DUART in reset */
132 titan_writel(0x00ff3cff, CPRR);
133#endif /* defined(CONFIG_SERIAL_8250) */
134
135 return 0;
136}
137
138static int __init excite_platform_init(void)
139{
140 unsigned int i;
141 unsigned char buf[3];
142 u8 reg;
143 void __iomem * dpr;
144
145 /* BIU buffer allocations */
146 ocd_writel(8, CPURSLMT); /* CPU */
147 titan_writel(4, CPGRWL); /* GPI / Ethernet */
148
149 /* Map control registers located in FPGA */
150 ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16);
151 if (!ctl_regs)
152 panic("eXcite: failed to map platform control registers\n");
153 memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf));
154 unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16);
155
156 /* Clear the reboot flag */
157 dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1);
158 reg = __raw_readb(dpr);
159 __raw_writeb(reg & 0x7f, dpr);
160 iounmap(dpr);
161
162 /* Interrupt controller setup */
163 for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) {
164 ocd_writel(0x00000000, i + 0x04);
165 ocd_writel(0xffffffff, i + 0x0c);
166 }
167 ocd_writel(0x2, NMICONFIG);
168
169 ocd_writel(0x1 << (TITAN_MSGINT % 0x20),
170 INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20)));
171 ocd_writel((0x1 << (FPGA0_MSGINT % 0x20))
172 | ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))),
173 INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20)));
174 ocd_writel((0x1 << (FPGA1_MSGINT % 0x20))
175 | ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))),
176 INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20)));
177 ocd_writel((0x1 << (PHY_MSGINT % 0x20))
178 | ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))),
179 INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20)));
180#if USB_IRQ < 10
181 ocd_writel((0x1 << (USB_MSGINT % 0x20))
182 | ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))),
183 INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20)));
184#endif
185 /* Enable the packet FIFO, XDMA and XDMA arbiter */
186 titan_writel(0x00ff18ff, CPRR);
187
188 /*
189 * Set up the PADMUX. Power down all ethernet slices,
190 * they will be powered up and configured at device startup.
191 */
192 titan_writel(0x00878206, CPTC1R);
193 titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */
194
195 /* Reset and enable the FIFO block */
196 titan_writel(0x00000001, SDRXFCIE);
197 titan_writel(0x00000001, SDTXFCIE);
198 titan_writel(0x00000100, SDRXFCIE);
199 titan_writel(0x00000000, SDTXFCIE);
200
201 /*
202 * Initialize the common interrupt shared by all components of
203 * the GPI/Ethernet subsystem.
204 */
205 titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0);
206 titan_writel(TITAN_MSGINT, CPCFG1);
207
208 /*
209 * XDMA configuration.
210 * In order for the XDMA to be sharable among multiple drivers,
211 * the setup must be done here in the platform. The reason is that
212 * this setup can only be done while the XDMA is in reset. If this
213 * were done in a driver, it would interrupt all other drivers
214 * using the XDMA.
215 */
216 titan_writel(0x80021dff, GXCFG); /* XDMA reset */
217 titan_writel(0x00000000, CPXCISRA);
218 titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */
219#if defined (CONFIG_HIGHMEM)
220# error change for HIGHMEM support!
221#else
222 titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */
223#endif
224 titan_writel(0, GXDMA_DESCADR);
225
226 for (i = 0x5040; i <= 0x5300; i += 0x0040)
227 titan_writel(0x80080000, i); /* reset channel */
228
229 titan_writel((0x1 << 29) /* no sparse tx descr. */
230 | (0x1 << 28) /* no sparse rx descr. */
231 | (0x1 << 23) | (0x1 << 24) /* descriptor coherency */
232 | (0x1 << 21) | (0x1 << 22) /* data coherency */
233 | (0x1 << 17)
234 | 0x1dff,
235 GXCFG);
236
237#if defined(CONFIG_SMP)
238# error No SMP support
239#else
240 /* All interrupts go to core #0 only. */
241 titan_writel(0x1f007fff, CPDST0A);
242 titan_writel(0x00000000, CPDST0B);
243 titan_writel(0x0000ff3f, CPDST1A);
244 titan_writel(0x00000000, CPDST1B);
245 titan_writel(0x00ffffff, CPXDSTA);
246 titan_writel(0x00000000, CPXDSTB);
247#endif
248
249 /* Enable DUART interrupts, disable everything else. */
250 titan_writel(0x04000000, CPGIG0ER);
251 titan_writel(0x000000c0, CPGIG1ER);
252
253 excite_procfs_init();
254 return 0;
255}
256
257void __init plat_setup(void)
258{
259 volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000;
260
261 /* Announce RAM to system */
262 add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
263
264 /* Set up timer initialization hooks */
265 board_time_init = excite_timer_init;
266 board_timer_setup = excite_timer_setup;
267
268 /* Set up the peripheral address map */
269 *(boot_ocd_base + (LKB9 / sizeof (u32))) = 0;
270 *(boot_ocd_base + (LKB10 / sizeof (u32))) = 0;
271 *(boot_ocd_base + (LKB11 / sizeof (u32))) = 0;
272 *(boot_ocd_base + (LKB12 / sizeof (u32))) = 0;
273 wmb();
274 *(boot_ocd_base + (LKB0 / sizeof (u32))) = EXCITE_PHYS_OCD >> 4;
275 wmb();
276
277 ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
278 ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5);
279 ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13);
280 ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13);
281
282 /* Local bus slot #0 */
283 ocd_writel(0x00040510, LDP0);
284 ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9);
285 ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9);
286
287 /* Local bus slot #2 */
288 ocd_writel(0x00000330, LDP2);
289 ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11);
290 ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11);
291
292 /* Local bus slot #3 */
293 ocd_writel(0x00123413, LDP3);
294 ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12);
295 ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12);
296}
297
298
299
300console_initcall(excite_init_console);
301arch_initcall(excite_platform_init);
302
303EXPORT_SYMBOL(titan_lock);
304EXPORT_SYMBOL(titan_irqflags);
305EXPORT_SYMBOL(titan_irq);
306EXPORT_SYMBOL(ocd_base);
307EXPORT_SYMBOL(titan_base);
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
new file mode 100644
index 000000000000..3240962ef585
--- /dev/null
+++ b/arch/mips/configs/excite_defconfig
@@ -0,0 +1,1211 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.16-rc4
4# Thu Feb 23 13:15:27 2006
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MIPS_MTX1 is not set
12# CONFIG_MIPS_BOSPORUS is not set
13# CONFIG_MIPS_PB1000 is not set
14# CONFIG_MIPS_PB1100 is not set
15# CONFIG_MIPS_PB1500 is not set
16# CONFIG_MIPS_PB1550 is not set
17# CONFIG_MIPS_PB1200 is not set
18# CONFIG_MIPS_DB1000 is not set
19# CONFIG_MIPS_DB1100 is not set
20# CONFIG_MIPS_DB1500 is not set
21# CONFIG_MIPS_DB1550 is not set
22# CONFIG_MIPS_DB1200 is not set
23# CONFIG_MIPS_MIRAGE is not set
24# CONFIG_MIPS_COBALT is not set
25# CONFIG_MACH_DECSTATION is not set
26# CONFIG_MIPS_EV64120 is not set
27# CONFIG_MIPS_EV96100 is not set
28# CONFIG_MIPS_IVR is not set
29# CONFIG_MIPS_ITE8172 is not set
30# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set
33# CONFIG_MIPS_MALTA is not set
34# CONFIG_MIPS_SEAD is not set
35# CONFIG_MIPS_SIM is not set
36# CONFIG_MOMENCO_JAGUAR_ATX is not set
37# CONFIG_MOMENCO_OCELOT is not set
38# CONFIG_MOMENCO_OCELOT_3 is not set
39# CONFIG_MOMENCO_OCELOT_C is not set
40# CONFIG_MOMENCO_OCELOT_G is not set
41# CONFIG_MIPS_XXS1500 is not set
42# CONFIG_PNX8550_V2PCI is not set
43# CONFIG_PNX8550_JBS is not set
44CONFIG_BASLER_EXCITE=y
45# CONFIG_BASLER_EXCITE_PROTOTYPE is not set
46# CONFIG_DDB5074 is not set
47# CONFIG_DDB5476 is not set
48# CONFIG_DDB5477 is not set
49# CONFIG_MACH_VR41XX is not set
50# CONFIG_PMC_YOSEMITE is not set
51# CONFIG_QEMU is not set
52# CONFIG_SGI_IP22 is not set
53# CONFIG_SGI_IP27 is not set
54# CONFIG_SGI_IP32 is not set
55# CONFIG_SIBYTE_BIGSUR is not set
56# CONFIG_SIBYTE_SWARM is not set
57# CONFIG_SIBYTE_SENTOSA is not set
58# CONFIG_SIBYTE_RHONE is not set
59# CONFIG_SIBYTE_CARMEL is not set
60# CONFIG_SIBYTE_PTSWARM is not set
61# CONFIG_SIBYTE_LITTLESUR is not set
62# CONFIG_SIBYTE_CRHINE is not set
63# CONFIG_SIBYTE_CRHONE is not set
64# CONFIG_SNI_RM200_PCI is not set
65# CONFIG_TOSHIBA_JMR3927 is not set
66# CONFIG_TOSHIBA_RBTX4927 is not set
67# CONFIG_TOSHIBA_RBTX4938 is not set
68CONFIG_RWSEM_GENERIC_SPINLOCK=y
69CONFIG_GENERIC_CALIBRATE_DELAY=y
70CONFIG_DMA_COHERENT=y
71CONFIG_SERIAL_RM9000=y
72CONFIG_CPU_BIG_ENDIAN=y
73# CONFIG_CPU_LITTLE_ENDIAN is not set
74CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
75CONFIG_IRQ_CPU=y
76CONFIG_IRQ_CPU_RM7K=y
77CONFIG_IRQ_CPU_RM9K=y
78CONFIG_MIPS_L1_CACHE_SHIFT=5
79
80#
81# CPU selection
82#
83# CONFIG_CPU_MIPS32_R1 is not set
84# CONFIG_CPU_MIPS32_R2 is not set
85# CONFIG_CPU_MIPS64_R1 is not set
86# CONFIG_CPU_MIPS64_R2 is not set
87# CONFIG_CPU_R3000 is not set
88# CONFIG_CPU_TX39XX is not set
89# CONFIG_CPU_VR41XX is not set
90# CONFIG_CPU_R4300 is not set
91# CONFIG_CPU_R4X00 is not set
92# CONFIG_CPU_TX49XX is not set
93# CONFIG_CPU_R5000 is not set
94# CONFIG_CPU_R5432 is not set
95# CONFIG_CPU_R6000 is not set
96# CONFIG_CPU_NEVADA is not set
97# CONFIG_CPU_R8000 is not set
98# CONFIG_CPU_R10000 is not set
99# CONFIG_CPU_RM7000 is not set
100CONFIG_CPU_RM9000=y
101# CONFIG_CPU_SB1 is not set
102CONFIG_SYS_HAS_CPU_RM9000=y
103CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
104CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
105CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
106CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
107
108#
109# Kernel type
110#
111CONFIG_32BIT=y
112# CONFIG_64BIT is not set
113CONFIG_PAGE_SIZE_4KB=y
114# CONFIG_PAGE_SIZE_8KB is not set
115# CONFIG_PAGE_SIZE_16KB is not set
116# CONFIG_PAGE_SIZE_64KB is not set
117CONFIG_CPU_HAS_PREFETCH=y
118# CONFIG_MIPS_MT is not set
119# CONFIG_64BIT_PHYS_ADDR is not set
120# CONFIG_CPU_ADVANCED is not set
121CONFIG_CPU_HAS_LLSC=y
122CONFIG_CPU_HAS_SYNC=y
123CONFIG_GENERIC_HARDIRQS=y
124CONFIG_GENERIC_IRQ_PROBE=y
125CONFIG_CPU_SUPPORTS_HIGHMEM=y
126CONFIG_ARCH_FLATMEM_ENABLE=y
127CONFIG_SELECT_MEMORY_MODEL=y
128CONFIG_FLATMEM_MANUAL=y
129# CONFIG_DISCONTIGMEM_MANUAL is not set
130# CONFIG_SPARSEMEM_MANUAL is not set
131CONFIG_FLATMEM=y
132CONFIG_FLAT_NODE_MEM_MAP=y
133# CONFIG_SPARSEMEM_STATIC is not set
134CONFIG_SPLIT_PTLOCK_CPUS=4
135# CONFIG_SMP is not set
136# CONFIG_PREEMPT_NONE is not set
137# CONFIG_PREEMPT_VOLUNTARY is not set
138CONFIG_PREEMPT=y
139CONFIG_PREEMPT_BKL=y
140
141#
142# Code maturity level options
143#
144CONFIG_EXPERIMENTAL=y
145CONFIG_BROKEN_ON_SMP=y
146CONFIG_LOCK_KERNEL=y
147CONFIG_INIT_ENV_ARG_LIMIT=32
148
149#
150# General setup
151#
152CONFIG_LOCALVERSION=""
153# CONFIG_LOCALVERSION_AUTO is not set
154CONFIG_SWAP=y
155CONFIG_SYSVIPC=y
156CONFIG_POSIX_MQUEUE=y
157# CONFIG_BSD_PROCESS_ACCT is not set
158CONFIG_SYSCTL=y
159# CONFIG_AUDIT is not set
160# CONFIG_IKCONFIG is not set
161CONFIG_INITRAMFS_SOURCE=""
162CONFIG_CC_OPTIMIZE_FOR_SIZE=y
163CONFIG_EMBEDDED=y
164CONFIG_KALLSYMS=y
165# CONFIG_KALLSYMS_EXTRA_PASS is not set
166CONFIG_HOTPLUG=y
167CONFIG_PRINTK=y
168CONFIG_BUG=y
169CONFIG_ELF_CORE=y
170CONFIG_BASE_FULL=y
171CONFIG_FUTEX=y
172CONFIG_EPOLL=y
173CONFIG_SHMEM=y
174CONFIG_CC_ALIGN_FUNCTIONS=0
175CONFIG_CC_ALIGN_LABELS=0
176CONFIG_CC_ALIGN_LOOPS=0
177CONFIG_CC_ALIGN_JUMPS=0
178CONFIG_SLAB=y
179# CONFIG_TINY_SHMEM is not set
180CONFIG_BASE_SMALL=0
181# CONFIG_SLOB is not set
182
183#
184# Loadable module support
185#
186CONFIG_MODULES=y
187CONFIG_MODULE_UNLOAD=y
188# CONFIG_MODULE_FORCE_UNLOAD is not set
189CONFIG_OBSOLETE_MODPARM=y
190# CONFIG_MODVERSIONS is not set
191# CONFIG_MODULE_SRCVERSION_ALL is not set
192CONFIG_KMOD=y
193
194#
195# Block layer
196#
197# CONFIG_LBD is not set
198
199#
200# IO Schedulers
201#
202CONFIG_IOSCHED_NOOP=y
203CONFIG_IOSCHED_AS=y
204CONFIG_IOSCHED_DEADLINE=y
205CONFIG_IOSCHED_CFQ=y
206CONFIG_DEFAULT_AS=y
207# CONFIG_DEFAULT_DEADLINE is not set
208# CONFIG_DEFAULT_CFQ is not set
209# CONFIG_DEFAULT_NOOP is not set
210CONFIG_DEFAULT_IOSCHED="anticipatory"
211
212#
213# Bus options (PCI, PCMCIA, EISA, ISA, TC)
214#
215CONFIG_HW_HAS_PCI=y
216CONFIG_PCI=y
217# CONFIG_PCI_LEGACY_PROC is not set
218CONFIG_MMU=y
219
220#
221# PCCARD (PCMCIA/CardBus) support
222#
223# CONFIG_PCCARD is not set
224
225#
226# PCI Hotplug Support
227#
228# CONFIG_HOTPLUG_PCI is not set
229
230#
231# Executable file formats
232#
233CONFIG_BINFMT_ELF=y
234# CONFIG_BINFMT_MISC is not set
235CONFIG_TRAD_SIGNALS=y
236
237#
238# Networking
239#
240CONFIG_NET=y
241
242#
243# Networking options
244#
245# CONFIG_NETDEBUG is not set
246CONFIG_PACKET=y
247CONFIG_PACKET_MMAP=y
248CONFIG_UNIX=y
249# CONFIG_NET_KEY is not set
250CONFIG_INET=y
251# CONFIG_IP_MULTICAST is not set
252# CONFIG_IP_ADVANCED_ROUTER is not set
253CONFIG_IP_FIB_HASH=y
254CONFIG_IP_PNP=y
255CONFIG_IP_PNP_DHCP=y
256# CONFIG_IP_PNP_BOOTP is not set
257# CONFIG_IP_PNP_RARP is not set
258# CONFIG_NET_IPIP is not set
259# CONFIG_NET_IPGRE is not set
260# CONFIG_ARPD is not set
261# CONFIG_SYN_COOKIES is not set
262# CONFIG_INET_AH is not set
263# CONFIG_INET_ESP is not set
264# CONFIG_INET_IPCOMP is not set
265# CONFIG_INET_TUNNEL is not set
266CONFIG_INET_DIAG=y
267CONFIG_INET_TCP_DIAG=y
268# CONFIG_TCP_CONG_ADVANCED is not set
269CONFIG_TCP_CONG_BIC=y
270# CONFIG_IPV6 is not set
271# CONFIG_NETFILTER is not set
272
273#
274# DCCP Configuration (EXPERIMENTAL)
275#
276# CONFIG_IP_DCCP is not set
277
278#
279# SCTP Configuration (EXPERIMENTAL)
280#
281# CONFIG_IP_SCTP is not set
282
283#
284# TIPC Configuration (EXPERIMENTAL)
285#
286# CONFIG_TIPC is not set
287# CONFIG_ATM is not set
288# CONFIG_BRIDGE is not set
289# CONFIG_VLAN_8021Q is not set
290# CONFIG_DECNET is not set
291# CONFIG_LLC2 is not set
292# CONFIG_IPX is not set
293# CONFIG_ATALK is not set
294# CONFIG_X25 is not set
295# CONFIG_LAPB is not set
296# CONFIG_NET_DIVERT is not set
297# CONFIG_ECONET is not set
298# CONFIG_WAN_ROUTER is not set
299
300#
301# QoS and/or fair queueing
302#
303# CONFIG_NET_SCHED is not set
304
305#
306# Network testing
307#
308# CONFIG_NET_PKTGEN is not set
309# CONFIG_HAMRADIO is not set
310# CONFIG_IRDA is not set
311# CONFIG_BT is not set
312# CONFIG_IEEE80211 is not set
313
314#
315# Device Drivers
316#
317
318#
319# Generic Driver Options
320#
321CONFIG_STANDALONE=y
322CONFIG_PREVENT_FIRMWARE_BUILD=y
323# CONFIG_FW_LOADER is not set
324
325#
326# Connector - unified userspace <-> kernelspace linker
327#
328# CONFIG_CONNECTOR is not set
329
330#
331# Memory Technology Devices (MTD)
332#
333CONFIG_MTD=y
334# CONFIG_MTD_DEBUG is not set
335# CONFIG_MTD_CONCAT is not set
336CONFIG_MTD_PARTITIONS=y
337# CONFIG_MTD_REDBOOT_PARTS is not set
338# CONFIG_MTD_CMDLINE_PARTS is not set
339
340#
341# User Modules And Translation Layers
342#
343CONFIG_MTD_CHAR=y
344CONFIG_MTD_BLOCK=y
345# CONFIG_FTL is not set
346# CONFIG_NFTL is not set
347# CONFIG_INFTL is not set
348# CONFIG_RFD_FTL is not set
349
350#
351# RAM/ROM/Flash chip drivers
352#
353# CONFIG_MTD_CFI is not set
354# CONFIG_MTD_JEDECPROBE is not set
355CONFIG_MTD_MAP_BANK_WIDTH_1=y
356CONFIG_MTD_MAP_BANK_WIDTH_2=y
357CONFIG_MTD_MAP_BANK_WIDTH_4=y
358# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
359# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
360# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
361CONFIG_MTD_CFI_I1=y
362CONFIG_MTD_CFI_I2=y
363# CONFIG_MTD_CFI_I4 is not set
364# CONFIG_MTD_CFI_I8 is not set
365# CONFIG_MTD_RAM is not set
366# CONFIG_MTD_ROM is not set
367# CONFIG_MTD_ABSENT is not set
368# CONFIG_MTD_OBSOLETE_CHIPS is not set
369
370#
371# Mapping drivers for chip access
372#
373# CONFIG_MTD_COMPLEX_MAPPINGS is not set
374# CONFIG_MTD_PLATRAM is not set
375
376#
377# Self-contained MTD device drivers
378#
379# CONFIG_MTD_PMC551 is not set
380# CONFIG_MTD_SLRAM is not set
381# CONFIG_MTD_PHRAM is not set
382# CONFIG_MTD_MTDRAM is not set
383# CONFIG_MTD_BLKMTD is not set
384# CONFIG_MTD_BLOCK2MTD is not set
385
386#
387# Disk-On-Chip Device Drivers
388#
389# CONFIG_MTD_DOC2000 is not set
390# CONFIG_MTD_DOC2001 is not set
391# CONFIG_MTD_DOC2001PLUS is not set
392
393#
394# NAND Flash Device Drivers
395#
396CONFIG_MTD_NAND=y
397CONFIG_MTD_NAND_VERIFY_WRITE=y
398CONFIG_MTD_NAND_IDS=y
399# CONFIG_MTD_NAND_DISKONCHIP is not set
400CONFIG_MTD_NAND_BASLER_EXCITE=y
401# CONFIG_MTD_NAND_BASLER_EXCITE_RDNBY is not set
402# CONFIG_MTD_NAND_BASLER_EXCITE_PERF is not set
403# CONFIG_MTD_NAND_NANDSIM is not set
404
405#
406# OneNAND Flash Device Drivers
407#
408# CONFIG_MTD_ONENAND is not set
409
410#
411# Parallel port support
412#
413# CONFIG_PARPORT is not set
414
415#
416# Plug and Play support
417#
418
419#
420# Block devices
421#
422# CONFIG_BLK_CPQ_DA is not set
423# CONFIG_BLK_CPQ_CISS_DA is not set
424# CONFIG_BLK_DEV_DAC960 is not set
425# CONFIG_BLK_DEV_UMEM is not set
426# CONFIG_BLK_DEV_COW_COMMON is not set
427CONFIG_BLK_DEV_LOOP=m
428# CONFIG_BLK_DEV_CRYPTOLOOP is not set
429# CONFIG_BLK_DEV_NBD is not set
430# CONFIG_BLK_DEV_SX8 is not set
431# CONFIG_BLK_DEV_UB is not set
432# CONFIG_BLK_DEV_RAM is not set
433CONFIG_BLK_DEV_RAM_COUNT=16
434# CONFIG_CDROM_PKTCDVD is not set
435# CONFIG_ATA_OVER_ETH is not set
436
437#
438# ATA/ATAPI/MFM/RLL support
439#
440# CONFIG_IDE is not set
441
442#
443# SCSI device support
444#
445# CONFIG_RAID_ATTRS is not set
446CONFIG_SCSI=y
447# CONFIG_SCSI_PROC_FS is not set
448
449#
450# SCSI support type (disk, tape, CD-ROM)
451#
452CONFIG_BLK_DEV_SD=y
453# CONFIG_CHR_DEV_ST is not set
454# CONFIG_CHR_DEV_OSST is not set
455# CONFIG_BLK_DEV_SR is not set
456# CONFIG_CHR_DEV_SG is not set
457# CONFIG_CHR_DEV_SCH is not set
458
459#
460# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
461#
462# CONFIG_SCSI_MULTI_LUN is not set
463# CONFIG_SCSI_CONSTANTS is not set
464# CONFIG_SCSI_LOGGING is not set
465
466#
467# SCSI Transport Attributes
468#
469# CONFIG_SCSI_SPI_ATTRS is not set
470# CONFIG_SCSI_FC_ATTRS is not set
471# CONFIG_SCSI_ISCSI_ATTRS is not set
472# CONFIG_SCSI_SAS_ATTRS is not set
473
474#
475# SCSI low-level drivers
476#
477# CONFIG_ISCSI_TCP is not set
478# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
479# CONFIG_SCSI_3W_9XXX is not set
480# CONFIG_SCSI_ACARD is not set
481# CONFIG_SCSI_AACRAID is not set
482# CONFIG_SCSI_AIC7XXX is not set
483# CONFIG_SCSI_AIC7XXX_OLD is not set
484# CONFIG_SCSI_AIC79XX is not set
485# CONFIG_SCSI_DPT_I2O is not set
486# CONFIG_MEGARAID_NEWGEN is not set
487# CONFIG_MEGARAID_LEGACY is not set
488# CONFIG_MEGARAID_SAS is not set
489# CONFIG_SCSI_SATA is not set
490# CONFIG_SCSI_DMX3191D is not set
491# CONFIG_SCSI_FUTURE_DOMAIN is not set
492# CONFIG_SCSI_IPS is not set
493# CONFIG_SCSI_INITIO is not set
494# CONFIG_SCSI_INIA100 is not set
495# CONFIG_SCSI_SYM53C8XX_2 is not set
496# CONFIG_SCSI_IPR is not set
497# CONFIG_SCSI_QLOGIC_FC is not set
498# CONFIG_SCSI_QLOGIC_1280 is not set
499# CONFIG_SCSI_QLA_FC is not set
500# CONFIG_SCSI_LPFC is not set
501# CONFIG_SCSI_DC395x is not set
502# CONFIG_SCSI_DC390T is not set
503# CONFIG_SCSI_NSP32 is not set
504# CONFIG_SCSI_DEBUG is not set
505
506#
507# Multi-device support (RAID and LVM)
508#
509# CONFIG_MD is not set
510
511#
512# Fusion MPT device support
513#
514# CONFIG_FUSION is not set
515# CONFIG_FUSION_SPI is not set
516# CONFIG_FUSION_FC is not set
517# CONFIG_FUSION_SAS is not set
518
519#
520# IEEE 1394 (FireWire) support
521#
522# CONFIG_IEEE1394 is not set
523
524#
525# I2O device support
526#
527# CONFIG_I2O is not set
528
529#
530# Network device support
531#
532CONFIG_NETDEVICES=y
533# CONFIG_DUMMY is not set
534# CONFIG_BONDING is not set
535# CONFIG_EQUALIZER is not set
536# CONFIG_TUN is not set
537
538#
539# ARCnet devices
540#
541# CONFIG_ARCNET is not set
542
543#
544# PHY device support
545#
546
547#
548# Ethernet (10 or 100Mbit)
549#
550# CONFIG_NET_ETHERNET is not set
551
552#
553# Ethernet (1000 Mbit)
554#
555# CONFIG_ACENIC is not set
556# CONFIG_DL2K is not set
557# CONFIG_E1000 is not set
558# CONFIG_NS83820 is not set
559# CONFIG_HAMACHI is not set
560# CONFIG_YELLOWFIN is not set
561# CONFIG_R8169 is not set
562# CONFIG_SIS190 is not set
563# CONFIG_SKGE is not set
564# CONFIG_SKY2 is not set
565# CONFIG_SK98LIN is not set
566# CONFIG_TIGON3 is not set
567# CONFIG_BNX2 is not set
568# CONFIG_TITAN_GE is not set
569CONFIG_RM9K_GE=m
570
571#
572# Ethernet (10000 Mbit)
573#
574# CONFIG_CHELSIO_T1 is not set
575# CONFIG_IXGB is not set
576# CONFIG_S2IO is not set
577
578#
579# Token Ring devices
580#
581# CONFIG_TR is not set
582
583#
584# Wireless LAN (non-hamradio)
585#
586# CONFIG_NET_RADIO is not set
587
588#
589# Wan interfaces
590#
591# CONFIG_WAN is not set
592# CONFIG_FDDI is not set
593# CONFIG_HIPPI is not set
594# CONFIG_PPP is not set
595# CONFIG_SLIP is not set
596# CONFIG_NET_FC is not set
597# CONFIG_SHAPER is not set
598# CONFIG_NETCONSOLE is not set
599# CONFIG_NETPOLL is not set
600# CONFIG_NET_POLL_CONTROLLER is not set
601
602#
603# ISDN subsystem
604#
605# CONFIG_ISDN is not set
606
607#
608# Telephony Support
609#
610# CONFIG_PHONE is not set
611
612#
613# Input device support
614#
615CONFIG_INPUT=y
616
617#
618# Userland interfaces
619#
620CONFIG_INPUT_MOUSEDEV=m
621CONFIG_INPUT_MOUSEDEV_PSAUX=y
622CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
623CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
624# CONFIG_INPUT_JOYDEV is not set
625# CONFIG_INPUT_TSDEV is not set
626CONFIG_INPUT_EVDEV=m
627# CONFIG_INPUT_EVBUG is not set
628
629#
630# Input Device Drivers
631#
632# CONFIG_INPUT_KEYBOARD is not set
633# CONFIG_INPUT_MOUSE is not set
634# CONFIG_INPUT_JOYSTICK is not set
635# CONFIG_INPUT_TOUCHSCREEN is not set
636# CONFIG_INPUT_MISC is not set
637
638#
639# Hardware I/O ports
640#
641# CONFIG_SERIO is not set
642# CONFIG_GAMEPORT is not set
643
644#
645# Character devices
646#
647CONFIG_VT=y
648CONFIG_VT_CONSOLE=y
649CONFIG_HW_CONSOLE=y
650# CONFIG_SERIAL_NONSTANDARD is not set
651
652#
653# Serial drivers
654#
655CONFIG_SERIAL_8250=y
656CONFIG_SERIAL_8250_CONSOLE=y
657CONFIG_SERIAL_8250_NR_UARTS=2
658CONFIG_SERIAL_8250_RUNTIME_UARTS=2
659CONFIG_SERIAL_8250_EXTENDED=y
660# CONFIG_SERIAL_8250_MANY_PORTS is not set
661CONFIG_SERIAL_8250_SHARE_IRQ=y
662# CONFIG_SERIAL_8250_DETECT_IRQ is not set
663# CONFIG_SERIAL_8250_RSA is not set
664
665#
666# Non-8250 serial port support
667#
668CONFIG_SERIAL_CORE=y
669CONFIG_SERIAL_CORE_CONSOLE=y
670# CONFIG_SERIAL_JSM is not set
671CONFIG_UNIX98_PTYS=y
672# CONFIG_LEGACY_PTYS is not set
673
674#
675# IPMI
676#
677# CONFIG_IPMI_HANDLER is not set
678
679#
680# Watchdog Cards
681#
682CONFIG_WATCHDOG=y
683# CONFIG_WATCHDOG_NOWAYOUT is not set
684
685#
686# Watchdog Device Drivers
687#
688# CONFIG_SOFT_WATCHDOG is not set
689CONFIG_WDT_RM9K_GPI=m
690
691#
692# PCI-based Watchdog Cards
693#
694# CONFIG_PCIPCWATCHDOG is not set
695# CONFIG_WDTPCI is not set
696
697#
698# USB-based Watchdog Cards
699#
700# CONFIG_USBPCWATCHDOG is not set
701# CONFIG_RTC is not set
702# CONFIG_GEN_RTC is not set
703# CONFIG_DTLK is not set
704# CONFIG_R3964 is not set
705# CONFIG_APPLICOM is not set
706
707#
708# Ftape, the floppy tape device driver
709#
710# CONFIG_DRM is not set
711# CONFIG_RAW_DRIVER is not set
712
713#
714# TPM devices
715#
716# CONFIG_TCG_TPM is not set
717# CONFIG_TELCLOCK is not set
718
719#
720# I2C support
721#
722# CONFIG_I2C is not set
723
724#
725# SPI support
726#
727# CONFIG_SPI is not set
728# CONFIG_SPI_MASTER is not set
729
730#
731# Dallas's 1-wire bus
732#
733# CONFIG_W1 is not set
734
735#
736# Hardware Monitoring support
737#
738# CONFIG_HWMON is not set
739# CONFIG_HWMON_VID is not set
740
741#
742# Misc devices
743#
744
745#
746# Multimedia Capabilities Port drivers
747#
748
749#
750# Multimedia devices
751#
752# CONFIG_VIDEO_DEV is not set
753
754#
755# Digital Video Broadcasting Devices
756#
757# CONFIG_DVB is not set
758
759#
760# Graphics support
761#
762CONFIG_FB=y
763CONFIG_FB_CFB_FILLRECT=y
764CONFIG_FB_CFB_COPYAREA=y
765CONFIG_FB_CFB_IMAGEBLIT=y
766# CONFIG_FB_MACMODES is not set
767# CONFIG_FB_MODE_HELPERS is not set
768# CONFIG_FB_TILEBLITTING is not set
769# CONFIG_FB_CIRRUS is not set
770# CONFIG_FB_PM2 is not set
771# CONFIG_FB_CYBER2000 is not set
772# CONFIG_FB_ASILIANT is not set
773# CONFIG_FB_IMSTT is not set
774# CONFIG_FB_S1D13XXX is not set
775# CONFIG_FB_NVIDIA is not set
776# CONFIG_FB_RIVA is not set
777# CONFIG_FB_MATROX is not set
778# CONFIG_FB_RADEON_OLD is not set
779# CONFIG_FB_RADEON is not set
780# CONFIG_FB_ATY128 is not set
781# CONFIG_FB_ATY is not set
782# CONFIG_FB_SAVAGE is not set
783# CONFIG_FB_SIS is not set
784# CONFIG_FB_NEOMAGIC is not set
785# CONFIG_FB_KYRO is not set
786# CONFIG_FB_3DFX is not set
787# CONFIG_FB_VOODOO1 is not set
788# CONFIG_FB_SMIVGX is not set
789# CONFIG_FB_TRIDENT is not set
790# CONFIG_FB_VIRTUAL is not set
791CONFIG_FB_DD=y
792
793#
794# Console display driver support
795#
796# CONFIG_VGA_CONSOLE is not set
797CONFIG_DUMMY_CONSOLE=y
798CONFIG_FRAMEBUFFER_CONSOLE=m
799# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
800# CONFIG_FONTS is not set
801CONFIG_FONT_8x8=y
802CONFIG_FONT_8x16=y
803
804#
805# Logo configuration
806#
807# CONFIG_LOGO is not set
808# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
809
810#
811# Sound
812#
813# CONFIG_SOUND is not set
814
815#
816# USB support
817#
818CONFIG_USB_ARCH_HAS_HCD=y
819CONFIG_USB_ARCH_HAS_OHCI=y
820CONFIG_USB=y
821# CONFIG_USB_DEBUG is not set
822
823#
824# Miscellaneous USB options
825#
826CONFIG_USB_DEVICEFS=y
827# CONFIG_USB_BANDWIDTH is not set
828# CONFIG_USB_DYNAMIC_MINORS is not set
829# CONFIG_USB_OTG is not set
830
831#
832# USB Host Controller Drivers
833#
834CONFIG_USB_EHCI_HCD=y
835# CONFIG_USB_EHCI_SPLIT_ISO is not set
836# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
837# CONFIG_USB_ISP116X_HCD is not set
838CONFIG_USB_OHCI_HCD=y
839# CONFIG_USB_OHCI_BIG_ENDIAN is not set
840CONFIG_USB_OHCI_LITTLE_ENDIAN=y
841# CONFIG_USB_UHCI_HCD is not set
842# CONFIG_USB_SL811_HCD is not set
843
844#
845# USB Device Class drivers
846#
847# CONFIG_USB_ACM is not set
848# CONFIG_USB_PRINTER is not set
849
850#
851# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
852#
853
854#
855# may also be needed; see USB_STORAGE Help for more information
856#
857CONFIG_USB_STORAGE=y
858# CONFIG_USB_STORAGE_DEBUG is not set
859# CONFIG_USB_STORAGE_DATAFAB is not set
860# CONFIG_USB_STORAGE_FREECOM is not set
861# CONFIG_USB_STORAGE_DPCM is not set
862# CONFIG_USB_STORAGE_USBAT is not set
863# CONFIG_USB_STORAGE_SDDR09 is not set
864# CONFIG_USB_STORAGE_SDDR55 is not set
865# CONFIG_USB_STORAGE_JUMPSHOT is not set
866# CONFIG_USB_STORAGE_ALAUDA is not set
867# CONFIG_USB_STORAGE_ONETOUCH is not set
868# CONFIG_USB_LIBUSUAL is not set
869
870#
871# USB Input Devices
872#
873CONFIG_USB_HID=m
874CONFIG_USB_HIDINPUT=y
875# CONFIG_USB_HIDINPUT_POWERBOOK is not set
876# CONFIG_HID_FF is not set
877# CONFIG_USB_HIDDEV is not set
878
879#
880# USB HID Boot Protocol drivers
881#
882# CONFIG_USB_KBD is not set
883# CONFIG_USB_MOUSE is not set
884# CONFIG_USB_AIPTEK is not set
885# CONFIG_USB_WACOM is not set
886# CONFIG_USB_ACECAD is not set
887# CONFIG_USB_KBTAB is not set
888# CONFIG_USB_POWERMATE is not set
889# CONFIG_USB_MTOUCH is not set
890# CONFIG_USB_ITMTOUCH is not set
891# CONFIG_USB_EGALAX is not set
892# CONFIG_USB_YEALINK is not set
893# CONFIG_USB_XPAD is not set
894# CONFIG_USB_ATI_REMOTE is not set
895# CONFIG_USB_ATI_REMOTE2 is not set
896# CONFIG_USB_KEYSPAN_REMOTE is not set
897# CONFIG_USB_APPLETOUCH is not set
898
899#
900# USB Imaging devices
901#
902# CONFIG_USB_MDC800 is not set
903# CONFIG_USB_MICROTEK is not set
904
905#
906# USB Multimedia devices
907#
908# CONFIG_USB_DABUSB is not set
909
910#
911# Video4Linux support is needed for USB Multimedia device support
912#
913
914#
915# USB Network Adapters
916#
917# CONFIG_USB_CATC is not set
918# CONFIG_USB_KAWETH is not set
919# CONFIG_USB_PEGASUS is not set
920# CONFIG_USB_RTL8150 is not set
921# CONFIG_USB_USBNET is not set
922# CONFIG_USB_MON is not set
923
924#
925# USB port drivers
926#
927
928#
929# USB Serial Converter support
930#
931# CONFIG_USB_SERIAL is not set
932
933#
934# USB Miscellaneous drivers
935#
936# CONFIG_USB_EMI62 is not set
937# CONFIG_USB_EMI26 is not set
938# CONFIG_USB_AUERSWALD is not set
939# CONFIG_USB_RIO500 is not set
940CONFIG_USB_ARTTFT=m
941# CONFIG_USB_ARTTOUCH is not set
942# CONFIG_USB_LEGOTOWER is not set
943# CONFIG_USB_LCD is not set
944# CONFIG_USB_LED is not set
945# CONFIG_USB_CYTHERM is not set
946# CONFIG_USB_PHIDGETKIT is not set
947# CONFIG_USB_PHIDGETSERVO is not set
948# CONFIG_USB_IDMOUSE is not set
949# CONFIG_USB_SISUSBVGA is not set
950# CONFIG_USB_LD is not set
951# CONFIG_USB_TEST is not set
952
953#
954# USB DSL modem support
955#
956
957#
958# USB Gadget Support
959#
960# CONFIG_USB_GADGET is not set
961
962#
963# MMC/SD Card support
964#
965# CONFIG_MMC is not set
966
967#
968# InfiniBand support
969#
970# CONFIG_INFINIBAND is not set
971
972#
973# SN Devices
974#
975
976#
977# EDAC - error detection and reporting (RAS)
978#
979
980#
981# eXcite frame capture support
982#
983CONFIG_EXCITE_FCAP=m
984CONFIG_EXCITE_FCAP_GPI=m
985
986#
987# File systems
988#
989CONFIG_EXT2_FS=y
990# CONFIG_EXT2_FS_XATTR is not set
991# CONFIG_EXT2_FS_XIP is not set
992# CONFIG_EXT3_FS is not set
993# CONFIG_REISERFS_FS is not set
994# CONFIG_JFS_FS is not set
995# CONFIG_FS_POSIX_ACL is not set
996# CONFIG_XFS_FS is not set
997# CONFIG_OCFS2_FS is not set
998# CONFIG_MINIX_FS is not set
999# CONFIG_ROMFS_FS is not set
1000CONFIG_INOTIFY=y
1001# CONFIG_QUOTA is not set
1002# CONFIG_DNOTIFY is not set
1003# CONFIG_AUTOFS_FS is not set
1004# CONFIG_AUTOFS4_FS is not set
1005# CONFIG_FUSE_FS is not set
1006
1007#
1008# CD-ROM/DVD Filesystems
1009#
1010# CONFIG_ISO9660_FS is not set
1011# CONFIG_UDF_FS is not set
1012
1013#
1014# DOS/FAT/NT Filesystems
1015#
1016CONFIG_FAT_FS=m
1017CONFIG_MSDOS_FS=m
1018CONFIG_VFAT_FS=m
1019CONFIG_FAT_DEFAULT_CODEPAGE=437
1020CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1021# CONFIG_NTFS_FS is not set
1022
1023#
1024# Pseudo filesystems
1025#
1026CONFIG_PROC_FS=y
1027CONFIG_PROC_KCORE=y
1028CONFIG_SYSFS=y
1029CONFIG_TMPFS=y
1030# CONFIG_HUGETLB_PAGE is not set
1031CONFIG_RAMFS=y
1032# CONFIG_RELAYFS_FS is not set
1033# CONFIG_CONFIGFS_FS is not set
1034
1035#
1036# Miscellaneous filesystems
1037#
1038# CONFIG_ADFS_FS is not set
1039# CONFIG_AFFS_FS is not set
1040# CONFIG_HFS_FS is not set
1041# CONFIG_HFSPLUS_FS is not set
1042# CONFIG_BEFS_FS is not set
1043# CONFIG_BFS_FS is not set
1044# CONFIG_EFS_FS is not set
1045# CONFIG_JFFS_FS is not set
1046CONFIG_JFFS2_FS=y
1047CONFIG_JFFS2_FS_DEBUG=0
1048CONFIG_JFFS2_FS_WRITEBUFFER=y
1049# CONFIG_JFFS2_SUMMARY is not set
1050# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1051CONFIG_JFFS2_ZLIB=y
1052CONFIG_JFFS2_RTIME=y
1053# CONFIG_JFFS2_RUBIN is not set
1054# CONFIG_CRAMFS is not set
1055# CONFIG_VXFS_FS is not set
1056# CONFIG_HPFS_FS is not set
1057# CONFIG_QNX4FS_FS is not set
1058# CONFIG_SYSV_FS is not set
1059# CONFIG_UFS_FS is not set
1060
1061#
1062# Network File Systems
1063#
1064CONFIG_NFS_FS=y
1065CONFIG_NFS_V3=y
1066# CONFIG_NFS_V3_ACL is not set
1067# CONFIG_NFS_V4 is not set
1068# CONFIG_NFS_DIRECTIO is not set
1069# CONFIG_NFSD is not set
1070CONFIG_ROOT_NFS=y
1071CONFIG_LOCKD=y
1072CONFIG_LOCKD_V4=y
1073CONFIG_NFS_COMMON=y
1074CONFIG_SUNRPC=y
1075# CONFIG_RPCSEC_GSS_KRB5 is not set
1076# CONFIG_RPCSEC_GSS_SPKM3 is not set
1077# CONFIG_SMB_FS is not set
1078# CONFIG_CIFS is not set
1079# CONFIG_NCP_FS is not set
1080# CONFIG_CODA_FS is not set
1081# CONFIG_AFS_FS is not set
1082# CONFIG_9P_FS is not set
1083
1084#
1085# Partition Types
1086#
1087CONFIG_PARTITION_ADVANCED=y
1088# CONFIG_ACORN_PARTITION is not set
1089# CONFIG_OSF_PARTITION is not set
1090# CONFIG_AMIGA_PARTITION is not set
1091# CONFIG_ATARI_PARTITION is not set
1092# CONFIG_MAC_PARTITION is not set
1093CONFIG_MSDOS_PARTITION=y
1094# CONFIG_BSD_DISKLABEL is not set
1095# CONFIG_MINIX_SUBPARTITION is not set
1096# CONFIG_SOLARIS_X86_PARTITION is not set
1097# CONFIG_UNIXWARE_DISKLABEL is not set
1098# CONFIG_LDM_PARTITION is not set
1099# CONFIG_SGI_PARTITION is not set
1100# CONFIG_ULTRIX_PARTITION is not set
1101# CONFIG_SUN_PARTITION is not set
1102# CONFIG_KARMA_PARTITION is not set
1103# CONFIG_EFI_PARTITION is not set
1104
1105#
1106# Native Language Support
1107#
1108CONFIG_NLS=y
1109CONFIG_NLS_DEFAULT="iso8859-1"
1110CONFIG_NLS_CODEPAGE_437=m
1111# CONFIG_NLS_CODEPAGE_737 is not set
1112# CONFIG_NLS_CODEPAGE_775 is not set
1113CONFIG_NLS_CODEPAGE_850=m
1114# CONFIG_NLS_CODEPAGE_852 is not set
1115# CONFIG_NLS_CODEPAGE_855 is not set
1116# CONFIG_NLS_CODEPAGE_857 is not set
1117# CONFIG_NLS_CODEPAGE_860 is not set
1118# CONFIG_NLS_CODEPAGE_861 is not set
1119# CONFIG_NLS_CODEPAGE_862 is not set
1120# CONFIG_NLS_CODEPAGE_863 is not set
1121# CONFIG_NLS_CODEPAGE_864 is not set
1122# CONFIG_NLS_CODEPAGE_865 is not set
1123# CONFIG_NLS_CODEPAGE_866 is not set
1124# CONFIG_NLS_CODEPAGE_869 is not set
1125# CONFIG_NLS_CODEPAGE_936 is not set
1126# CONFIG_NLS_CODEPAGE_950 is not set
1127# CONFIG_NLS_CODEPAGE_932 is not set
1128# CONFIG_NLS_CODEPAGE_949 is not set
1129# CONFIG_NLS_CODEPAGE_874 is not set
1130# CONFIG_NLS_ISO8859_8 is not set
1131# CONFIG_NLS_CODEPAGE_1250 is not set
1132# CONFIG_NLS_CODEPAGE_1251 is not set
1133# CONFIG_NLS_ASCII is not set
1134CONFIG_NLS_ISO8859_1=m
1135# CONFIG_NLS_ISO8859_2 is not set
1136# CONFIG_NLS_ISO8859_3 is not set
1137# CONFIG_NLS_ISO8859_4 is not set
1138# CONFIG_NLS_ISO8859_5 is not set
1139# CONFIG_NLS_ISO8859_6 is not set
1140# CONFIG_NLS_ISO8859_7 is not set
1141# CONFIG_NLS_ISO8859_9 is not set
1142# CONFIG_NLS_ISO8859_13 is not set
1143# CONFIG_NLS_ISO8859_14 is not set
1144# CONFIG_NLS_ISO8859_15 is not set
1145# CONFIG_NLS_KOI8_R is not set
1146# CONFIG_NLS_KOI8_U is not set
1147# CONFIG_NLS_UTF8 is not set
1148
1149#
1150# Profiling support
1151#
1152# CONFIG_PROFILING is not set
1153
1154#
1155# Kernel hacking
1156#
1157# CONFIG_PRINTK_TIME is not set
1158# CONFIG_MAGIC_SYSRQ is not set
1159# CONFIG_DEBUG_KERNEL is not set
1160CONFIG_LOG_BUF_SHIFT=14
1161CONFIG_CROSSCOMPILE=y
1162CONFIG_CMDLINE=""
1163
1164#
1165# Security options
1166#
1167# CONFIG_KEYS is not set
1168# CONFIG_SECURITY is not set
1169
1170#
1171# Cryptographic options
1172#
1173CONFIG_CRYPTO=y
1174# CONFIG_CRYPTO_HMAC is not set
1175# CONFIG_CRYPTO_NULL is not set
1176# CONFIG_CRYPTO_MD4 is not set
1177# CONFIG_CRYPTO_MD5 is not set
1178# CONFIG_CRYPTO_SHA1 is not set
1179# CONFIG_CRYPTO_SHA256 is not set
1180# CONFIG_CRYPTO_SHA512 is not set
1181# CONFIG_CRYPTO_WP512 is not set
1182# CONFIG_CRYPTO_TGR192 is not set
1183# CONFIG_CRYPTO_DES is not set
1184# CONFIG_CRYPTO_BLOWFISH is not set
1185# CONFIG_CRYPTO_TWOFISH is not set
1186# CONFIG_CRYPTO_SERPENT is not set
1187# CONFIG_CRYPTO_AES is not set
1188# CONFIG_CRYPTO_CAST5 is not set
1189# CONFIG_CRYPTO_CAST6 is not set
1190# CONFIG_CRYPTO_TEA is not set
1191# CONFIG_CRYPTO_ARC4 is not set
1192# CONFIG_CRYPTO_KHAZAD is not set
1193# CONFIG_CRYPTO_ANUBIS is not set
1194# CONFIG_CRYPTO_DEFLATE is not set
1195# CONFIG_CRYPTO_MICHAEL_MIC is not set
1196# CONFIG_CRYPTO_CRC32C is not set
1197# CONFIG_CRYPTO_TEST is not set
1198
1199#
1200# Hardware crypto devices
1201#
1202
1203#
1204# Library routines
1205#
1206# CONFIG_CRC_CCITT is not set
1207# CONFIG_CRC16 is not set
1208CONFIG_CRC32=y
1209# CONFIG_LIBCRC32C is not set
1210CONFIG_ZLIB_INFLATE=y
1211CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 56000a069604..465778c5d816 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
23# 23#
24# These are still pretty much in the old state, watch, go blind. 24# These are still pretty much in the old state, watch, go blind.
25# 25#
26obj-$(CONFIG_BASLER_EXCITE) = ops-titan.o pci-excite.o fixup-excite.o
26obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o 27obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
27obj-$(CONFIG_LASAT) += pci-lasat.o 28obj-$(CONFIG_LASAT) += pci-lasat.o
28obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o 29obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
diff --git a/arch/mips/pci/fixup-excite.c b/arch/mips/pci/fixup-excite.c
new file mode 100644
index 000000000000..1da696d43f00
--- /dev/null
+++ b/arch/mips/pci/fixup-excite.c
@@ -0,0 +1,36 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/pci.h>
22#include <excite.h>
23
24int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
25{
26 if (pin == 0)
27 return -1;
28
29 return USB_IRQ; /* USB controller is the only PCI device */
30}
31
32/* Do platform specific device initialization at pci_enable_device() time */
33int pcibios_plat_dev_init(struct pci_dev *dev)
34{
35 return 0;
36}
diff --git a/arch/mips/pci/ops-titan.c b/arch/mips/pci/ops-titan.c
index 233ec6f2054d..ebf8fc40e9b2 100644
--- a/arch/mips/pci/ops-titan.c
+++ b/arch/mips/pci/ops-titan.c
@@ -26,8 +26,19 @@
26#include <linux/pci.h> 26#include <linux/pci.h>
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28 28
29#include <asm/titan_dep.h> 29#include <asm/pci.h>
30#include <asm/io.h>
31#include <asm/rm9k-ocd.h>
30 32
33/*
34 * PCI specific defines
35 */
36#define TITAN_PCI_0_CONFIG_ADDRESS 0x780
37#define TITAN_PCI_0_CONFIG_DATA 0x784
38
39/*
40 * Titan PCI Config Read Byte
41 */
31static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg, 42static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
32 int size, u32 * val) 43 int size, u32 * val)
33{ 44{
@@ -43,8 +54,8 @@ static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
43 54
44 55
45 /* start the configuration cycle */ 56 /* start the configuration cycle */
46 TITAN_WRITE(TITAN_PCI_0_CONFIG_ADDRESS, address); 57 ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
47 tmp = TITAN_READ(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3); 58 tmp = ocd_readl(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3);
48 59
49 switch (size) { 60 switch (size) {
50 case 1: 61 case 1:
@@ -71,20 +82,20 @@ static int titan_write_config(struct pci_bus *bus, unsigned int devfn, int reg,
71 (reg & 0xfc) | 0x80000000; 82 (reg & 0xfc) | 0x80000000;
72 83
73 /* start the configuration cycle */ 84 /* start the configuration cycle */
74 TITAN_WRITE(TITAN_PCI_0_CONFIG_ADDRESS, address); 85 ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
75 86
76 /* write the data */ 87 /* write the data */
77 switch (size) { 88 switch (size) {
78 case 1: 89 case 1:
79 TITAN_WRITE_8(TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3), val); 90 ocd_writeb(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3));
80 break; 91 break;
81 92
82 case 2: 93 case 2:
83 TITAN_WRITE_16(TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2), val); 94 ocd_writew(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2));
84 break; 95 break;
85 96
86 case 4: 97 case 4:
87 TITAN_WRITE(TITAN_PCI_0_CONFIG_DATA, val); 98 ocd_writel(val, TITAN_PCI_0_CONFIG_DATA);
88 break; 99 break;
89 } 100 }
90 101
diff --git a/arch/mips/pci/pci-excite.c b/arch/mips/pci/pci-excite.c
new file mode 100644
index 000000000000..3c86c77cb74f
--- /dev/null
+++ b/arch/mips/pci/pci-excite.c
@@ -0,0 +1,149 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 * Based on the PMC-Sierra Yosemite board support by Ralf Baechle.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/pci.h>
24#include <linux/bitops.h>
25#include <asm/rm9k-ocd.h>
26#include <excite.h>
27
28
29extern struct pci_ops titan_pci_ops;
30
31
32static struct resource
33 mem_resource = {
34 .name = "PCI memory",
35 .start = EXCITE_PHYS_PCI_MEM,
36 .end = EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1,
37 .flags = IORESOURCE_MEM
38 },
39 io_resource = {
40 .name = "PCI I/O",
41 .start = EXCITE_PHYS_PCI_IO,
42 .end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1,
43 .flags = IORESOURCE_IO
44 };
45
46
47static struct pci_controller bx_controller = {
48 .pci_ops = &titan_pci_ops,
49 .mem_resource = &mem_resource,
50 .mem_offset = 0x00000000UL,
51 .io_resource = &io_resource,
52 .io_offset = 0x00000000UL
53};
54
55
56static char
57 iopage_failed[] __initdata = "Cannot allocate PCI I/O page",
58 modebits_no_pci[] __initdata = "PCI is not configured in mode bits";
59
60#define RM9000x2_OCD_HTSC 0x0604
61#define RM9000x2_OCD_HTBHL 0x060c
62#define RM9000x2_OCD_PCIHRST 0x078c
63
64#define RM9K_OCD_MODEBIT1 0x00d4 /* (MODEBIT1) Mode Bit 1 */
65#define RM9K_OCD_CPHDCR 0x00f4 /* CPU-PCI/HT Data Control. */
66
67#define PCISC_FB2B 0x00000200
68#define PCISC_MWICG 0x00000010
69#define PCISC_EMC 0x00000004
70#define PCISC_ERMA 0x00000002
71
72
73
74static int __init basler_excite_pci_setup(void)
75{
76 const unsigned int fullbars = memsize / (256 << 20);
77 unsigned int i;
78
79 /* Check modebits to see if PCI is really enabled. */
80 if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1))
81 panic(modebits_no_pci);
82
83 if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO,
84 "Memory-mapped PCI I/O page"))
85 panic(iopage_failed);
86
87 /* Enable PCI 0 as master for config cycles */
88 ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC);
89
90
91 /* Set up latency timer */
92 ocd_writel(0x8008, RM9000x2_OCD_HTBHL);
93
94 /* Setup host IO and Memory space */
95 ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7);
96 ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7);
97 ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8);
98 ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8);
99
100 /* Set up PCI BARs to map all installed memory */
101 for (i = 0; i < 6; i++) {
102 const unsigned int bar = 0x610 + i * 4;
103
104 if (i < fullbars) {
105 ocd_writel(0x10000000 * i, bar);
106 ocd_writel(0x01000000 * i, bar + 0x140);
107 ocd_writel(0x0ffff029, bar + 0x100);
108 continue;
109 }
110
111 if (i == fullbars) {
112 int o;
113 u32 mask;
114
115 const unsigned long rem = memsize - i * 0x10000000;
116 if (!rem) {
117 ocd_writel(0x00000000, bar + 0x100);
118 continue;
119 }
120
121 o = ffs(rem) - 1;
122 if (rem & ~(0x1 << o))
123 o++;
124 mask = ((0x1 << o) & 0x0ffff000) - 0x1000;
125 ocd_writel(0x10000000 * i, bar);
126 ocd_writel(0x01000000 * i, bar + 0x140);
127 ocd_writel(0x00000029 | mask, bar + 0x100);
128 continue;
129 }
130
131 ocd_writel(0x00000000, bar + 0x100);
132 }
133
134 /* Finally, enable the PCI interupt */
135#if USB_IRQ > 7
136 set_c0_intcontrol(1 << USB_IRQ);
137#else
138 set_c0_status(1 << (USB_IRQ + 8));
139#endif
140
141 ioport_resource.start = EXCITE_PHYS_PCI_IO;
142 ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1;
143 set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO));
144 register_pci_controller(&bx_controller);
145 return 0;
146}
147
148
149arch_initcall(basler_excite_pci_setup);
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index 72fa6dc45523..3b745e76f429 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -217,6 +217,7 @@
217 */ 217 */
218#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ 218#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
219#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */ 219#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
220#define MACH_TITAN_EXCITE 2 /* Basler eXcite */
220 221
221/* 222/*
222 * Valid machtype for group NEC EMMA2RH 223 * Valid machtype for group NEC EMMA2RH
diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/include/asm-mips/mach-excite/cpu-feature-overrides.h
new file mode 100644
index 000000000000..abb76b2fd865
--- /dev/null
+++ b/include/asm-mips/mach-excite/cpu-feature-overrides.h
@@ -0,0 +1,40 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
7 */
8#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
10
11/*
12 * Basler eXcite has an RM9122 processor.
13 */
14#define cpu_has_watch 1
15#define cpu_has_mips16 0
16#define cpu_has_divec 0
17#define cpu_has_vce 0
18#define cpu_has_cache_cdex_p 0
19#define cpu_has_cache_cdex_s 0
20#define cpu_has_prefetch 1
21#define cpu_has_mcheck 0
22#define cpu_has_ejtag 0
23
24#define cpu_has_llsc 1
25#define cpu_has_vtag_icache 0
26#define cpu_has_dc_aliases 0
27#define cpu_has_ic_fills_f_dc 0
28#define cpu_has_dsp 0
29#define cpu_icache_snoops_remote_store 0
30
31#define cpu_has_nofpuex 0
32#define cpu_has_64bits 1
33
34#define cpu_has_subset_pcaches 0
35
36#define cpu_dcache_line_size() 32
37#define cpu_icache_line_size() 32
38#define cpu_scache_line_size() 32
39
40#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-excite/excite.h b/include/asm-mips/mach-excite/excite.h
new file mode 100644
index 000000000000..c52610de2b3a
--- /dev/null
+++ b/include/asm-mips/mach-excite/excite.h
@@ -0,0 +1,155 @@
1#ifndef __EXCITE_H__
2#define __EXCITE_H__
3
4#include <linux/config.h>
5#include <linux/init.h>
6#include <asm/addrspace.h>
7#include <asm/types.h>
8
9#define EXCITE_CPU_EXT_CLOCK 100000000
10
11#if !defined(__ASSEMBLER__)
12void __init excite_kgdb_init(void);
13void excite_procfs_init(void);
14extern unsigned long memsize;
15extern char modetty[];
16extern u32 unit_id;
17#endif
18
19/* Base name for XICAP devices */
20#define XICAP_NAME "xicap_gpi"
21
22/* OCD register offsets */
23#define LKB0 0x0038
24#define LKB5 0x0128
25#define LKM5 0x012C
26#define LKB7 0x0138
27#define LKM7 0x013c
28#define LKB8 0x0140
29#define LKM8 0x0144
30#define LKB9 0x0148
31#define LKM9 0x014c
32#define LKB10 0x0150
33#define LKM10 0x0154
34#define LKB11 0x0158
35#define LKM11 0x015c
36#define LKB12 0x0160
37#define LKM12 0x0164
38#define LKB13 0x0168
39#define LKM13 0x016c
40#define LDP0 0x0200
41#define LDP1 0x0210
42#define LDP2 0x0220
43#define LDP3 0x0230
44#define INTPIN0 0x0A40
45#define INTPIN1 0x0A44
46#define INTPIN2 0x0A48
47#define INTPIN3 0x0A4C
48#define INTPIN4 0x0A50
49#define INTPIN5 0x0A54
50#define INTPIN6 0x0A58
51#define INTPIN7 0x0A5C
52
53
54
55
56/* TITAN register offsets */
57#define CPRR 0x0004
58#define CPDSR 0x0008
59#define CPTC0R 0x000c
60#define CPTC1R 0x0010
61#define CPCFG0 0x0020
62#define CPCFG1 0x0024
63#define CPDST0A 0x0028
64#define CPDST0B 0x002c
65#define CPDST1A 0x0030
66#define CPDST1B 0x0034
67#define CPXDSTA 0x0038
68#define CPXDSTB 0x003c
69#define CPXCISRA 0x0048
70#define CPXCISRB 0x004c
71#define CPGIG0ER 0x0050
72#define CPGIG1ER 0x0054
73#define CPGRWL 0x0068
74#define CPURSLMT 0x00f8
75#define UACFG 0x0200
76#define UAINTS 0x0204
77#define SDRXFCIE 0x4828
78#define SDTXFCIE 0x4928
79#define INTP0Status0 0x1B00
80#define INTP0Mask0 0x1B04
81#define INTP0Set0 0x1B08
82#define INTP0Clear0 0x1B0C
83#define GXCFG 0x5000
84#define GXDMADRPFX 0x5018
85#define GXDMA_DESCADR 0x501c
86#define GXCH0TDESSTRT 0x5054
87
88/* IRQ definitions */
89#define NMICONFIG 0xac0
90#define TITAN_MSGINT 0xc4
91#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2)
92#define FPGA0_MSGINT 0x5a
93#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2)
94#define FPGA1_MSGINT 0x7b
95#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2)
96#define PHY_MSGINT 0x9c
97#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2)
98
99#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
100/* Pre-release units used interrupt pin #9 */
101#define USB_IRQ 11
102#else
103/* Re-designed units use interrupt pin #1 */
104#define USB_MSGINT 0x39
105#define USB_IRQ ((USB_MSGINT / 0x20) + 2)
106#endif
107#define TIMER_IRQ 12
108
109
110/* Device address ranges */
111#define EXCITE_OFFS_OCD 0x1fffc000
112#define EXCITE_SIZE_OCD (16 * 1024)
113#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD)
114#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD)
115
116#define EXCITE_OFFS_SCRAM 0x1fffa000
117#define EXCITE_SIZE_SCRAM (8 << 10)
118#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM)
119#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM)
120
121#define EXCITE_OFFS_PCI_IO 0x1fff8000
122#define EXCITE_SIZE_PCI_IO (8 << 10)
123#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO)
124#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
125
126#define EXCITE_OFFS_TITAN 0x1fff0000
127#define EXCITE_SIZE_TITAN (32 << 10)
128#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN)
129#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN)
130
131#define EXCITE_OFFS_PCI_MEM 0x1ffe0000
132#define EXCITE_SIZE_PCI_MEM (64 << 10)
133#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM)
134#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
135
136#define EXCITE_OFFS_FPGA 0x1ffdc000
137#define EXCITE_SIZE_FPGA (16 << 10)
138#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA)
139#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA)
140
141#define EXCITE_OFFS_NAND 0x1ffd8000
142#define EXCITE_SIZE_NAND (16 << 10)
143#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND)
144#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND)
145
146#define EXCITE_OFFS_BOOTROM 0x1f000000
147#define EXCITE_SIZE_BOOTROM (8 << 20)
148#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM)
149#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
150
151/* FPGA address offsets */
152#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */
153#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */
154
155#endif /* __EXCITE_H__ */
diff --git a/include/asm-mips/mach-excite/excite_nandflash.h b/include/asm-mips/mach-excite/excite_nandflash.h
new file mode 100644
index 000000000000..c4cf6140622e
--- /dev/null
+++ b/include/asm-mips/mach-excite/excite_nandflash.h
@@ -0,0 +1,7 @@
1#ifndef __EXCITE_NANDFLASH_H__
2#define __EXCITE_NANDFLASH_H__
3
4/* Resource names */
5#define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs"
6
7#endif /* __EXCITE_NANDFLASH_H__ */
diff --git a/include/asm-mips/mach-excite/rm9k_eth.h b/include/asm-mips/mach-excite/rm9k_eth.h
new file mode 100644
index 000000000000..94705a46f72e
--- /dev/null
+++ b/include/asm-mips/mach-excite/rm9k_eth.h
@@ -0,0 +1,23 @@
1#if !defined(__RM9K_ETH_H__)
2#define __RM9K_ETH_H__
3
4#define RM9K_GE_NAME "rm9k_ge"
5
6/* Resource names */
7#define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac"
8#define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat"
9#define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc"
10#define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma"
11#define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx"
12#define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx"
13#define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx"
14#define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx"
15#define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy"
16#define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx"
17#define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx"
18#define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main"
19#define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy"
20#define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice"
21#define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel"
22
23#endif /* !defined(__RM9K_ETH_H__) */
diff --git a/include/asm-mips/mach-excite/rm9k_wdt.h b/include/asm-mips/mach-excite/rm9k_wdt.h
new file mode 100644
index 000000000000..3fa3c08d2da7
--- /dev/null
+++ b/include/asm-mips/mach-excite/rm9k_wdt.h
@@ -0,0 +1,12 @@
1#ifndef __RM9K_WDT_H__
2#define __RM9K_WDT_H__
3
4/* Device name */
5#define WDT_NAME "wdt_gpi"
6
7/* Resource names */
8#define WDT_RESOURCE_REGS "excite_watchdog_regs"
9#define WDT_RESOURCE_IRQ "excite_watchdog_irq"
10#define WDT_RESOURCE_COUNTER "excite_watchdog_counter"
11
12#endif /* __RM9K_WDT_H__ */
diff --git a/include/asm-mips/mach-excite/rm9k_xicap.h b/include/asm-mips/mach-excite/rm9k_xicap.h
new file mode 100644
index 000000000000..009577734a8d
--- /dev/null
+++ b/include/asm-mips/mach-excite/rm9k_xicap.h
@@ -0,0 +1,16 @@
1#ifndef __EXCITE_XICAP_H__
2#define __EXCITE_XICAP_H__
3
4
5/* Resource names */
6#define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx"
7#define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx"
8#define XICAP_RESOURCE_XDMA "xicap_xdma"
9#define XICAP_RESOURCE_DMADESC "xicap_dmadesc"
10#define XICAP_RESOURCE_PKTPROC "xicap_pktproc"
11#define XICAP_RESOURCE_IRQ "xicap_irq"
12#define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice"
13#define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks"
14#define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream"
15
16#endif /* __EXCITE_XICAP_H__ */
diff --git a/include/asm-mips/rm9k-ocd.h b/include/asm-mips/rm9k-ocd.h
new file mode 100644
index 000000000000..b0b80d9ecf96
--- /dev/null
+++ b/include/asm-mips/rm9k-ocd.h
@@ -0,0 +1,56 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#if !defined(_ASM_RM9K_OCD_H)
21#define _ASM_RM9K_OCD_H
22
23#include <linux/types.h>
24#include <linux/spinlock.h>
25#include <asm/io.h>
26
27extern volatile void __iomem * const ocd_base;
28extern volatile void __iomem * const titan_base;
29
30#define ocd_addr(__x__) (ocd_base + (__x__))
31#define titan_addr(__x__) (titan_base + (__x__))
32#define scram_addr(__x__) (scram_base + (__x__))
33
34/* OCD register access */
35#define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__))
36#define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__))
37#define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__))
38#define ocd_writel(__val__, __offs__) \
39 __raw_writel((__val__), ocd_addr(__offs__))
40#define ocd_writew(__val__, __offs__) \
41 __raw_writew((__val__), ocd_addr(__offs__))
42#define ocd_writeb(__val__, __offs__) \
43 __raw_writeb((__val__), ocd_addr(__offs__))
44
45/* TITAN register access - 32 bit-wide only */
46#define titan_readl(__offs__) __raw_readl(titan_addr(__offs__))
47#define titan_writel(__val__, __offs__) \
48 __raw_writel((__val__), titan_addr(__offs__))
49
50/* Protect access to shared TITAN registers */
51extern spinlock_t titan_lock;
52extern int titan_irqflags;
53#define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags)
54#define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags)
55
56#endif /* !defined(_ASM_RM9K_OCD_H) */
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index ad374bd3f130..70636b41832c 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -172,7 +172,8 @@
172 * On the RM9000 there is a problem which makes the CreateDirtyExclusive 172 * On the RM9000 there is a problem which makes the CreateDirtyExclusive
173 * cache operation unusable on SMP systems. 173 * cache operation unusable on SMP systems.
174 */ 174 */
175#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) 175#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \
176 defined(CONFIG_BASLER_EXCITE)
176#define RM9000_CDEX_SMP_WAR 1 177#define RM9000_CDEX_SMP_WAR 1
177#endif 178#endif
178 179
@@ -182,7 +183,7 @@
182 * being fetched may case spurious exceptions. 183 * being fetched may case spurious exceptions.
183 */ 184 */
184#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ 185#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
185 defined(CONFIG_PMC_YOSEMITE) 186 defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
186#define ICACHE_REFILLS_WORKAROUND_WAR 1 187#define ICACHE_REFILLS_WORKAROUND_WAR 1
187#endif 188#endif
188 189
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 09:45:17 -0500