diff options
-rw-r--r-- | drivers/gpu/drm/radeon/cik.c | 71 |
1 files changed, 1 insertions, 70 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 03e160b39aa0..dd8f50f9962f 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c | |||
@@ -7297,8 +7297,7 @@ static int cik_irq_init(struct radeon_device *rdev) | |||
7297 | int cik_irq_set(struct radeon_device *rdev) | 7297 | int cik_irq_set(struct radeon_device *rdev) |
7298 | { | 7298 | { |
7299 | u32 cp_int_cntl; | 7299 | u32 cp_int_cntl; |
7300 | u32 cp_m1p0, cp_m1p1, cp_m1p2, cp_m1p3; | 7300 | u32 cp_m1p0; |
7301 | u32 cp_m2p0, cp_m2p1, cp_m2p2, cp_m2p3; | ||
7302 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; | 7301 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; |
7303 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; | 7302 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; |
7304 | u32 grbm_int_cntl = 0; | 7303 | u32 grbm_int_cntl = 0; |
@@ -7332,13 +7331,6 @@ int cik_irq_set(struct radeon_device *rdev) | |||
7332 | dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; | 7331 | dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; |
7333 | 7332 | ||
7334 | cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; | 7333 | cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; |
7335 | cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; | ||
7336 | cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; | ||
7337 | cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; | ||
7338 | cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; | ||
7339 | cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; | ||
7340 | cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; | ||
7341 | cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; | ||
7342 | 7334 | ||
7343 | if (rdev->flags & RADEON_IS_IGP) | 7335 | if (rdev->flags & RADEON_IS_IGP) |
7344 | thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL) & | 7336 | thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL) & |
@@ -7360,33 +7352,6 @@ int cik_irq_set(struct radeon_device *rdev) | |||
7360 | case 0: | 7352 | case 0: |
7361 | cp_m1p0 |= TIME_STAMP_INT_ENABLE; | 7353 | cp_m1p0 |= TIME_STAMP_INT_ENABLE; |
7362 | break; | 7354 | break; |
7363 | case 1: | ||
7364 | cp_m1p1 |= TIME_STAMP_INT_ENABLE; | ||
7365 | break; | ||
7366 | case 2: | ||
7367 | cp_m1p2 |= TIME_STAMP_INT_ENABLE; | ||
7368 | break; | ||
7369 | case 3: | ||
7370 | cp_m1p2 |= TIME_STAMP_INT_ENABLE; | ||
7371 | break; | ||
7372 | default: | ||
7373 | DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe); | ||
7374 | break; | ||
7375 | } | ||
7376 | } else if (ring->me == 2) { | ||
7377 | switch (ring->pipe) { | ||
7378 | case 0: | ||
7379 | cp_m2p0 |= TIME_STAMP_INT_ENABLE; | ||
7380 | break; | ||
7381 | case 1: | ||
7382 | cp_m2p1 |= TIME_STAMP_INT_ENABLE; | ||
7383 | break; | ||
7384 | case 2: | ||
7385 | cp_m2p2 |= TIME_STAMP_INT_ENABLE; | ||
7386 | break; | ||
7387 | case 3: | ||
7388 | cp_m2p2 |= TIME_STAMP_INT_ENABLE; | ||
7389 | break; | ||
7390 | default: | 7355 | default: |
7391 | DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe); | 7356 | DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe); |
7392 | break; | 7357 | break; |
@@ -7403,33 +7368,6 @@ int cik_irq_set(struct radeon_device *rdev) | |||
7403 | case 0: | 7368 | case 0: |
7404 | cp_m1p0 |= TIME_STAMP_INT_ENABLE; | 7369 | cp_m1p0 |= TIME_STAMP_INT_ENABLE; |
7405 | break; | 7370 | break; |
7406 | case 1: | ||
7407 | cp_m1p1 |= TIME_STAMP_INT_ENABLE; | ||
7408 | break; | ||
7409 | case 2: | ||
7410 | cp_m1p2 |= TIME_STAMP_INT_ENABLE; | ||
7411 | break; | ||
7412 | case 3: | ||
7413 | cp_m1p2 |= TIME_STAMP_INT_ENABLE; | ||
7414 | break; | ||
7415 | default: | ||
7416 | DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe); | ||
7417 | break; | ||
7418 | } | ||
7419 | } else if (ring->me == 2) { | ||
7420 | switch (ring->pipe) { | ||
7421 | case 0: | ||
7422 | cp_m2p0 |= TIME_STAMP_INT_ENABLE; | ||
7423 | break; | ||
7424 | case 1: | ||
7425 | cp_m2p1 |= TIME_STAMP_INT_ENABLE; | ||
7426 | break; | ||
7427 | case 2: | ||
7428 | cp_m2p2 |= TIME_STAMP_INT_ENABLE; | ||
7429 | break; | ||
7430 | case 3: | ||
7431 | cp_m2p2 |= TIME_STAMP_INT_ENABLE; | ||
7432 | break; | ||
7433 | default: | 7371 | default: |
7434 | DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe); | 7372 | DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe); |
7435 | break; | 7373 | break; |
@@ -7518,13 +7456,6 @@ int cik_irq_set(struct radeon_device *rdev) | |||
7518 | WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1); | 7456 | WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1); |
7519 | 7457 | ||
7520 | WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); | 7458 | WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); |
7521 | WREG32(CP_ME1_PIPE1_INT_CNTL, cp_m1p1); | ||
7522 | WREG32(CP_ME1_PIPE2_INT_CNTL, cp_m1p2); | ||
7523 | WREG32(CP_ME1_PIPE3_INT_CNTL, cp_m1p3); | ||
7524 | WREG32(CP_ME2_PIPE0_INT_CNTL, cp_m2p0); | ||
7525 | WREG32(CP_ME2_PIPE1_INT_CNTL, cp_m2p1); | ||
7526 | WREG32(CP_ME2_PIPE2_INT_CNTL, cp_m2p2); | ||
7527 | WREG32(CP_ME2_PIPE3_INT_CNTL, cp_m2p3); | ||
7528 | 7459 | ||
7529 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); | 7460 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
7530 | 7461 | ||