drm/radeon/cik: Don't touch int of pipes 1-7

amdkfd should set interrupts for pipes 1-7.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>

1 files changed, 1 insertions, 70 deletions

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 03e160b39aa0..dd8f50f9962f 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -7297,8 +7297,7 @@ static int cik_irq_init(struct radeon_device *rdev)
 int cik_irq_set(struct radeon_device *rdev)
 {
         u32 cp_int_cntl;
-        u32 cp_m1p0, cp_m1p1, cp_m1p2, cp_m1p3;
-        u32 cp_m2p0, cp_m2p1, cp_m2p2, cp_m2p3;
+        u32 cp_m1p0;
         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
         u32 grbm_int_cntl = 0;
@@ -7332,13 +7331,6 @@ int cik_irq_set(struct radeon_device *rdev)
         dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
 
         cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
-        cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
-        cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
-        cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
-        cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
-        cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
-        cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
-        cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
 
         if (rdev->flags & RADEON_IS_IGP)
                 thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL) &
@@ -7360,33 +7352,6 @@ int cik_irq_set(struct radeon_device *rdev)
                         case 0:
                                 cp_m1p0 |= TIME_STAMP_INT_ENABLE;
                                 break;
-                        case 1:
-                                cp_m1p1 |= TIME_STAMP_INT_ENABLE;
-                                break;
-                        case 2:
-                                cp_m1p2 |= TIME_STAMP_INT_ENABLE;
-                                break;
-                        case 3:
-                                cp_m1p2 |= TIME_STAMP_INT_ENABLE;
-                                break;
-                        default:
-                                DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);
-                                break;
-                        }
-                } else if (ring->me == 2) {
-                        switch (ring->pipe) {
-                        case 0:
-                                cp_m2p0 |= TIME_STAMP_INT_ENABLE;
-                                break;
-                        case 1:
-                                cp_m2p1 |= TIME_STAMP_INT_ENABLE;
-                                break;
-                        case 2:
-                                cp_m2p2 |= TIME_STAMP_INT_ENABLE;
-                                break;
-                        case 3:
-                                cp_m2p2 |= TIME_STAMP_INT_ENABLE;
-                                break;
                         default:
                                 DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);
                                 break;
@@ -7403,33 +7368,6 @@ int cik_irq_set(struct radeon_device *rdev)
                         case 0:
                                 cp_m1p0 |= TIME_STAMP_INT_ENABLE;
                                 break;
-                        case 1:
-                                cp_m1p1 |= TIME_STAMP_INT_ENABLE;
-                                break;
-                        case 2:
-                                cp_m1p2 |= TIME_STAMP_INT_ENABLE;
-                                break;
-                        case 3:
-                                cp_m1p2 |= TIME_STAMP_INT_ENABLE;
-                                break;
-                        default:
-                                DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);
-                                break;
-                        }
-                } else if (ring->me == 2) {
-                        switch (ring->pipe) {
-                        case 0:
-                                cp_m2p0 |= TIME_STAMP_INT_ENABLE;
-                                break;
-                        case 1:
-                                cp_m2p1 |= TIME_STAMP_INT_ENABLE;
-                                break;
-                        case 2:
-                                cp_m2p2 |= TIME_STAMP_INT_ENABLE;
-                                break;
-                        case 3:
-                                cp_m2p2 |= TIME_STAMP_INT_ENABLE;
-                                break;
                         default:
                                 DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);
                                 break;
@@ -7518,13 +7456,6 @@ int cik_irq_set(struct radeon_device *rdev)
         WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);
 
         WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0);
-        WREG32(CP_ME1_PIPE1_INT_CNTL, cp_m1p1);
-        WREG32(CP_ME1_PIPE2_INT_CNTL, cp_m1p2);
-        WREG32(CP_ME1_PIPE3_INT_CNTL, cp_m1p3);
-        WREG32(CP_ME2_PIPE0_INT_CNTL, cp_m2p0);
-        WREG32(CP_ME2_PIPE1_INT_CNTL, cp_m2p1);
-        WREG32(CP_ME2_PIPE2_INT_CNTL, cp_m2p2);
-        WREG32(CP_ME2_PIPE3_INT_CNTL, cp_m2p3);
 
         WREG32(GRBM_INT_CNTL, grbm_int_cntl);