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-rw-r--r--drivers/gpu/drm/msm/dsi/dsi.xml.h502
-rw-r--r--drivers/gpu/drm/msm/dsi/mmss_cc.xml.h114
-rw-r--r--drivers/gpu/drm/msm/dsi/sfpb.xml.h48
-rw-r--r--drivers/gpu/drm/msm/hdmi/hdmi.xml.h508
-rw-r--r--drivers/gpu/drm/msm/hdmi/qfprom.xml.h50
-rw-r--r--drivers/gpu/drm/msm/mdp4/mdp4.xml.h1061
6 files changed, 2283 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
new file mode 100644
index 000000000000..6f8396be431d
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -0,0 +1,502 @@
1#ifndef DSI_XML
2#define DSI_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://0x04.net/cgit/index.cgi/rules-ng-ng
8git clone git://0x04.net/rules-ng-ng
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-08-16 22:16:36)
14- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
15- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
17- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
18- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15)
19
20Copyright (C) 2013 by the following authors:
21- Rob Clark <robdclark@gmail.com> (robclark)
22
23Permission is hereby granted, free of charge, to any person obtaining
24a copy of this software and associated documentation files (the
25"Software"), to deal in the Software without restriction, including
26without limitation the rights to use, copy, modify, merge, publish,
27distribute, sublicense, and/or sell copies of the Software, and to
28permit persons to whom the Software is furnished to do so, subject to
29the following conditions:
30
31The above copyright notice and this permission notice (including the
32next paragraph) shall be included in all copies or substantial
33portions of the Software.
34
35THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
38IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
39LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
40OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
41WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
42*/
43
44
45enum dsi_traffic_mode {
46 NON_BURST_SYNCH_PULSE = 0,
47 NON_BURST_SYNCH_EVENT = 1,
48 BURST_MODE = 2,
49};
50
51enum dsi_dst_format {
52 DST_FORMAT_RGB565 = 0,
53 DST_FORMAT_RGB666 = 1,
54 DST_FORMAT_RGB666_LOOSE = 2,
55 DST_FORMAT_RGB888 = 3,
56};
57
58enum dsi_rgb_swap {
59 SWAP_RGB = 0,
60 SWAP_RBG = 1,
61 SWAP_BGR = 2,
62 SWAP_BRG = 3,
63 SWAP_GRB = 4,
64 SWAP_GBR = 5,
65};
66
67enum dsi_cmd_trigger {
68 TRIGGER_NONE = 0,
69 TRIGGER_TE = 2,
70 TRIGGER_SW = 4,
71 TRIGGER_SW_SEOF = 5,
72 TRIGGER_SW_TE = 6,
73};
74
75#define DSI_IRQ_CMD_DMA_DONE 0x00000001
76#define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
77#define DSI_IRQ_CMD_MDP_DONE 0x00000100
78#define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
79#define DSI_IRQ_VIDEO_DONE 0x00010000
80#define DSI_IRQ_MASK_VIDEO_DONE 0x00020000
81#define DSI_IRQ_ERROR 0x01000000
82#define DSI_IRQ_MASK_ERROR 0x02000000
83#define REG_DSI_CTRL 0x00000000
84#define DSI_CTRL_ENABLE 0x00000001
85#define DSI_CTRL_VID_MODE_EN 0x00000002
86#define DSI_CTRL_CMD_MODE_EN 0x00000004
87#define DSI_CTRL_LANE0 0x00000010
88#define DSI_CTRL_LANE1 0x00000020
89#define DSI_CTRL_LANE2 0x00000040
90#define DSI_CTRL_LANE3 0x00000080
91#define DSI_CTRL_CLK_EN 0x00000100
92#define DSI_CTRL_ECC_CHECK 0x00100000
93#define DSI_CTRL_CRC_CHECK 0x01000000
94
95#define REG_DSI_STATUS0 0x00000004
96#define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002
97#define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008
98#define DSI_STATUS0_DSI_BUSY 0x00000010
99
100#define REG_DSI_FIFO_STATUS 0x00000008
101
102#define REG_DSI_VID_CFG0 0x0000000c
103#define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003
104#define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0
105static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val)
106{
107 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK;
108}
109#define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030
110#define DSI_VID_CFG0_DST_FORMAT__SHIFT 4
111static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_dst_format val)
112{
113 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK;
114}
115#define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300
116#define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8
117static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val)
118{
119 return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK;
120}
121#define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000
122#define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000
123#define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000
124#define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000
125#define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000
126#define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000
127
128#define REG_DSI_VID_CFG1 0x0000001c
129#define DSI_VID_CFG1_R_SEL 0x00000010
130#define DSI_VID_CFG1_G_SEL 0x00000100
131#define DSI_VID_CFG1_B_SEL 0x00001000
132#define DSI_VID_CFG1_RGB_SWAP__MASK 0x00070000
133#define DSI_VID_CFG1_RGB_SWAP__SHIFT 16
134static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val)
135{
136 return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK;
137}
138#define DSI_VID_CFG1_INTERLEAVE_MAX__MASK 0x00f00000
139#define DSI_VID_CFG1_INTERLEAVE_MAX__SHIFT 20
140static inline uint32_t DSI_VID_CFG1_INTERLEAVE_MAX(uint32_t val)
141{
142 return ((val) << DSI_VID_CFG1_INTERLEAVE_MAX__SHIFT) & DSI_VID_CFG1_INTERLEAVE_MAX__MASK;
143}
144
145#define REG_DSI_ACTIVE_H 0x00000020
146#define DSI_ACTIVE_H_START__MASK 0x00000fff
147#define DSI_ACTIVE_H_START__SHIFT 0
148static inline uint32_t DSI_ACTIVE_H_START(uint32_t val)
149{
150 return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK;
151}
152#define DSI_ACTIVE_H_END__MASK 0x0fff0000
153#define DSI_ACTIVE_H_END__SHIFT 16
154static inline uint32_t DSI_ACTIVE_H_END(uint32_t val)
155{
156 return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK;
157}
158
159#define REG_DSI_ACTIVE_V 0x00000024
160#define DSI_ACTIVE_V_START__MASK 0x00000fff
161#define DSI_ACTIVE_V_START__SHIFT 0
162static inline uint32_t DSI_ACTIVE_V_START(uint32_t val)
163{
164 return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK;
165}
166#define DSI_ACTIVE_V_END__MASK 0x0fff0000
167#define DSI_ACTIVE_V_END__SHIFT 16
168static inline uint32_t DSI_ACTIVE_V_END(uint32_t val)
169{
170 return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK;
171}
172
173#define REG_DSI_TOTAL 0x00000028
174#define DSI_TOTAL_H_TOTAL__MASK 0x00000fff
175#define DSI_TOTAL_H_TOTAL__SHIFT 0
176static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val)
177{
178 return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK;
179}
180#define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000