drm/msm: add register definitions

Generated from rnndb files in:

https://github.com/freedreno/envytools

Keep this split out as a separate commit to make it easier to review the
actual driver.

Signed-off-by: Rob Clark <robdclark@gmail.com>

6 files changed, 2283 insertions, 0 deletions

diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
new file mode 100644
index 000000000000..6f8396be431d
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -0,0 +1,502 @@
+#ifndef DSI_XML
+#define DSI_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    595 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml           (  19332 bytes, from 2013-08-16 22:16:36)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1544 bytes, from 2013-08-16 19:17:05)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  19288 bytes, from 2013-08-11 18:14:15)
+
+Copyright (C) 2013 by the following authors:
+- Rob Clark <robdclark@gmail.com> (robclark)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+enum dsi_traffic_mode {
+        NON_BURST_SYNCH_PULSE = 0,
+        NON_BURST_SYNCH_EVENT = 1,
+        BURST_MODE = 2,
+};
+
+enum dsi_dst_format {
+        DST_FORMAT_RGB565 = 0,
+        DST_FORMAT_RGB666 = 1,
+        DST_FORMAT_RGB666_LOOSE = 2,
+        DST_FORMAT_RGB888 = 3,
+};
+
+enum dsi_rgb_swap {
+        SWAP_RGB = 0,
+        SWAP_RBG = 1,
+        SWAP_BGR = 2,
+        SWAP_BRG = 3,
+        SWAP_GRB = 4,
+        SWAP_GBR = 5,
+};
+
+enum dsi_cmd_trigger {
+        TRIGGER_NONE = 0,
+        TRIGGER_TE = 2,
+        TRIGGER_SW = 4,
+        TRIGGER_SW_SEOF = 5,
+        TRIGGER_SW_TE = 6,
+};
+
+#define DSI_IRQ_CMD_DMA_DONE                                    0x00000001
+#define DSI_IRQ_MASK_CMD_DMA_DONE                               0x00000002
+#define DSI_IRQ_CMD_MDP_DONE                                    0x00000100
+#define DSI_IRQ_MASK_CMD_MDP_DONE                               0x00000200
+#define DSI_IRQ_VIDEO_DONE                                      0x00010000
+#define DSI_IRQ_MASK_VIDEO_DONE                                 0x00020000
+#define DSI_IRQ_ERROR                                           0x01000000
+#define DSI_IRQ_MASK_ERROR                                      0x02000000
+#define REG_DSI_CTRL                                            0x00000000
+#define DSI_CTRL_ENABLE                                         0x00000001
+#define DSI_CTRL_VID_MODE_EN                                    0x00000002
+#define DSI_CTRL_CMD_MODE_EN                                    0x00000004
+#define DSI_CTRL_LANE0                                          0x00000010
+#define DSI_CTRL_LANE1                                          0x00000020
+#define DSI_CTRL_LANE2                                          0x00000040
+#define DSI_CTRL_LANE3                                          0x00000080
+#define DSI_CTRL_CLK_EN                                         0x00000100
+#define DSI_CTRL_ECC_CHECK                                      0x00100000
+#define DSI_CTRL_CRC_CHECK                                      0x01000000
+
+#define REG_DSI_STATUS0                                         0x00000004
+#define DSI_STATUS0_CMD_MODE_DMA_BUSY                           0x00000002
+#define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY                      0x00000008
+#define DSI_STATUS0_DSI_BUSY                                    0x00000010
+
+#define REG_DSI_FIFO_STATUS                                     0x00000008
+
+#define REG_DSI_VID_CFG0                                        0x0000000c
+#define DSI_VID_CFG0_VIRT_CHANNEL__MASK                         0x00000003
+#define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT                        0
+static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val)
+{
+        return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK;
+}
+#define DSI_VID_CFG0_DST_FORMAT__MASK                           0x00000030
+#define DSI_VID_CFG0_DST_FORMAT__SHIFT                          4
+static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_dst_format val)
+{
+        return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK;
+}
+#define DSI_VID_CFG0_TRAFFIC_MODE__MASK                         0x00000300
+#define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT                        8
+static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val)
+{
+        return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK;
+}
+#define DSI_VID_CFG0_BLLP_POWER_STOP                            0x00001000
+#define DSI_VID_CFG0_EOF_BLLP_POWER_STOP                        0x00008000
+#define DSI_VID_CFG0_HSA_POWER_STOP                             0x00010000
+#define DSI_VID_CFG0_HBP_POWER_STOP                             0x00100000
+#define DSI_VID_CFG0_HFP_POWER_STOP                             0x01000000
+#define DSI_VID_CFG0_PULSE_MODE_HSA_HE                          0x10000000
+
+#define REG_DSI_VID_CFG1                                        0x0000001c
+#define DSI_VID_CFG1_R_SEL                                      0x00000010
+#define DSI_VID_CFG1_G_SEL                                      0x00000100
+#define DSI_VID_CFG1_B_SEL                                      0x00001000
+#define DSI_VID_CFG1_RGB_SWAP__MASK                             0x00070000
+#define DSI_VID_CFG1_RGB_SWAP__SHIFT                            16
+static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val)
+{
+        return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK;
+}
+#define DSI_VID_CFG1_INTERLEAVE_MAX__MASK                       0x00f00000
+#define DSI_VID_CFG1_INTERLEAVE_MAX__SHIFT                      20
+static inline uint32_t DSI_VID_CFG1_INTERLEAVE_MAX(uint32_t val)
+{
+        return ((val) << DSI_VID_CFG1_INTERLEAVE_MAX__SHIFT) & DSI_VID_CFG1_INTERLEAVE_MAX__MASK;
+}
+
+#define REG_DSI_ACTIVE_H                                        0x00000020
+#define DSI_ACTIVE_H_START__MASK                                0x00000fff
+#define DSI_ACTIVE_H_START__SHIFT                               0
+static inline uint32_t DSI_ACTIVE_H_START(uint32_t val)
+{
+        return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK;
+}
+#define DSI_ACTIVE_H_END__MASK                                  0x0fff0000
+#define DSI_ACTIVE_H_END__SHIFT                                 16
+static inline uint32_t DSI_ACTIVE_H_END(uint32_t val)
+{
+        return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK;
+}
+
+#define REG_DSI_ACTIVE_V                                        0x00000024
+#define DSI_ACTIVE_V_START__MASK                                0x00000fff
+#define DSI_ACTIVE_V_START__SHIFT                               0
+static inline uint32_t DSI_ACTIVE_V_START(uint32_t val)
+{
+        return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK;
+}
+#define DSI_ACTIVE_V_END__MASK                                  0x0fff0000
+#define DSI_ACTIVE_V_END__SHIFT                                 16
+static inline uint32_t DSI_ACTIVE_V_END(uint32_t val)
+{
+        return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK;
+}
+
+#define REG_DSI_TOTAL                                           0x00000028
+#define DSI_TOTAL_H_TOTAL__MASK                                 0x00000fff
+#define DSI_TOTAL_H_TOTAL__SHIFT                                0
+static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val)
+{
+        return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK;
+}
+#define DSI_TOTAL_V_TOTAL__MASK                                 0x0fff0000
+#define DSI_TOTAL_V_TOTAL__SHIFT                                16
+static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val)
+{
+        return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK;
+}
+
+#define REG_DSI_ACTIVE_HSYNC                                    0x0000002c
+#define DSI_ACTIVE_HSYNC_START__MASK                            0x00000fff
+#define DSI_ACTIVE_HSYNC_START__SHIFT                           0
+static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val)
+{
+        return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK;
+}
+#define DSI_ACTIVE_HSYNC_END__MASK                              0x0fff0000
+#define DSI_ACTIVE_HSYNC_END__SHIFT                             16
+static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val)
+{
+        return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK;
+}
+
+#define REG_DSI_ACTIVE_VSYNC                                    0x00000034
+#define DSI_ACTIVE_VSYNC_START__MASK                            0x00000fff
+#define DSI_ACTIVE_VSYNC_START__SHIFT                           0
+static inline uint32_t DSI_ACTIVE_VSYNC_START(uint32_t val)
+{
+        return ((val) << DSI_ACTIVE_VSYNC_START__SHIFT) & DSI_ACTIVE_VSYNC_START__MASK;
+}
+#define DSI_ACTIVE_VSYNC_END__MASK                              0x0fff0000
+#define DSI_ACTIVE_VSYNC_END__SHIFT                             16
+static inline uint32_t DSI_ACTIVE_VSYNC_END(uint32_t val)
+{
+        return ((val) << DSI_ACTIVE_VSYNC_END__SHIFT) & DSI_ACTIVE_VSYNC_END__MASK;
+}
+
+#define REG_DSI_CMD_DMA_CTRL                                    0x00000038
+#define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER                      0x10000000
+#define DSI_CMD_DMA_CTRL_LOW_POWER                              0x04000000
+
+#define REG_DSI_CMD_CFG0                                        0x0000003c
+
+#define REG_DSI_CMD_CFG1                                        0x00000040
+
+#define REG_DSI_DMA_BASE                                        0x00000044
+
+#define REG_DSI_DMA_LEN                                         0x00000048
+
+#define REG_DSI_ACK_ERR_STATUS                                  0x00000064
+
+static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; }
+
+static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; }
+
+#define REG_DSI_TRIG_CTRL                                       0x00000080
+#define DSI_TRIG_CTRL_DMA_TRIGGER__MASK                         0x0000000f
+#define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT                        0
+static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val)
+{
+        return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK;
+}
+#define DSI_TRIG_CTRL_MDP_TRIGGER__MASK                         0x000000f0
+#define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT                        4
+static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val)
+{
+        return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK;
+}
+#define DSI_TRIG_CTRL_STREAM                                    0x00000100
+#define DSI_TRIG_CTRL_TE                                        0x80000000
+
+#define REG_DSI_TRIG_DMA                                        0x0000008c
+
+#define REG_DSI_DLN0_PHY_ERR                                    0x000000b0
+
+#define REG_DSI_TIMEOUT_STATUS                                  0x000000bc
+
+#define REG_DSI_CLKOUT_TIMING_CTRL                              0x000000c0
+#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK                  0x0000003f
+#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT                 0
+static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val)
+{
+        return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK;
+}
+#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK                 0x00003f00
+#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT                8
+static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
+{
+        return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK;
+}
+
+#define REG_DSI_EOT_PACKET_CTRL                                 0x000000c8
+#define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND                       0x00000001
+#define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE                       0x00000010
+
+#define REG_DSI_LANE_SWAP_CTRL                                  0x000000ac
+
+#define REG_DSI_ERR_INT_MASK0                                   0x00000108
+
+#define REG_DSI_INTR_CTRL                                       0x0000010c
+
+#define REG_DSI_RESET                                           0x00000114
+
+#define REG_DSI_CLK_CTRL                                        0x00000118
+
+#define REG_DSI_PHY_RESET                                       0x00000128
+
+#define REG_DSI_PHY_PLL_CTRL_0                                  0x00000200
+#define DSI_PHY_PLL_CTRL_0_ENABLE                               0x00000001
+
+#define REG_DSI_PHY_PLL_CTRL_1                                  0x00000204
+
+#define REG_DSI_PHY_PLL_CTRL_2                                  0x00000208
+
+#define REG_DSI_PHY_PLL_CTRL_3                                  0x0000020c
+
+#define REG_DSI_PHY_PLL_CTRL_4                                  0x00000210
+
+#define REG_DSI_PHY_PLL_CTRL_5                                  0x00000214
+
+#define REG_DSI_PHY_PLL_CTRL_6                                  0x00000218
+
+#define REG_DSI_PHY_PLL_CTRL_7                                  0x0000021c
+
+#define REG_DSI_PHY_PLL_CTRL_8                                  0x00000220
+
+#define REG_DSI_PHY_PLL_CTRL_9                                  0x00000224
+
+#define REG_DSI_PHY_PLL_CTRL_10                                 0x00000228
+
+#define REG_DSI_PHY_PLL_CTRL_11                                 0x0000022c
+
+#define REG_DSI_PHY_PLL_CTRL_12                                 0x00000230
+
+#define REG_DSI_PHY_PLL_CTRL_13                                 0x00000234
+
+#define REG_DSI_PHY_PLL_CTRL_14                                 0x00000238
+
+#define REG_DSI_PHY_PLL_CTRL_15                                 0x0000023c
+
+#define REG_DSI_PHY_PLL_CTRL_16                                 0x00000240
+
+#define REG_DSI_PHY_PLL_CTRL_17                                 0x00000244
+
+#define REG_DSI_PHY_PLL_CTRL_18                                 0x00000248
+
+#define REG_DSI_PHY_PLL_CTRL_19                                 0x0000024c
+
+#define REG_DSI_PHY_PLL_CTRL_20                                 0x00000250
+
+#define REG_DSI_PHY_PLL_STATUS                                  0x00000280
+#define DSI_PHY_PLL_STATUS_PLL_BUSY                             0x00000001
+
+#define REG_DSI_8x60_PHY_TPA_CTRL_1                             0x00000258
+
+#define REG_DSI_8x60_PHY_TPA_CTRL_2                             0x0000025c
+
+#define REG_DSI_8x60_PHY_TIMING_CTRL_0                          0x00000260
+
+#define REG_DSI_8x60_PHY_TIMING_CTRL_1                          0x00000264
+
+#define REG_DSI_8x60_PHY_TIMING_CTRL_2                          0x00000268
+
+#define REG_DSI_8x60_PHY_TIMING_CTRL_3                          0x0000026c
+
+#define REG_DSI_8x60_PHY_TIMING_CTRL_4                          0x00000270
+
+#define REG_DSI_8x60_PHY_TIMING_CTRL_5                          0x00000274
+
+#define REG_DSI_8x60_PHY_TIMING_CTRL_6                          0x00000278
+
+#define REG_DSI_8x60_PHY_TIMING_CTRL_7                          0x0000027c
+
+#define REG_DSI_8x60_PHY_TIMING_CTRL_8                          0x00000280
+
+#define REG_DSI_8x60_PHY_TIMING_CTRL_9                          0x00000284
+
+#define REG_DSI_8x60_PHY_TIMING_CTRL_10                         0x00000288
+
+#define REG_DSI_8x60_PHY_TIMING_CTRL_11                         0x0000028c
+
+#define REG_DSI_8x60_PHY_CTRL_0                                 0x00000290
+
+#define REG_DSI_8x60_PHY_CTRL_1                                 0x00000294
+
+#define REG_DSI_8x60_PHY_CTRL_2                                 0x00000298
+
+#define REG_DSI_8x60_PHY_CTRL_3                                 0x0000029c
+
+#define REG_DSI_8x60_PHY_STRENGTH_0                             0x000002a0
+
+#define REG_DSI_8x60_PHY_STRENGTH_1                             0x000002a4
+
+#define REG_DSI_8x60_PHY_STRENGTH_2                             0x000002a8
+
+#define REG_DSI_8x60_PHY_STRENGTH_3                             0x000002ac
+
+#define REG_DSI_8x60_PHY_REGULATOR_CTRL_0                       0x000002cc
+
+#define REG_DSI_8x60_PHY_REGULATOR_CTRL_1                       0x000002d0
+
+#define REG_DSI_8x60_PHY_REGULATOR_CTRL_2                       0x000002d4
+
+#define REG_DSI_8x60_PHY_REGULATOR_CTRL_3                       0x000002d8
+
+#define REG_DSI_8x60_PHY_REGULATOR_CTRL_4                       0x000002dc
+
+#define REG_DSI_8x60_PHY_CAL_HW_TRIGGER                         0x000000f0
+
+#define REG_DSI_8x60_PHY_CAL_CTRL                               0x000000f4
+
+#define REG_DSI_8x60_PHY_CAL_STATUS                             0x000000fc
+#define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY                        0x10000000
+
+static inline uint32_t REG_DSI_8960_LN(uint32_t i0) { return 0x00000300 + 0x40*i0; }
+
+static inline uint32_t REG_DSI_8960_LN_CFG_0(uint32_t i0) { return 0x00000300 + 0x40*i0; }
+
+static inline uint32_t REG_DSI_8960_LN_CFG_1(uint32_t i0) { return 0x00000304 + 0x40*i0; }
+
+static inline uint32_t REG_DSI_8960_LN_CFG_2(uint32_t i0) { return 0x00000308 + 0x40*i0; }
+
+static inline uint32_t REG_DSI_8960_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000030c + 0x40*i0; }
+
+static inline uint32_t REG_DSI_8960_LN_TEST_STR_0(uint32_t i0) { return 0x00000314 + 0x40*i0; }
+
+static inline uint32_t REG_DSI_8960_LN_TEST_STR_1(uint32_t i0) { return 0x00000318 + 0x40*i0; }
+
+#define REG_DSI_8960_PHY_LNCK_CFG_0                             0x00000400
+
+#define REG_DSI_8960_PHY_LNCK_CFG_1                             0x00000404
+
+#define REG_DSI_8960_PHY_LNCK_CFG_2                             0x00000408
+
+#define REG_DSI_8960_PHY_LNCK_TEST_DATAPATH                     0x0000040c
+
+#define REG_DSI_8960_PHY_LNCK_TEST_STR0                         0x00000414
+
+#define REG_DSI_8960_PHY_LNCK_TEST_STR1                         0x00000418
+
+#define REG_DSI_8960_PHY_TIMING_CTRL_0                          0x00000440
+
+#define REG_DSI_8960_PHY_TIMING_CTRL_1                          0x00000444
+
+#define REG_DSI_8960_PHY_TIMING_CTRL_2                          0x00000448
+
+#define REG_DSI_8960_PHY_TIMING_CTRL_3                          0x0000044c
+
+#define REG_DSI_8960_PHY_TIMING_CTRL_4                          0x00000450
+
+#define REG_DSI_8960_PHY_TIMING_CTRL_5                          0x00000454
+
+#define REG_DSI_8960_PHY_TIMING_CTRL_6                          0x00000458
+
+#define REG_DSI_8960_PHY_TIMING_CTRL_7                          0x0000045c
+
+#define REG_DSI_8960_PHY_TIMING_CTRL_8                          0x00000460
+
+#define REG_DSI_8960_PHY_TIMING_CTRL_9                          0x00000464
+
+#define REG_DSI_8960_PHY_TIMING_CTRL_10                         0x00000468
+
+#define REG_DSI_8960_PHY_TIMING_CTRL_11                         0x0000046c
+
+#define REG_DSI_8960_PHY_CTRL_0                                 0x00000470
+
+#define REG_DSI_8960_PHY_CTRL_1                                 0x00000474
+
+#define REG_DSI_8960_PHY_CTRL_2                                 0x00000478
+
+#define REG_DSI_8960_PHY_CTRL_3                                 0x0000047c
+
+#define REG_DSI_8960_PHY_STRENGTH_0                             0x00000480
+
+#define REG_DSI_8960_PHY_STRENGTH_1                             0x00000484
+
+#define REG_DSI_8960_PHY_STRENGTH_2                             0x00000488
+
+#define REG_DSI_8960_PHY_BIST_CTRL_0                            0x0000048c
+
+#define REG_DSI_8960_PHY_BIST_CTRL_1                            0x00000490
+
+#define REG_DSI_8960_PHY_BIST_CTRL_2                            0x00000494
+
+#define REG_DSI_8960_PHY_BIST_CTRL_3                            0x00000498
+
+#define REG_DSI_8960_PHY_BIST_CTRL_4                            0x0000049c
+
+#define REG_DSI_8960_PHY_LDO_CTRL                               0x000004b0
+
+#define REG_DSI_8960_PHY_REGULATOR_CTRL_0                       0x00000500
+
+#define REG_DSI_8960_PHY_REGULATOR_CTRL_1                       0x00000504
+
+#define REG_DSI_8960_PHY_REGULATOR_CTRL_2                       0x00000508
+
+#define REG_DSI_8960_PHY_REGULATOR_CTRL_3                       0x0000050c
+
+#define REG_DSI_8960_PHY_REGULATOR_CTRL_4                       0x00000510
+
+#define REG_DSI_8960_PHY_REGULATOR_CAL_PWR_CFG                  0x00000518
+
+#define REG_DSI_8960_PHY_CAL_HW_TRIGGER                         0x00000528
+
+#define REG_DSI_8960_PHY_CAL_SW_CFG_0                           0x0000052c
+
+#define REG_DSI_8960_PHY_CAL_SW_CFG_1                           0x00000530
+
+#define REG_DSI_8960_PHY_CAL_SW_CFG_2                           0x00000534
+
+#define REG_DSI_8960_PHY_CAL_HW_CFG_0                           0x00000538
+
+#define REG_DSI_8960_PHY_CAL_HW_CFG_1                           0x0000053c
+
+#define REG_DSI_8960_PHY_CAL_HW_CFG_2                           0x00000540
+
+#define REG_DSI_8960_PHY_CAL_HW_CFG_3                           0x00000544
+
+#define REG_DSI_8960_PHY_CAL_HW_CFG_4                           0x00000548
+
+#define REG_DSI_8960_PHY_CAL_STATUS                             0x00000550
+#define DSI_8960_PHY_CAL_STATUS_CAL_BUSY                        0x00000010
+
+
+#endif /* DSI_XML */
diff --git a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
new file mode 100644
index 000000000000..aefc1b8feae9
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
@@ -0,0 +1,114 @@
+#ifndef MMSS_CC_XML
+#define MMSS_CC_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    595 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml           (  19332 bytes, from 2013-08-16 22:16:36)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1544 bytes, from 2013-08-16 19:17:05)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  19288 bytes, from 2013-08-11 18:14:15)
+
+Copyright (C) 2013 by the following authors:
+- Rob Clark <robdclark@gmail.com> (robclark)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+enum mmss_cc_clk {
+        CLK = 0,
+        PCLK = 1,
+};
+
+#define REG_MMSS_CC_AHB                                         0x00000008
+
+static inline uint32_t __offset_CLK(enum mmss_cc_clk idx)
+{
+        switch (idx) {
+                case CLK: return 0x0000004c;
+                case PCLK: return 0x00000130;
+                default: return INVALID_IDX(idx);
+        }
+}
+static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); }
+
+static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); }
+#define MMSS_CC_CLK_CC_CLK_EN                                   0x00000001
+#define MMSS_CC_CLK_CC_ROOT_EN                                  0x00000004
+#define MMSS_CC_CLK_CC_MND_EN                                   0x00000020
+#define MMSS_CC_CLK_CC_MND_MODE__MASK                           0x000000c0
+#define MMSS_CC_CLK_CC_MND_MODE__SHIFT                          6
+static inline uint32_t MMSS_CC_CLK_CC_MND_MODE(uint32_t val)
+{
+        return ((val) << MMSS_CC_CLK_CC_MND_MODE__SHIFT) & MMSS_CC_CLK_CC_MND_MODE__MASK;
+}
+#define MMSS_CC_CLK_CC_PMXO_SEL__MASK                           0x00000300
+#define MMSS_CC_CLK_CC_PMXO_SEL__SHIFT                          8
+static inline uint32_t MMSS_CC_CLK_CC_PMXO_SEL(uint32_t val)
+{
+        return ((val) << MMSS_CC_CLK_CC_PMXO_SEL__SHIFT) & MMSS_CC_CLK_CC_PMXO_SEL__MASK;
+}
+
+static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); }
+#define MMSS_CC_CLK_MD_D__MASK                                  0x000000ff
+#define MMSS_CC_CLK_MD_D__SHIFT                                 0
+static inline uint32_t MMSS_CC_CLK_MD_D(uint32_t val)
+{
+        return ((val) << MMSS_CC_CLK_MD_D__SHIFT) & MMSS_CC_CLK_MD_D__MASK;
+}
+#define MMSS_CC_CLK_MD_M__MASK                                  0x0000ff00
+#define MMSS_CC_CLK_MD_M__SHIFT                                 8
+static inline uint32_t MMSS_CC_CLK_MD_M(uint32_t val)
+{
+        return ((val) << MMSS_CC_CLK_MD_M__SHIFT) & MMSS_CC_CLK_MD_M__MASK;
+}
+
+static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); }
+#define MMSS_CC_CLK_NS_SRC__MASK                                0x0000000f
+#define MMSS_CC_CLK_NS_SRC__SHIFT                               0
+static inline uint32_t MMSS_CC_CLK_NS_SRC(uint32_t val)
+{
+        return ((val) << MMSS_CC_CLK_NS_SRC__SHIFT) & MMSS_CC_CLK_NS_SRC__MASK;
+}
+#define MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK                       0x00fff000
+#define MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT                      12
+static inline uint32_t MMSS_CC_CLK_NS_PRE_DIV_FUNC(uint32_t val)
+{
+        return ((val) << MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT) & MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK;
+}
+#define MMSS_CC_CLK_NS_VAL__MASK                                0xff000000
+#define MMSS_CC_CLK_NS_VAL__SHIFT                               24
+static inline uint32_t MMSS_CC_CLK_NS_VAL(uint32_t val)
+{
+        return ((val) << MMSS_CC_CLK_NS_VAL__SHIFT) & MMSS_CC_CLK_NS_VAL__MASK;
+}
+
+
+#endif /* MMSS_CC_XML */
diff --git a/drivers/gpu/drm/msm/dsi/sfpb.xml.h b/drivers/gpu/drm/msm/dsi/sfpb.xml.h
new file mode 100644
index 000000000000..a225e8170b2a
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi/sfpb.xml.h
@@ -0,0 +1,48 @@
+#ifndef SFPB_XML
+#define SFPB_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    595 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml           (  19332 bytes, from 2013-08-16 22:16:36)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1544 bytes, from 2013-08-16 19:17:05)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  19288 bytes, from 2013-08-11 18:14:15)
+
+Copyright (C) 2013 by the following authors:
+- Rob Clark <robdclark@gmail.com> (robclark)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+#define REG_SFPB_CFG                                            0x00000058
+
+
+#endif /* SFPB_XML */
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
new file mode 100644
index 000000000000..f5fa4865e059
--- /dev/null
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
@@ -0,0 +1,508 @@
+#ifndef HDMI_XML
+#define HDMI_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    595 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml           (  19332 bytes, from 2013-08-16 22:16:36)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1544 bytes, from 2013-08-16 19:17:05)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  19288 bytes, from 2013-08-11 18:14:15)
+
+Copyright (C) 2013 by the following authors:
+- Rob Clark <robdclark@gmail.com> (robclark)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+enum hdmi_hdcp_key_state {
+        NO_KEYS = 0,
+        NOT_CHECKED = 1,
+        CHECKING = 2,
+        KEYS_VALID = 3,
+        AKSV_INVALID = 4,
+        CHECKSUM_MISMATCH = 5,
+};
+
+enum hdmi_ddc_read_write {
+        DDC_WRITE = 0,
+        DDC_READ = 1,
+};
+
+enum hdmi_acr_cts {
+        ACR_NONE = 0,
+        ACR_32 = 1,
+        ACR_44 = 2,
+        ACR_48 = 3,
+};
+
+#define REG_HDMI_CTRL                                           0x00000000
+#define HDMI_CTRL_ENABLE                                        0x00000001
+#define HDMI_CTRL_HDMI                                          0x00000002
+#define HDMI_CTRL_ENCRYPTED                                     0x00000004
+
+#define REG_HDMI_AUDIO_PKT_CTRL1                                0x00000020
+#define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND                  0x00000001
+
+#define REG_HDMI_ACR_PKT_CTRL                                   0x00000024
+#define HDMI_ACR_PKT_CTRL_CONT                                  0x00000001
+#define HDMI_ACR_PKT_CTRL_SEND                                  0x00000002
+#define HDMI_ACR_PKT_CTRL_SELECT__MASK                          0x00000030
+#define HDMI_ACR_PKT_CTRL_SELECT__SHIFT                         4
+static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val)
+{
+        return ((val) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT) & HDMI_ACR_PKT_CTRL_SELECT__MASK;
+}
+#define HDMI_ACR_PKT_CTRL_SOURCE                                0x00000100
+#define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK                    0x00070000
+#define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT                   16
+static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val)
+{
+        return ((val) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK;
+}
+#define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY                        0x80000000
+
+#define REG_HDMI_VBI_PKT_CTRL                                   0x00000028
+#define HDMI_VBI_PKT_CTRL_GC_ENABLE                             0x00000010
+#define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME                        0x00000020
+#define HDMI_VBI_PKT_CTRL_ISRC_SEND                             0x00000100
+#define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS                       0x00000200
+#define HDMI_VBI_PKT_CTRL_ACP_SEND                              0x00001000
+#define HDMI_VBI_PKT_CTRL_ACP_SRC_SW                            0x00002000
+
+#define REG_HDMI_INFOFRAME_CTRL0                                0x0000002c
+#define HDMI_INFOFRAME_CTRL0_AVI_SEND                           0x00000001
+#define HDMI_INFOFRAME_CTRL0_AVI_CONT                           0x00000002
+#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND                    0x00000010
+#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT                    0x00000020
+#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE                  0x00000040
+#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE                  0x00000080
+
+#define REG_HDMI_GEN_PKT_CTRL                                   0x00000034
+#define HDMI_GEN_PKT_CTRL_GENERIC0_SEND                         0x00000001
+#define HDMI_GEN_PKT_CTRL_GENERIC0_CONT                         0x00000002
+#define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK                 0x0000000c
+#define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT                2
+static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val)
+{
+        return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK;
+}
+#define HDMI_GEN_PKT_CTRL_GENERIC1_SEND                         0x00000010
+#define HDMI_GEN_PKT_CTRL_GENERIC1_CONT                         0x00000020
+#define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK                   0x003f0000
+#define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT                  16
+static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val)
+{
+        return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK;
+}
+#define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK                   0x3f000000
+#define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT                  24
+static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val)
+{
+        return ((val) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK;
+}
+
+#define REG_HDMI_GC                                             0x00000040
+#define HDMI_GC_MUTE                                            0x00000001
+
+#define REG_HDMI_AUDIO_PKT_CTRL2                                0x00000044
+#define HDMI_AUDIO_PKT_CTRL2_OVERRIDE                           0x00000001
+#define HDMI_AUDIO_PKT_CTRL2_LAYOUT                             0x00000002
+
+static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; }
+
+#define REG_HDMI_GENERIC0_HDR                                   0x00000084
+
+static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; }
+
+#define REG_HDMI_GENERIC1_HDR                                   0x000000a4
+
+static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; }
+
+static inline uint32_t REG_HDMI_ACR(uint32_t i0) { return 0x000000c4 + 0x8*i0; }
+
+static inline uint32_t REG_HDMI_ACR_0(uint32_t i0) { return 0x000000c4 + 0x8*i0; }
+#define HDMI_ACR_0_CTS__MASK                                    0xfffff000
+#define HDMI_ACR_0_CTS__SHIFT                                   12
+static inline uint32_t HDMI_ACR_0_CTS(uint32_t val)
+{
+        return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK;
+}
+
+static inline uint32_t REG_HDMI_ACR_1(uint32_t i0) { return 0x000000c8 + 0x8*i0; }
+#define HDMI_ACR_1_N__MASK                                      0xffffffff
+#define HDMI_ACR_1_N__SHIFT                                     0
+static inline uint32_t HDMI_ACR_1_N(uint32_t val)
+{
+        return ((val) << HDMI_ACR_1_N__SHIFT) & HDMI_ACR_1_N__MASK;
+}
+
+#define REG_HDMI_AUDIO_INFO0                                    0x000000e4
+#define HDMI_AUDIO_INFO0_CHECKSUM__MASK                         0x000000ff
+#define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT                        0
+static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val)
+{
+        return ((val) << HDMI_AUDIO_INFO0_CHECKSUM__SHIFT) & HDMI_AUDIO_INFO0_CHECKSUM__MASK;
+}
+#define HDMI_AUDIO_INFO0_CC__MASK                               0x00000700
+#define HDMI_AUDIO_INFO0_CC__SHIFT                              8
+static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val)
+{
+        return ((val) << HDMI_AUDIO_INFO0_CC__SHIFT) & HDMI_AUDIO_INFO0_CC__MASK;
+}
+
+#define REG_HDMI_AUDIO_INFO1                                    0x000000e8
+#define HDMI_AUDIO_INFO1_CA__MASK                               0x000000ff
+#define HDMI_AUDIO_INFO1_CA__SHIFT                              0
+static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val)
+{
+        return ((val) << HDMI_AUDIO_INFO1_CA__SHIFT) & HDMI_AUDIO_INFO1_CA__MASK;
+}
+#define HDMI_AUDIO_INFO1_LSV__MASK                              0x00007800
+#define HDMI_AUDIO_INFO1_LSV__SHIFT                             11
+static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val)
+{
+        return ((val) << HDMI_AUDIO_INFO1_LSV__SHIFT) & HDMI_AUDIO_INFO1_LSV__MASK;
+}
+#define HDMI_AUDIO_INFO1_DM_INH                                 0x00008000
+
+#define REG_HDMI_HDCP_CTRL                                      0x00000110
+#define HDMI_HDCP_CTRL_ENABLE                                   0x00000001
+#define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE                        0x00000100
+
+#define REG_HDMI_HDCP_INT_CTRL                                  0x00000118
+
+#define REG_HDMI_HDCP_LINK0_STATUS                              0x0000011c
+#define HDMI_HDCP_LINK0_STATUS_AN_0_READY                       0x00000100
+#define HDMI_HDCP_LINK0_STATUS_AN_1_READY                       0x00000200
+#define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK                  0x70000000
+#define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT                 28
+static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val)
+{
+        return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK;
+}
+
+#define REG_HDMI_HDCP_RESET                                     0x00000130
+#define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE                    0x00000001
+
+#define REG_HDMI_AUDIO_CFG                                      0x000001d0
+#define HDMI_AUDIO_CFG_ENGINE_ENABLE                            0x00000001
+#define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK                     0x000000f0
+#define HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT                    4
+static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val)
+{
+        return ((val) << HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT) & HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK;
+}
+
+#define REG_HDMI_USEC_REFTIMER                                  0x00000208
+
+#define REG_HDMI_DDC_CTRL                                       0x0000020c
+#define HDMI_DDC_CTRL_GO                                        0x00000001
+#define HDMI_DDC_CTRL_SOFT_RESET                                0x00000002
+#define HDMI_DDC_CTRL_SEND_RESET                                0x00000004
+#define HDMI_DDC_CTRL_SW_STATUS_RESET                           0x00000008
+#define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK                     0x00300000
+#define HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT                    20
+static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val)
+{
+        return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK;
+}
+
+#define REG_HDMI_DDC_INT_CTRL                                   0x00000214
+#define HDMI_DDC_INT_CTRL_SW_DONE_INT                           0x00000001
+#define HDMI_DDC_INT_CTRL_SW_DONE_ACK                           0x00000002
+#define HDMI_DDC_INT_CTRL_SW_DONE_MASK                          0x00000004
+
+#define REG_HDMI_DDC_SW_STATUS                                  0x00000218
+#define HDMI_DDC_SW_STATUS_NACK0                                0x00001000
+#define HDMI_DDC_SW_STATUS_NACK1                                0x00002000
+#define HDMI_DDC_SW_STATUS_NACK2                                0x00004000
+#define HDMI_DDC_SW_STATUS_NACK3                                0x00008000
+
+#define REG_HDMI_DDC_HW_STATUS                                  0x0000021c
+
+#define REG_HDMI_DDC_SPEED                                      0x00000220
+#define HDMI_DDC_SPEED_THRESHOLD__MASK                          0x00000003
+#define HDMI_DDC_SPEED_THRESHOLD__SHIFT                         0
+static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val)
+{
+        return ((val) << HDMI_DDC_SPEED_THRESHOLD__SHIFT) & HDMI_DDC_SPEED_THRESHOLD__MASK;
+}
+#define HDMI_DDC_SPEED_PRESCALE__MASK                           0xffff0000
+#define HDMI_DDC_SPEED_PRESCALE__SHIFT                          16
+static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val)
+{
+        return ((val) << HDMI_DDC_SPEED_PRESCALE__SHIFT) & HDMI_DDC_SPEED_PRESCALE__MASK;
+}
+
+#define REG_HDMI_DDC_SETUP                                      0x00000224
+#define HDMI_DDC_SETUP_TIMEOUT__MASK                            0xff000000
+#define HDMI_DDC_SETUP_TIMEOUT__SHIFT                           24
+static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val)
+{
+        return ((val) << HDMI_DDC_SETUP_TIMEOUT__SHIFT) & HDMI_DDC_SETUP_TIMEOUT__MASK;
+}
+
+static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; }
+
+static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; }
+#define HDMI_I2C_TRANSACTION_REG_RW__MASK                       0x00000001
+#define HDMI_I2C_TRANSACTION_REG_RW__SHIFT                      0
+static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val)
+{
+        return ((val) << HDMI_I2C_TRANSACTION_REG_RW__SHIFT) & HDMI_I2C_TRANSACTION_REG_RW__MASK;
+}
+#define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK                   0x00000100
+#define HDMI_I2C_TRANSACTION_REG_START                          0x00001000
+#define HDMI_I2C_TRANSACTION_REG_STOP                           0x00002000
+#define HDMI_I2C_TRANSACTION_REG_CNT__MASK                      0x00ff0000
+#define HDMI_I2C_TRANSACTION_REG_CNT__SHIFT                     16
+static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val)
+{
+        return ((val) << HDMI_I2C_TRANSACTION_REG_CNT__SHIFT) & HDMI_I2C_TRANSACTION_REG_CNT__MASK;
+}
+
+#define REG_HDMI_DDC_DATA                                       0x00000238
+#define HDMI_DDC_DATA_DATA_RW__MASK                             0x00000001
+#define HDMI_DDC_DATA_DATA_RW__SHIFT                            0
+static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val)
+{
+        return ((val) << HDMI_DDC_DATA_DATA_RW__SHIFT) & HDMI_DDC_DATA_DATA_RW__MASK;
+}
+#define HDMI_DDC_DATA_DATA__MASK                                0x0000ff00
+#define HDMI_DDC_DATA_DATA__SHIFT                               8
+static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val)
+{
+        return ((val) << HDMI_DDC_DATA_DATA__SHIFT) & HDMI_DDC_DATA_DATA__MASK;
+}
+#define HDMI_DDC_DATA_INDEX__MASK                               0x00ff0000
+#define HDMI_DDC_DATA_INDEX__SHIFT                              16
+static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val)
+{
+        return ((val) << HDMI_DDC_DATA_INDEX__SHIFT) & HDMI_DDC_DATA_INDEX__MASK;
+}
+#define HDMI_DDC_DATA_INDEX_WRITE                               0x80000000
+
+#define REG_HDMI_HPD_INT_STATUS                                 0x00000250
+#define HDMI_HPD_INT_STATUS_INT                                 0x00000001
+#define HDMI_HPD_INT_STATUS_CABLE_DETECTED                      0x00000002
+
+#define REG_HDMI_HPD_INT_CTRL                                   0x00000254
+#define HDMI_HPD_INT_CTRL_INT_ACK                               0x00000001
+#define HDMI_HPD_INT_CTRL_INT_CONNECT                           0x00000002
+#define HDMI_HPD_INT_CTRL_INT_EN                                0x00000004
+#define HDMI_HPD_INT_CTRL_RX_INT_ACK                            0x00000010
+#define HDMI_HPD_INT_CTRL_RX_INT_EN                             0x00000020
+#define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK                   0x00000200
+
+#define REG_HDMI_HPD_CTRL                                       0x00000258
+#define HDMI_HPD_CTRL_TIMEOUT__MASK                             0x00001fff
+#define HDMI_HPD_CTRL_TIMEOUT__SHIFT                            0
+static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val)
+{
+        return ((val) << HDMI_HPD_CTRL_TIMEOUT__SHIFT) & HDMI_HPD_CTRL_TIMEOUT__MASK;
+}
+#define HDMI_HPD_CTRL_ENABLE                                    0x10000000
+
+#define REG_HDMI_DDC_REF                                        0x0000027c
+#define HDMI_DDC_REF_REFTIMER_ENABLE                            0x00010000
+#define HDMI_DDC_REF_REFTIMER__MASK                             0x0000ffff
+#define HDMI_DDC_REF_REFTIMER__SHIFT                            0
+static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
+{
+        return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK;
+}
+
+#define REG_HDMI_ACTIVE_HSYNC                                   0x000002b4
+#define HDMI_ACTIVE_HSYNC_START__MASK                           0x00000fff
+#define HDMI_ACTIVE_HSYNC_START__SHIFT                          0
+static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val)
+{
+        return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK;
+}
+#define HDMI_ACTIVE_HSYNC_END__MASK                             0x0fff0000
+#define HDMI_ACTIVE_HSYNC_END__SHIFT                            16
+static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val)
+{
+        return ((val) << HDMI_ACTIVE_HSYNC_END__SHIFT) & HDMI_ACTIVE_HSYNC_END__MASK;
+}
+
+#define REG_HDMI_ACTIVE_VSYNC                                   0x000002b8
+#define HDMI_ACTIVE_VSYNC_START__MASK                           0x00000fff
+#define HDMI_ACTIVE_VSYNC_START__SHIFT                          0
+static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val)
+{
+        return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK;
+}
+#define HDMI_ACTIVE_VSYNC_END__MASK                             0x0fff0000
+#define HDMI_ACTIVE_VSYNC_END__SHIFT                            16
+static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val)
+{
+        return ((val) << HDMI_ACTIVE_VSYNC_END__SHIFT) & HDMI_ACTIVE_VSYNC_END__MASK;
+}
+
+#define REG_HDMI_VSYNC_ACTIVE_F2                                0x000002bc
+#define HDMI_VSYNC_ACTIVE_F2_START__MASK                        0x00000fff
+#define HDMI_VSYNC_ACTIVE_F2_START__SHIFT                       0
+static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val)
+{
+        return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK;
+}
+#define HDMI_VSYNC_ACTIVE_F2_END__MASK                          0x0fff0000
+#define HDMI_VSYNC_ACTIVE_F2_END__SHIFT                         16
+static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)
+{
+        return ((val) << HDMI_VSYNC_ACTIVE_F2_END__SHIFT) & HDMI_VSYNC_ACTIVE_F2_END__MASK;
+}
+
+#define REG_HDMI_TOTAL                                          0x000002c0
+#define HDMI_TOTAL_H_TOTAL__MASK                                0x00000fff
+#define HDMI_TOTAL_H_TOTAL__SHIFT                               0
+static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val)
+{
+        return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK;
+}
+#define HDMI_TOTAL_V_TOTAL__MASK                                0x0fff0000
+#define HDMI_TOTAL_V_TOTAL__SHIFT                               16
+static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val)
+{
+        return ((val) << HDMI_TOTAL_V_TOTAL__SHIFT) & HDMI_TOTAL_V_TOTAL__MASK;
+}
+
+#define REG_HDMI_VSYNC_TOTAL_F2                                 0x000002c4
+#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK                       0x00000fff
+#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT                      0
+static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
+{
+        return ((val) << HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT) & HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK;
+}
+
+#define REG_HDMI_FRAME_CTRL                                     0x000002c8
+#define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR                         0x00001000
+#define HDMI_FRAME_CTRL_VSYNC_LOW                               0x10000000
+#define HDMI_FRAME_CTRL_HSYNC_LOW                               0x20000000
+#define HDMI_FRAME_CTRL_INTERLACED_EN                           0x80000000
+
+#define REG_HDMI_PHY_CTRL                                       0x000002d4
+#define HDMI_PHY_CTRL_SW_RESET_PLL                              0x00000001
+#define HDMI_PHY_CTRL_SW_RESET_PLL_LOW                          0x00000002
+#define HDMI_PHY_CTRL_SW_RESET                                  0x00000004
+#define HDMI_PHY_CTRL_SW_RESET_LOW                              0x00000008
+
+#define REG_HDMI_AUD_INT                                        0x000002cc
+#define HDMI_AUD_INT_AUD_FIFO_URUN_INT                          0x00000001
+#define HDMI_AUD_INT_AUD_FIFO_URAN_MASK                         0x00000002
+#define HDMI_AUD_INT_AUD_SAM_DROP_INT                           0x00000004
+#define HDMI_AUD_INT_AUD_SAM_DROP_MASK                          0x00000008
+
+#define REG_HDMI_8x60_PHY_REG0                                  0x00000300
+#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK                 0x0000001c
+#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT                2
+static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val)
+{
+        return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK;
+}
+
+#define REG_HDMI_8x60_PHY_REG1                                  0x00000304
+#define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK                  0x000000f0
+#define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT                 4
+static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val)
+{
+        return ((val) << HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT) & HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK;
+}
+#define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK              0x0000000f
+#define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT             0
+static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
+{
+        return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK;
+}
+
+#define REG_HDMI_8x60_PHY_REG2                                  0x00000308
+#define HDMI_8x60_PHY_REG2_PD_DESER                             0x00000001
+#define HDMI_8x60_PHY_REG2_PD_DRIVE_1                           0x00000002
+#define HDMI_8x60_PHY_REG2_PD_DRIVE_2                           0x00000004
+#define HDMI_8x60_PHY_REG2_PD_DRIVE_3                           0x00000008
+#define HDMI_8x60_PHY_REG2_PD_DRIVE_4                           0x00000010
+#define HDMI_8x60_PHY_REG2_PD_PLL                               0x00000020
+#define HDMI_8x60_PHY_REG2_PD_PWRGEN                            0x00000040
+#define HDMI_8x60_PHY_REG2_RCV_SENSE_EN                         0x00000080
+
+#define REG_HDMI_8x60_PHY_REG3                                  0x0000030c
+#define HDMI_8x60_PHY_REG3_PLL_ENABLE                           0x00000001
+
+#define REG_HDMI_8x60_PHY_REG4                                  0x00000310
+
+#define REG_HDMI_8x60_PHY_REG5                                  0x00000314
+
+#define REG_HDMI_8x60_PHY_REG6                                  0x00000318
+
+#define REG_HDMI_8x60_PHY_REG7                                  0x0000031c
+
+#define REG_HDMI_8x60_PHY_REG8                                  0x00000320
+
+#define REG_HDMI_8x60_PHY_REG9                                  0x00000324
+
+#define REG_HDMI_8x60_PHY_REG10                                 0x00000328
+
+#define REG_HDMI_8x60_PHY_REG11                                 0x0000032c
+
+#define REG_HDMI_8x60_PHY_REG12                                 0x00000330
+#define HDMI_8x60_PHY_REG12_RETIMING_EN                         0x00000001
+#define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN                  0x00000002
+#define HDMI_8x60_PHY_REG12_FORCE_LOCK                          0x00000010
+
+#define REG_HDMI_8960_PHY_REG0                                  0x00000400
+
+#define REG_HDMI_8960_PHY_REG1                                  0x00000404
+
+#define REG_HDMI_8960_PHY_REG2                                  0x00000408
+
+#define REG_HDMI_8960_PHY_REG3                                  0x0000040c
+
+#define REG_HDMI_8960_PHY_REG4                                  0x00000410
+
+#define REG_HDMI_8960_PHY_REG5                                  0x00000414
+
+#define REG_HDMI_8960_PHY_REG6                                  0x00000418
+
+#define REG_HDMI_8960_PHY_REG7                                  0x0000041c
+
+#define REG_HDMI_8960_PHY_REG8                                  0x00000420
+
+#define REG_HDMI_8960_PHY_REG9                                  0x00000424
+
+#define REG_HDMI_8960_PHY_REG10                                 0x00000428
+
+#define REG_HDMI_8960_PHY_REG11                                 0x0000042c
+
+#define REG_HDMI_8960_PHY_REG12                                 0x00000430
+
+
+#endif /* HDMI_XML */
diff --git a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
new file mode 100644
index 000000000000..bee36363bcd0
--- /dev/null
+++ b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
@@ -0,0 +1,50 @@
+#ifndef QFPROM_XML
+#define QFPROM_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    595 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml           (  19332 bytes, from 2013-08-16 22:16:36)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1544 bytes, from 2013-08-16 19:17:05)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  19288 bytes, from 2013-08-11 18:14:15)
+
+Copyright (C) 2013 by the following authors:
+- Rob Clark <robdclark@gmail.com> (robclark)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+#define REG_QFPROM_CONFIG_ROW0_LSB                              0x00000238
+#define QFPROM_CONFIG_ROW0_LSB_HDMI_DISABLE                     0x00200000
+#define QFPROM_CONFIG_ROW0_LSB_HDCP_DISABLE                     0x00400000
+
+
+#endif /* QFPROM_XML */
diff --git a/drivers/gpu/drm/msm/mdp4/mdp4.xml.h b/drivers/gpu/drm/msm/mdp4/mdp4.xml.h
new file mode 100644
index 000000000000..bbeeebe2db55
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp4/mdp4.xml.h
@@ -0,0 +1,1061 @@
+#ifndef MDP4_XML
+#define MDP4_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    595 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml           (  19332 bytes, from 2013-08-16 22:16:36)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1544 bytes, from 2013-08-16 19:17:05)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  19288 bytes, from 2013-08-11 18:14:15)
+
+Copyright (C) 2013 by the following authors:
+- Rob Clark <robdclark@gmail.com> (robclark)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+enum mpd4_bpc {
+        BPC1 = 0,
+        BPC5 = 1,
+        BPC6 = 2,
+        BPC8 = 3,
+};
+
+enum mpd4_bpc_alpha {
+        BPC1A = 0,
+        BPC4A = 1,
+        BPC6A = 2,
+        BPC8A = 3,
+};
+
+enum mpd4_alpha_type {
+        FG_CONST = 0,
+        BG_CONST = 1,
+        FG_PIXEL = 2,
+        BG_PIXEL = 3,
+};
+
+enum mpd4_pipe {
+        VG1 = 0,
+        VG2 = 1,
+        RGB1 = 2,
+        RGB2 = 3,
+        RGB3 = 4,
+        VG3 = 5,
+        VG4 = 6,
+};
+
+enum mpd4_mixer {
+        MIXER0 = 0,
+        MIXER1 = 1,
+        MIXER2 = 2,
+};
+
+enum mpd4_mixer_stage_id {
+        STAGE_UNUSED = 0,
+        STAGE_BASE = 1,
+        STAGE0 = 2,
+        STAGE1 = 3,
+        STAGE2 = 4,
+        STAGE3 = 5,
+};
+
+enum mdp4_intf {
+        INTF_LCDC_DTV = 0,
+        INTF_DSI_VIDEO = 1,
+        INTF_DSI_CMD = 2,
+        INTF_EBI2_TV = 3,
+};
+
+enum mdp4_cursor_format {
+        CURSOR_ARGB = 1,
+        CURSOR_XRGB = 2,
+};
+
+enum mdp4_dma {
+        DMA_P = 0,
+        DMA_S = 1,
+        DMA_E = 2,
+};
+
+#define MDP4_IRQ_OVERLAY0_DONE                                  0x00000001
+#define MDP4_IRQ_OVERLAY1_DONE                                  0x00000002
+#define MDP4_IRQ_DMA_S_DONE                                     0x00000004
+#define MDP4_IRQ_DMA_E_DONE                                     0x00000008
+#define MDP4_IRQ_DMA_P_DONE                                     0x00000010
+#define MDP4_IRQ_VG1_HISTOGRAM                                  0x00000020
+#define MDP4_IRQ_VG2_HISTOGRAM                                  0x00000040
+#define MDP4_IRQ_PRIMARY_VSYNC                                  0x00000080
+#define MDP4_IRQ_PRIMARY_INTF_UDERRUN                           0x00000100
+#define MDP4_IRQ_EXTERNAL_VSYNC                                 0x00000200
+#define MDP4_IRQ_EXTERNAL_INTF_UDERRUN                          0x00000400
+#define MDP4_IRQ_PRIMARY_RDPTR                                  0x00000800
+#define MDP4_IRQ_DMA_P_HISTOGRAM                                0x00020000
+#define MDP4_IRQ_DMA_S_HISTOGRAM                                0x04000000
+#define MDP4_IRQ_OVERLAY2_DONE                                  0x40000000
+#define REG_MDP4_VERSION                                        0x00000000
+#define MDP4_VERSION_MINOR__MASK                                0x00ff0000
+#define MDP4_VERSION_MINOR__SHIFT                               16
+static inline uint32_t MDP4_VERSION_MINOR(uint32_t val)
+{
+        return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK;
+}
+#define MDP4_VERSION_MAJOR__MASK                                0xff000000
+#define MDP4_VERSION_MAJOR__SHIFT                               24
+static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val)
+{
+        return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK;
+}
+
+#define REG_MDP4_OVLP0_KICK                                     0x00000004
+
+#define REG_MDP4_OVLP1_KICK                                     0x00000008
+
+#define REG_MDP4_OVLP2_KICK                                     0x000000d0
+
+#define REG_MDP4_DMA_P_KICK                                     0x0000000c
+
+#define REG_MDP4_DMA_S_KICK                                     0x00000010
+
+#define REG_MDP4_DMA_E_KICK                                     0x00000014
+
+#define REG_MDP4_DISP_STATUS                                    0x00000018
+
+#define REG_MDP4_DISP_INTF_SEL                                  0x00000038
+#define MDP4_DISP_INTF_SEL_PRIM__MASK                           0x00000003
+#define MDP4_DISP_INTF_SEL_PRIM__SHIFT                          0
+static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)
+{
+        return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK;
+}
+#define MDP4_DISP_INTF_SEL_SEC__MASK                            0x0000000c
+#define MDP4_DISP_INTF_SEL_SEC__SHIFT                           2
+static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)
+{
+        return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK;
+}
+#define MDP4_DISP_INTF_SEL_EXT__MASK                            0x00000030
+#define MDP4_DISP_INTF_SEL_EXT__SHIFT                           4
+static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)
+{
+        return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK;
+}
+#define MDP4_DISP_INTF_SEL_DSI_VIDEO                            0x00000040
+#define MDP4_DISP_INTF_SEL_DSI_CMD                              0x00000080
+
+#define REG_MDP4_RESET_STATUS                                   0x0000003c
+
+#define REG_MDP4_READ_CNFG                                      0x0000004c
+
+#define REG_MDP4_INTR_ENABLE                                    0x00000050
+
+#define REG_MDP4_INTR_STATUS                                    0x00000054
+
+#define REG_MDP4_INTR_CLEAR                                     0x00000058
+
+#define REG_MDP4_EBI2_LCD0                                      0x00000060
+
+#define REG_MDP4_EBI2_LCD1                                      0x00000064
+
+#define REG_MDP4_PORTMAP_MODE                                   0x00000070
+
+#define REG_MDP4_CS_CONTROLLER0                                 0x000000c0
+
+#define REG_MDP4_CS_CONTROLLER1                                 0x000000c4
+
+#define REG_MDP4_LAYERMIXER2_IN_CFG                             0x000100f0
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK                     0x00000007
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT                    0
+static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mpd4_mixer_stage_id val)
+{
+        return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;
+}
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1                    0x00000008
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK                     0x00000070
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT                    4
+static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mpd4_mixer_stage_id val)
+{
+        return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;
+}
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1                    0x00000080
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK                     0x00000700
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT                    8
+static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mpd4_mixer_stage_id val)
+{
+        return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;
+}
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1                    0x00000800
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK                     0x00007000
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT                    12
+static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mpd4_mixer_stage_id val)
+{
+        return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;
+}
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1                    0x00008000
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK                     0x00070000
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT                    16
+static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mpd4_mixer_stage_id val)
+{
+        return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;
+}
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1                    0x00080000
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK                     0x00700000
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT                    20
+static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mpd4_mixer_stage_id val)
+{
+        return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;
+}
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1                    0x00800000
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK                     0x07000000
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT                    24
+static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mpd4_mixer_stage_id val)
+{
+        return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;
+}
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1                    0x08000000
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK                     0x70000000
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT                    28
+static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mpd4_mixer_stage_id val)
+{
+        return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;
+}
+#define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1                    0x80000000
+
+#define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD                0x000100fc
+
+#define REG_MDP4_LAYERMIXER_IN_CFG                              0x00010100
+#define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK                      0x00000007
+#define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT                     0
+static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mpd4_mixer_stage_id val)
+{
+        return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;
+}
+#define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1                     0x00000008
+#define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK                      0x00000070
+#define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT                     4
+static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mpd4_mixer_stage_id val)
+{
+        return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;
+}
+#define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1                     0x00000080
+#define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK                      0x00000700
+#define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT                     8
+static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mpd4_mixer_stage_id val)
+{
+        return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;
+}
+#define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1                     0x00000800
+#define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK                      0x00007000
+#define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT                     12
+static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mpd4_mixer_stage_id val)
+{
+        return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;
+}
+#define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1                     0x00008000
+#define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK                      0x00070000
+#define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT                     16
+static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mpd4_mixer_stage_id val)
+{
+        return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;
+}
+#define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1                     0x00080000
+#define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK                      0x00700000
+#define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT                     20
+static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mpd4_mixer_stage_id val)
+{
+        return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;
+}
+#define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1                     0x00800000
+#define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK                      0x07000000
+#define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT                     24
+static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mpd4_mixer_stage_id val)
+{
+        return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;
+}
+#define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1                     0x08000000
+#define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK                      0x70000000
+#define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT                     28
+static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mpd4_mixer_stage_id val)
+{
+        return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;
+}
+#define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1                     0x80000000
+
+#define REG_MDP4_VG2_SRC_FORMAT                                 0x00030050
+
+#define REG_MDP4_VG2_CONST_COLOR                                0x00031008
+
+#define REG_MDP4_OVERLAY_FLUSH                                  0x00018000
+#define MDP4_OVERLAY_FLUSH_OVLP0                                0x00000001
+#define MDP4_OVERLAY_FLUSH_OVLP1                                0x00000002
+#define MDP4_OVERLAY_FLUSH_VG1                                  0x00000004
+#define MDP4_OVERLAY_FLUSH_VG2                                  0x00000008
+#define MDP4_OVERLAY_FLUSH_RGB1                                 0x00000010
+#define MDP4_OVERLAY_FLUSH_RGB2                                 0x00000020
+
+static inline uint32_t __offset_OVLP(uint32_t idx)
+{
+        switch (idx) {
+                case 0: return 0x00010000;
+                case 1: return 0x00018000;
+                case 2: return 0x00088000;
+                default: return INVALID_IDX(idx);
+        }
+}
+static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); }
+
+static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); }
+
+static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); }
+#define MDP4_OVLP_SIZE_HEIGHT__MASK                             0xffff0000
+#define MDP4_OVLP_SIZE_HEIGHT__SHIFT                            16
+static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val)
+{
+        return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK;
+}
+#define MDP4_OVLP_SIZE_WIDTH__MASK                              0x0000ffff
+#define MDP4_OVLP_SIZE_WIDTH__SHIFT                             0
+static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val)
+{
+        return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK;
+}
+
+static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); }
+
+static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); }
+
+static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); }
+
+static inline uint32_t __offset_STAGE(uint32_t idx)
+{
+        switch (idx) {
+                case 0: return 0x00000104;
+                case 1: return 0x00000124;
+                case 2: return 0x00000144;
+                case 3: return 0x00000160;
+                default: return INVALID_IDX(idx);
+        }
+}
+static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
+
+static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
+#define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK                       0x00000003
+#define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT                      0
+static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mpd4_alpha_type val)
+{
+        return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;
+}
+#define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA                         0x00000004
+#define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA                         0x00000008
+#define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK                       0x00000030
+#define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT                      4
+static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mpd4_alpha_type val)
+{
+        return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;
+}
+#define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA                         0x00000040
+#define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA                         0x00000080
+#define MDP4_OVLP_STAGE_OP_FG_TRANSP                            0x00000100
+#define MDP4_OVLP_STAGE_OP_BG_TRANSP                            0x00000200
+
+static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); }
+
+static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); }
+
+static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); }
+
+static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); }
+
+static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); }
+
+static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); }
+
+static inline uint32_t __offset_STAGE_CO3(uint32_t idx)
+{
+        switch (idx) {
+                case 0: return 0x00001004;
+                case 1: return 0x00001404;
+                case 2: return 0x00001804;
+                case 3: return 0x00001b84;
+                default: return INVALID_IDX(idx);
+        }
+}
+static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
+
+static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
+#define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA                        0x00000001
+
+static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); }
+
+static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); }
+
+static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); }
+
+static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); }
+
+static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); }
+
+static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); }
+
+
+static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
+
+#define REG_MDP4_DMA_P_OP_MODE                                  0x00090070
+
+static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; }
+
+static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
+
+#define REG_MDP4_DMA_S_OP_MODE                                  0x000a0028
+
+static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; }
+
+static inline uint32_t __offset_DMA(enum mdp4_dma idx)
+{
+        switch (idx) {
+                case DMA_P: return 0x00090000;
+                case DMA_S: return 0x000a0000;
+                case DMA_E: return 0x000b0000;
+                default: return INVALID_IDX(idx);
+        }
+}
+static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
+
+static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
+#define MDP4_DMA_CONFIG_G_BPC__MASK                             0x00000003
+#define MDP4_DMA_CONFIG_G_BPC__SHIFT                            0
+static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mpd4_bpc val)
+{
+        return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;
+}
+#define MDP4_DMA_CONFIG_B_BPC__MASK                             0x0000000c
+#define MDP4_DMA_CONFIG_B_BPC__SHIFT                            2
+static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mpd4_bpc val)
+{
+        return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;
+}
+#define MDP4_DMA_CONFIG_R_BPC__MASK                             0x00000030
+#define MDP4_DMA_CONFIG_R_BPC__SHIFT                            4
+static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mpd4_bpc val)
+{
+        return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;
+}
+#define MDP4_DMA_CONFIG_PACK_ALIGN_MSB                          0x00000080
+#define MDP4_DMA_CONFIG_PACK__MASK                              0x0000ff00
+#define MDP4_DMA_CONFIG_PACK__SHIFT                             8
+static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val)
+{
+        return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK;
+}
+#define MDP4_DMA_CONFIG_DEFLKR_EN                               0x01000000
+#define MDP4_DMA_CONFIG_DITHER_EN                               0x01000000
+
+static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); }
+#define MDP4_DMA_SRC_SIZE_HEIGHT__MASK                          0xffff0000
+#define MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT                         16
+static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val)
+{
+        return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK;
+}
+#define MDP4_DMA_SRC_SIZE_WIDTH__MASK                           0x0000ffff
+#define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT                          0
+static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val)
+{
+        return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK;
+}
+
+static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); }
+
+static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); }
+
+static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); }
+#define MDP4_DMA_DST_SIZE_HEIGHT__MASK                          0xffff0000
+#define MDP4_DMA_DST_SIZE_HEIGHT__SHIFT                         16
+static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val)
+{
+        return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK;
+}
+#define MDP4_DMA_DST_SIZE_WIDTH__MASK                           0x0000ffff
+#define MDP4_DMA_DST_SIZE_WIDTH__SHIFT                          0
+static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val)
+{
+        return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK;
+}
+
+static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); }
+#define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK                        0x0000007f
+#define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT                       0
+static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val)
+{
+        return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK;
+}
+#define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK                       0x007f0000
+#define MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT                      16
+static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val)
+{
+        return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK;
+}
+
+static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); }
+
+static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); }
+#define MDP4_DMA_CURSOR_POS_X__MASK                             0x0000ffff
+#define MDP4_DMA_CURSOR_POS_X__SHIFT                            0
+static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val)
+{
+        return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK;
+}
+#define MDP4_DMA_CURSOR_POS_Y__MASK                             0xffff0000
+#define MDP4_DMA_CURSOR_POS_Y__SHIFT                            16
+static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val)
+{
+        return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK;
+}
+
+static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); }
+#define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN                  0x00000001
+#define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK               0x00000006
+#define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT              1
+static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)
+{
+        return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK;
+}
+#define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN                  0x00000008
+
+static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); }
+
+static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); }
+
+static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); }
+
+static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); }
+
+static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); }
+
+
+static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_PIPE(enum mpd4_pipe i0) { return 0x00020000 + 0x10000*i0; }
+
+static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mpd4_pipe i0) { return 0x00020000 + 0x10000*i0; }
+#define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK                         0xffff0000
+#define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT                        16
+static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK;
+}
+#define MDP4_PIPE_SRC_SIZE_WIDTH__MASK                          0x0000ffff
+#define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT                         0
+static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK;
+}
+
+static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mpd4_pipe i0) { return 0x00020004 + 0x10000*i0; }
+#define MDP4_PIPE_SRC_XY_Y__MASK                                0xffff0000
+#define MDP4_PIPE_SRC_XY_Y__SHIFT                               16
+static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK;
+}
+#define MDP4_PIPE_SRC_XY_X__MASK                                0x0000ffff
+#define MDP4_PIPE_SRC_XY_X__SHIFT                               0
+static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK;
+}
+
+static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mpd4_pipe i0) { return 0x00020008 + 0x10000*i0; }
+#define MDP4_PIPE_DST_SIZE_HEIGHT__MASK                         0xffff0000
+#define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT                        16
+static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK;
+}
+#define MDP4_PIPE_DST_SIZE_WIDTH__MASK                          0x0000ffff
+#define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT                         0
+static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK;
+}
+
+static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mpd4_pipe i0) { return 0x0002000c + 0x10000*i0; }
+#define MDP4_PIPE_DST_XY_Y__MASK                                0xffff0000
+#define MDP4_PIPE_DST_XY_Y__SHIFT                               16
+static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK;
+}
+#define MDP4_PIPE_DST_XY_X__MASK                                0x0000ffff
+#define MDP4_PIPE_DST_XY_X__SHIFT                               0
+static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK;
+}
+
+static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mpd4_pipe i0) { return 0x00020010 + 0x10000*i0; }
+
+static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mpd4_pipe i0) { return 0x00020014 + 0x10000*i0; }
+
+static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mpd4_pipe i0) { return 0x00020018 + 0x10000*i0; }
+
+static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mpd4_pipe i0) { return 0x00020040 + 0x10000*i0; }
+#define MDP4_PIPE_SRC_STRIDE_A_P0__MASK                         0x0000ffff
+#define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT                        0
+static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK;
+}
+#define MDP4_PIPE_SRC_STRIDE_A_P1__MASK                         0xffff0000
+#define MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT                        16
+static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK;
+}
+
+static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mpd4_pipe i0) { return 0x00020044 + 0x10000*i0; }
+#define MDP4_PIPE_SRC_STRIDE_B_P2__MASK                         0x0000ffff
+#define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT                        0
+static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK;
+}
+#define MDP4_PIPE_SRC_STRIDE_B_P3__MASK                         0xffff0000
+#define MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT                        16
+static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK;
+}
+
+static inline uint32_t REG_MDP4_PIPE_FRAME_SIZE(enum mpd4_pipe i0) { return 0x00020048 + 0x10000*i0; }
+#define MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK                       0xffff0000
+#define MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT                      16
+static inline uint32_t MDP4_PIPE_FRAME_SIZE_HEIGHT(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_FRAME_SIZE_HEIGHT__MASK;
+}
+#define MDP4_PIPE_FRAME_SIZE_WIDTH__MASK                        0x0000ffff
+#define MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT                       0
+static inline uint32_t MDP4_PIPE_FRAME_SIZE_WIDTH(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_FRAME_SIZE_WIDTH__MASK;
+}
+
+static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mpd4_pipe i0) { return 0x00020050 + 0x10000*i0; }
+#define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK                        0x00000003
+#define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT                       0
+static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mpd4_bpc val)
+{
+        return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;
+}
+#define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK                        0x0000000c
+#define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT                       2
+static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mpd4_bpc val)
+{
+        return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;
+}
+#define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK                        0x00000030
+#define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT                       4
+static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mpd4_bpc val)
+{
+        return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;
+}
+#define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK                        0x000000c0
+#define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT                       6
+static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mpd4_bpc_alpha val)
+{
+        return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;
+}
+#define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE                       0x00000100
+#define MDP4_PIPE_SRC_FORMAT_CPP__MASK                          0x00000600
+#define MDP4_PIPE_SRC_FORMAT_CPP__SHIFT                         9
+static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK;
+}
+#define MDP4_PIPE_SRC_FORMAT_ROTATED_90                         0x00001000
+#define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK                 0x00006000
+#define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT                13
+static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
+}
+#define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT                       0x00020000
+#define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB                   0x00040000
+#define MDP4_PIPE_SRC_FORMAT_SOLID_FILL                         0x00400000
+
+static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mpd4_pipe i0) { return 0x00020054 + 0x10000*i0; }
+#define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK                        0x000000ff
+#define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT                       0
+static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK;
+}
+#define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK                        0x0000ff00
+#define MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT                       8
+static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK;
+}
+#define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK                        0x00ff0000
+#define MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT                       16
+static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK;
+}
+#define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK                        0xff000000
+#define MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT                       24
+static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
+{
+        return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK;
+}
+
+static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mpd4_pipe i0) { return 0x00020058 + 0x10000*i0; }
+#define MDP4_PIPE_OP_MODE_SCALEX_EN                             0x00000001
+#define MDP4_PIPE_OP_MODE_SCALEY_EN                             0x00000002
+#define MDP4_PIPE_OP_MODE_SRC_YCBCR                             0x00000200
+#define MDP4_PIPE_OP_MODE_DST_YCBCR                             0x00000400
+#define MDP4_PIPE_OP_MODE_CSC_EN                                0x00000800
+#define MDP4_PIPE_OP_MODE_FLIP_LR                               0x00002000
+#define MDP4_PIPE_OP_MODE_FLIP_UD                               0x00004000
+#define MDP4_PIPE_OP_MODE_DITHER_EN                             0x00008000
+#define MDP4_PIPE_OP_MODE_IGC_LUT_EN                            0x00010000
+#define MDP4_PIPE_OP_MODE_DEINT_EN                              0x00040000
+#define MDP4_PIPE_OP_MODE_DEINT_ODD_REF                         0x00080000
+
+static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mpd4_pipe i0) { return 0x0002005c + 0x10000*i0; }
+
+static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mpd4_pipe i0) { return 0x00020060 + 0x10000*i0; }
+
+static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mpd4_pipe i0) { return 0x00021004 + 0x10000*i0; }
+
+static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mpd4_pipe i0) { return 0x00021008 + 0x10000*i0; }
+
+static inline uint32_t REG_MDP4_PIPE_CSC(enum mpd4_pipe i0) { return 0x00024000 + 0x10000*i0; }
+
+
+static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mpd4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mpd4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mpd4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mpd4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mpd4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mpd4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mpd4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mpd4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mpd4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
+
+static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mpd4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
+
+#define REG_MDP4_LCDC                                           0x000c0000
+
+#define REG_MDP4_LCDC_ENABLE                                    0x000c0000
+
+#define REG_MDP4_LCDC_HSYNC_CTRL                                0x000c0004
+#define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK                       0x0000ffff
+#define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT                      0
+static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val)
+{
+        return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK;
+}
+#define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK                       0xffff0000
+#define MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT                      16
+static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val)
+{
+        return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK;
+}
+
+#define REG_MDP4_LCDC_VSYNC_PERIOD                              0x000c0008
+
+#define REG_MDP4_LCDC_VSYNC_LEN                                 0x000c000c
+
+#define REG_MDP4_LCDC_DISPLAY_HCTRL                             0x000c0010
+#define MDP4_LCDC_DISPLAY_HCTRL_START__MASK                     0x0000ffff
+#define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT                    0
+static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val)
+{
+        return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK;
+}
+#define MDP4_LCDC_DISPLAY_HCTRL_END__MASK                       0xffff0000
+#define MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT                      16
+static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val)
+{
+        return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK;
+}
+
+#define REG_MDP4_LCDC_DISPLAY_VSTART                            0x000c0014
+
+#define REG_MDP4_LCDC_DISPLAY_VEND                              0x000c0018
+
+#define REG_MDP4_LCDC_ACTIVE_HCTL                               0x000c001c
+#define MDP4_LCDC_ACTIVE_HCTL_START__MASK                       0x00007fff
+#define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT                      0
+static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val)
+{
+        return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK;
+}
+#define MDP4_LCDC_ACTIVE_HCTL_END__MASK                         0x7fff0000
+#define MDP4_LCDC_ACTIVE_HCTL_END__SHIFT                        16
+static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val)
+{
+        return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK;
+}
+#define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X                    0x80000000
+
+#define REG_MDP4_LCDC_ACTIVE_VSTART                             0x000c0020
+
+#define REG_MDP4_LCDC_ACTIVE_VEND                               0x000c0024
+
+#define REG_MDP4_LCDC_BORDER_CLR                                0x000c0028
+
+#define REG_MDP4_LCDC_UNDERFLOW_CLR                             0x000c002c
+#define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK                     0x00ffffff
+#define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT                    0
+static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val)
+{
+        return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK;
+}
+#define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY                 0x80000000
+
+#define REG_MDP4_LCDC_HSYNC_SKEW                                0x000c0030
+
+#define REG_MDP4_LCDC_TEST_CNTL                                 0x000c0034
+
+#define REG_MDP4_LCDC_CTRL_POLARITY                             0x000c0038
+#define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW                       0x00000001
+#define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW                       0x00000002
+#define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW                     0x00000004
+
+#define REG_MDP4_DTV                                            0x000d0000
+
+#define REG_MDP4_DTV_ENABLE                                     0x000d0000
+
+#define REG_MDP4_DTV_HSYNC_CTRL                                 0x000d0004
+#define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK                        0x0000ffff
+#define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT                       0
+static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val)
+{
+        return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK;
+}
+#define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK                        0xffff0000
+#define MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT                       16
+static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val)
+{
+        return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK;
+}
+
+#define REG_MDP4_DTV_VSYNC_PERIOD                               0x000d0008
+
+#define REG_MDP4_DTV_VSYNC_LEN                                  0x000d000c
+
+#define REG_MDP4_DTV_DISPLAY_HCTRL                              0x000d0018
+#define MDP4_DTV_DISPLAY_HCTRL_START__MASK                      0x0000ffff
+#define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT                     0
+static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val)
+{
+        return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK;
+}
+#define MDP4_DTV_DISPLAY_HCTRL_END__MASK                        0xffff0000
+#define MDP4_DTV_DISPLAY_HCTRL_END__SHIFT                       16
+static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val)
+{
+        return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK;
+}
+
+#define REG_MDP4_DTV_DISPLAY_VSTART                             0x000d001c
+
+#define REG_MDP4_DTV_DISPLAY_VEND                               0x000d0020
+
+#define REG_MDP4_DTV_ACTIVE_HCTL                                0x000d002c
+#define MDP4_DTV_ACTIVE_HCTL_START__MASK                        0x00007fff
+#define MDP4_DTV_ACTIVE_HCTL_START__SHIFT                       0
+static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val)
+{
+        return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK;
+}
+#define MDP4_DTV_ACTIVE_HCTL_END__MASK                          0x7fff0000
+#define MDP4_DTV_ACTIVE_HCTL_END__SHIFT                         16
+static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val)
+{
+        return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK;
+}
+#define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X                     0x80000000
+
+#define REG_MDP4_DTV_ACTIVE_VSTART                              0x000d0030
+
+#define REG_MDP4_DTV_ACTIVE_VEND                                0x000d0038
+
+#define REG_MDP4_DTV_BORDER_CLR                                 0x000d0040
+
+#define REG_MDP4_DTV_UNDERFLOW_CLR                              0x000d0044
+#define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK                      0x00ffffff
+#define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT                     0
+static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val)
+{
+        return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK;
+}
+#define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY                  0x80000000
+
+#define REG_MDP4_DTV_HSYNC_SKEW                                 0x000d0048
+
+#define REG_MDP4_DTV_TEST_CNTL                                  0x000d004c
+
+#define REG_MDP4_DTV_CTRL_POLARITY                              0x000d0050
+#define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW                        0x00000001
+#define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW                        0x00000002
+#define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW                      0x00000004
+
+#define REG_MDP4_DSI                                            0x000e0000
+
+#define REG_MDP4_DSI_ENABLE                                     0x000e0000
+
+#define REG_MDP4_DSI_HSYNC_CTRL                                 0x000e0004
+#define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK                        0x0000ffff
+#define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT                       0
+static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val)
+{
+        return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK;
+}
+#define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK                        0xffff0000
+#define MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT                       16
+static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val)
+{
+        return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK;
+}
+
+#define REG_MDP4_DSI_VSYNC_PERIOD                               0x000e0008
+
+#define REG_MDP4_DSI_VSYNC_LEN                                  0x000e000c
+
+#define REG_MDP4_DSI_DISPLAY_HCTRL                              0x000e0010
+#define MDP4_DSI_DISPLAY_HCTRL_START__MASK                      0x0000ffff
+#define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT                     0
+static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val)
+{
+        return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK;
+}
+#define MDP4_DSI_DISPLAY_HCTRL_END__MASK                        0xffff0000
+#define MDP4_DSI_DISPLAY_HCTRL_END__SHIFT                       16
+static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val)
+{
+        return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK;
+}
+
+#define REG_MDP4_DSI_DISPLAY_VSTART                             0x000e0014
+
+#define REG_MDP4_DSI_DISPLAY_VEND                               0x000e0018
+
+#define REG_MDP4_DSI_ACTIVE_HCTL                                0x000e001c
+#define MDP4_DSI_ACTIVE_HCTL_START__MASK                        0x00007fff
+#define MDP4_DSI_ACTIVE_HCTL_START__SHIFT                       0
+static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val)
+{
+        return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK;
+}
+#define MDP4_DSI_ACTIVE_HCTL_END__MASK                          0x7fff0000
+#define MDP4_DSI_ACTIVE_HCTL_END__SHIFT                         16
+static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val)
+{
+        return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK;
+}
+#define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X                     0x80000000
+
+#define REG_MDP4_DSI_ACTIVE_VSTART                              0x000e0020
+
+#define REG_MDP4_DSI_ACTIVE_VEND                                0x000e0024
+
+#define REG_MDP4_DSI_BORDER_CLR                                 0x000e0028
+
+#define REG_MDP4_DSI_UNDERFLOW_CLR                              0x000e002c
+#define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK                      0x00ffffff
+#define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT                     0
+static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val)
+{
+        return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK;
+}
+#define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY                  0x80000000
+
+#define REG_MDP4_DSI_HSYNC_SKEW                                 0x000e0030
+
+#define REG_MDP4_DSI_TEST_CNTL                                  0x000e0034
+
+#define REG_MDP4_DSI_CTRL_POLARITY                              0x000e0038
+#define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW                        0x00000001
+#define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW                        0x00000002
+#define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW                      0x00000004
+
+
+#endif /* MDP4_XML */