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| author | Markos Chandras <markos.chandras@imgtec.com> | 2014-07-18 05:51:31 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-09-22 07:35:52 -0400 |
| commit | 80bc94d10466c710158d5f30c43625ed9fa59e78 (patch) | |
| tree | d91cca1d045d8fccf6503747459a027114c239b3 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | fb02035083d9e2de1deba529b45835a698944f07 (diff) | |
MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores
Ingenic uses the CCA:1 bit to achieve write-combine memory writes.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7401/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions