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-rw-r--r--arch/mips/include/asm/pgtable-bits.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 011b0dcf306e..e747bfa0be7e 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -240,6 +240,11 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
240#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ 240#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
241#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ 241#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
242 242
243#elif defined(CONFIG_MACH_JZ4740)
244
245/* Ingenic uses the WA bit to achieve write-combine memory writes */
246#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
247
243#endif 248#endif
244 249
245#ifndef _CACHE_CACHABLE_NO_WA 250#ifndef _CACHE_CACHABLE_NO_WA