litmus-rt.git - The LITMUS^RT kernel.

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author	Linus Torvalds <torvalds@linux-foundation.org>	2013-11-29 12:57:13 -0500
committer	Linus Torvalds <torvalds@linux-foundation.org>	2013-11-29 12:57:13 -0500
commit	d5ff835f88c7c346ba748f389bd4ef5eae619ebc (patch)
tree	8feddb009e4479fbdad95284d72e4aa3c629038f /scripts/dtc/libfdt/fdt.c
parent	033dbbdec3ab178e5fe063a992b8c90ad08fd18c (diff)
parent	3676f9ef5481d614f8c5c857f5319755be248268 (diff)

Merge tag 'arm64-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64

Pull ARM64 fixes from Catalin Marinas: - Remove preempt_count modifications in the arm64 IRQ handling code since that's already dealt with in generic irq_enter/irq_exit - PTE_PROT_NONE bit moved higher up to avoid overlapping with the hardware bits (for PROT_NONE mappings which are pte_present) - Big-endian fixes for ptrace support - Asynchronous aborts unmasking while in the kernel - pgprot_writecombine() change to create Normal NonCacheable memory rather than Device GRE * tag 'arm64-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: arm64: Move PTE_PROT_NONE higher up arm64: Use Normal NonCacheable memory for writecombine arm64: debug: make aarch32 bkpt checking endian clean arm64: ptrace: fix compat registes get/set to be endian clean arm64: Unmask asynchronous aborts when in kernel mode arm64: dts: Reserve the memory used for secondary CPU release address arm64: let the core code deal with preempt_count

Diffstat (limited to 'scripts/dtc/libfdt/fdt.c')

0 files changed, 0 insertions, 0 deletions

/* * linux/arch/arm/mach-omap2/timer.c * * OMAP2 GP timer support. * * Copyright (C) 2009 Nokia Corporation * * Update to use new clocksource/clockevent layers * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> * Copyright (C) 2007 MontaVista Software, Inc. * * Original driver: * Copyright (C) 2005 Nokia Corporation * Author: Paul Mundt <paul.mundt@nokia.com> * Juha Yrjölä <juha.yrjola@nokia.com> * OMAP Dual-mode timer framework support by Timo Teras * * Some parts based off of TI's 24xx code: * * Copyright (C) 2004-2009 Texas Instruments, Inc. * * Roughly modelled after the OMAP1 MPU timer code. * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ #include <linux/init.h> #include <linux/time.h> #include <linux/interrupt.h> #include <linux/err.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/irq.h> #include <linux/clocksource.h> #include <linux/clockchips.h> #include <linux/slab.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/platform_data/dmtimer-omap.h> #include <linux/sched_clock.h> #include <asm/mach/time.h> #include <asm/smp_twd.h> #include "omap_hwmod.h" #include "omap_device.h" #include <plat/counter-32k.h> #include <plat/dmtimer.h> #include "omap-pm.h" #include "soc.h" #include "common.h" #include "powerdomain.h" #include "omap-secure.h" #define REALTIME_COUNTER_BASE 0x48243200 #define INCREMENTER_NUMERATOR_OFFSET 0x10 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000 /* Clockevent code */ static struct omap_dm_timer clkev; static struct clock_event_device clockevent_gpt; #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER static unsigned long arch_timer_freq; void set_cntfreq(void) { omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); } #endif static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evt = &clockevent_gpt; __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW); evt->event_handler(evt); return IRQ_HANDLED; } static struct irqaction omap2_gp_timer_irq = { .name = "gp_timer", .flags = IRQF_TIMER | IRQF_IRQPOLL, .handler = omap2_gp_timer_interrupt, }; static int omap2_gp_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, 0xffffffff - cycles, OMAP_TIMER_POSTED); return 0; } static void omap2_gp_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { u32 period; __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate); switch (mode) { case CLOCK_EVT_MODE_PERIODIC: period = clkev.rate / HZ; period -= 1; /* Looks like we need to first set the load value separately */ __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period, OMAP_TIMER_POSTED); __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, 0xffffffff - period, OMAP_TIMER_POSTED); break; case CLOCK_EVT_MODE_ONESHOT: break; case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: case CLOCK_EVT_MODE_RESUME: break; } } static struct clock_event_device clockevent_gpt = { .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .rating = 300, .set_next_event = omap2_gp_timer_set_next_event, .set_mode = omap2_gp_timer_set_mode, }; static struct property device_disabled = { .name = "status", .length = sizeof("disabled"), .value = "disabled", }; static const struct of_device_id omap_timer_match[] __initconst = { { .compatible = "ti,omap2420-timer", }, { .compatible = "ti,omap3430-timer", }, { .compatible = "ti,omap4430-timer", }, { .compatible = "ti,omap5430-timer", }, { .compatible = "ti,am335x-timer", }, { .compatible = "ti,am335x-timer-1ms", }, { } }; /** * omap_get_timer_dt - get a timer using device-tree * @match - device-tree match structure for matching a device type * @property - optional timer property to match * * Helper function to get a timer during early boot using device-tree for use * as kernel system timer. Optionally, the property argument can be used to * select a timer with a specific property. Once a timer is found then mark * the timer node in device-tree as disabled, to prevent the kernel from * registering this timer as a platform device and so no one else can use it. */ static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match, const char *property) { struct device_node *np; for_each_matching_node(np, match) { if (!of_device_is_available(np)) continue; if (property && !of_get_property(np, property, NULL)) continue; if (!property && (of_get_property(np, "ti,timer-alwon", NULL) || of_get_property(np, "ti,timer-dsp", NULL) || of_get_property(np, "ti,timer-pwm", NULL) || of_get_property(np, "ti,timer-secure", NULL))) continue; of_add_property(np, &device_disabled); return np; } return NULL; } /** * omap_dmtimer_init - initialisation function when device tree is used * * For secure OMAP3 devices, timers with device type "timer-secure" cannot * be used by the kernel as they are reserved. Therefore, to prevent the * kernel registering these devices remove them dynamically from the device * tree on boot. */ static void __init omap_dmtimer_init(void) { struct device_node *np; if (!cpu_is_omap34xx()) return; /* If we are a secure device, remove any secure timer nodes */ if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) { np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure"); if (np) of_node_put(np); } } /** * omap_dm_timer_get_errata - get errata flags for a timer * * Get the timer errata flags that are specific to the OMAP device being used. */ static u32 __init omap_dm_timer_get_errata(void) { if (cpu_is_omap24xx()) return 0; return OMAP_TIMER_ERRATA_I103_I767; } static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, const char *fck_source, const char *property, const char **timer_name, int posted) { char name[10]; /* 10 = sizeof("gptXX_Xck0") */ const char *oh_name = NULL; struct device_node *np; struct omap_hwmod *oh; struct resource irq, mem; struct clk *src; int r = 0; if (of_have_populated_dt()) { np = omap_get_timer_dt(omap_timer_match, property); if (!np) return -ENODEV; of_property_read_string_index(np, "ti,hwmods", 0, &oh_name); if (!oh_name) return -ENODEV; timer->irq = irq_of_parse_and_map(np, 0); if (!timer->irq) return -ENXIO; timer->io_base = of_iomap(np, 0); of_node_put(np); } else { if (omap_dm_timer_reserve_systimer(timer->id)) return -ENODEV; sprintf(name, "timer%d", timer->id); oh_name = name; } oh = omap_hwmod_lookup(oh_name); if (!oh) return -ENODEV; *timer_name = oh->name; if (!of_have_populated_dt()) { r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq); if (r) return -ENXIO; timer->irq = irq.start; r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem); if (r) return -ENXIO; /* Static mapping, never released */ timer->io_base = ioremap(mem.start, mem.end - mem.start); } if (!timer->io_base) return -ENXIO; /* After the dmtimer is using hwmod these clocks won't be needed */ timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));


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