aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
authorStephen Boyd <sboyd@codeaurora.org>2014-07-15 17:52:22 -0400
committerStephen Boyd <sboyd@codeaurora.org>2014-07-15 19:39:03 -0400
commite216ce60a9e05ab399d098f05cd86fd95c9da8d5 (patch)
treee4011df8185206e60764bb528e3be601c15a5668 /include
parentd8c25d3a1a1d61cf433654f3632a03ddaee4f781 (diff)
clk: qcom: Add support for APQ8064 multimedia clocks
The APQ8064 multimedia clock controller is fairly similar to the 8960 multimedia clock controller, except that gfx2d0/1 has been removed and the gfx3d frequency is slightly faster when using the newly introduced PLL15. We also add vcap clocks and a couple new TV clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/qcom,mmcc-msm8960.h8
-rw-r--r--include/dt-bindings/reset/qcom,mmcc-msm8960.h8
2 files changed, 16 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/include/dt-bindings/clock/qcom,mmcc-msm8960.h
index 5868ef14a777..85041b28f97f 100644
--- a/include/dt-bindings/clock/qcom,mmcc-msm8960.h
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8960.h
@@ -133,5 +133,13 @@
133#define CSIPHY0_TIMER_CLK 116 133#define CSIPHY0_TIMER_CLK 116
134#define PLL1 117 134#define PLL1 117
135#define PLL2 118 135#define PLL2 118
136#define RGB_TV_CLK 119
137#define NPL_TV_CLK 120
138#define VCAP_AHB_CLK 121
139#define VCAP_AXI_CLK 122
140#define VCAP_SRC 123
141#define VCAP_CLK 124
142#define VCAP_NPL_CLK 125
143#define PLL15 126
136 144
137#endif 145#endif
diff --git a/include/dt-bindings/reset/qcom,mmcc-msm8960.h b/include/dt-bindings/reset/qcom,mmcc-msm8960.h
index ba36ec680118..11741113a841 100644
--- a/include/dt-bindings/reset/qcom,mmcc-msm8960.h
+++ b/include/dt-bindings/reset/qcom,mmcc-msm8960.h
@@ -89,5 +89,13 @@
89#define CSI2_RESET 72 89#define CSI2_RESET 72
90#define CSI_RDI1_RESET 73 90#define CSI_RDI1_RESET 73
91#define CSI_RDI2_RESET 74 91#define CSI_RDI2_RESET 74
92#define GFX3D_AXI_RESET 75
93#define VCAP_AXI_RESET 76
94#define SMMU_VCAP_AHB_RESET 77
95#define VCAP_AHB_RESET 78
96#define CSI_RDI_RESET 79
97#define CSI_PIX_RESET 80
98#define VCAP_NPL_RESET 81
99#define VCAP_RESET 82
92 100
93#endif 101#endif