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authorStephen Boyd <sboyd@codeaurora.org>2014-07-15 17:52:22 -0400
committerStephen Boyd <sboyd@codeaurora.org>2014-07-15 19:39:03 -0400
commite216ce60a9e05ab399d098f05cd86fd95c9da8d5 (patch)
treee4011df8185206e60764bb528e3be601c15a5668
parentd8c25d3a1a1d61cf433654f3632a03ddaee4f781 (diff)
clk: qcom: Add support for APQ8064 multimedia clocks
The APQ8064 multimedia clock controller is fairly similar to the 8960 multimedia clock controller, except that gfx2d0/1 has been removed and the gfx3d frequency is slightly faster when using the newly introduced PLL15. We also add vcap clocks and a couple new TV clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,mmcc.txt1
-rw-r--r--drivers/clk/qcom/mmcc-msm8960.c433
-rw-r--r--include/dt-bindings/clock/qcom,mmcc-msm8960.h8
-rw-r--r--include/dt-bindings/reset/qcom,mmcc-msm8960.h8
4 files changed, 448 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
index 4f1f6be9e66d..29ebf84d25af 100644
--- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
@@ -4,6 +4,7 @@ Qualcomm Multimedia Clock & Reset Controller Binding
4Required properties : 4Required properties :
5- compatible : shall contain only one of the following: 5- compatible : shall contain only one of the following:
6 6
7 "qcom,mmcc-apq8064"
7 "qcom,mmcc-apq8084" 8 "qcom,mmcc-apq8084"
8 "qcom,mmcc-msm8660" 9 "qcom,mmcc-msm8660"
9 "qcom,mmcc-msm8960" 10 "qcom,mmcc-msm8960"
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
index 7985982ab4e9..255f127e8f3b 100644
--- a/drivers/clk/qcom/mmcc-msm8960.c
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -37,6 +37,7 @@
37#define P_PLL8 1 37#define P_PLL8 1
38#define P_PLL2 2 38#define P_PLL2 2
39#define P_PLL3 3 39#define P_PLL3 3
40#define P_PLL15 3
40 41
41#define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n } 42#define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
42 43
@@ -59,6 +60,20 @@ static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
59 [P_PLL3] = 3, 60 [P_PLL3] = 3,
60}; 61};
61 62
63static const char *mmcc_pxo_pll8_pll2_pll15[] = {
64 "pxo",
65 "pll8_vote",
66 "pll2",
67 "pll15",
68};
69
70static u8 mmcc_pxo_pll8_pll2_pll15_map[] = {
71 [P_PXO] = 0,
72 [P_PLL8] = 2,
73 [P_PLL2] = 1,
74 [P_PLL15] = 3,
75};
76
62static const char *mmcc_pxo_pll8_pll2_pll3[] = { 77static const char *mmcc_pxo_pll8_pll2_pll3[] = {
63 "pxo", 78 "pxo",
64 "pll8_vote", 79 "pll8_vote",
@@ -82,6 +97,36 @@ static struct clk_pll pll2 = {
82 }, 97 },
83}; 98};
84 99
100static struct clk_pll pll15 = {
101 .l_reg = 0x33c,
102 .m_reg = 0x340,
103 .n_reg = 0x344,
104 .config_reg = 0x348,
105 .mode_reg = 0x338,
106 .status_reg = 0x350,
107 .status_bit = 16,
108 .clkr.hw.init = &(struct clk_init_data){
109 .name = "pll15",
110 .parent_names = (const char *[]){ "pxo" },
111 .num_parents = 1,
112 .ops = &clk_pll_ops,
113 },
114};
115
116static const struct pll_config pll15_config = {
117 .l = 33,
118 .m = 1,
119 .n = 3,
120 .vco_val = 0x2 << 16,
121 .vco_mask = 0x3 << 16,
122 .pre_div_val = 0x0,
123 .pre_div_mask = BIT(19),
124 .post_div_val = 0x0,
125 .post_div_mask = 0x3 << 20,
126 .mn_ena_mask = BIT(22),
127 .main_output_mask = BIT(23),
128};
129
85static struct freq_tbl clk_tbl_cam[] = { 130static struct freq_tbl clk_tbl_cam[] = {
86 { 6000000, P_PLL8, 4, 1, 16 }, 131 { 6000000, P_PLL8, 4, 1, 16 },
87 { 8000000, P_PLL8, 4, 1, 12 }, 132 { 8000000, P_PLL8, 4, 1, 12 },
@@ -863,6 +908,27 @@ static struct freq_tbl clk_tbl_gfx3d[] = {
863 { } 908 { }
864}; 909};
865 910
911static struct freq_tbl clk_tbl_gfx3d_8064[] = {
912 F_MN( 27000000, P_PXO, 0, 0),
913 F_MN( 48000000, P_PLL8, 1, 8),
914 F_MN( 54857000, P_PLL8, 1, 7),
915 F_MN( 64000000, P_PLL8, 1, 6),
916 F_MN( 76800000, P_PLL8, 1, 5),
917 F_MN( 96000000, P_PLL8, 1, 4),
918 F_MN(128000000, P_PLL8, 1, 3),
919 F_MN(145455000, P_PLL2, 2, 11),
920 F_MN(160000000, P_PLL2, 1, 5),
921 F_MN(177778000, P_PLL2, 2, 9),
922 F_MN(192000000, P_PLL8, 1, 2),
923 F_MN(200000000, P_PLL2, 1, 4),
924 F_MN(228571000, P_PLL2, 2, 7),
925 F_MN(266667000, P_PLL2, 1, 3),
926 F_MN(320000000, P_PLL2, 2, 5),
927 F_MN(400000000, P_PLL2, 1, 2),
928 F_MN(450000000, P_PLL15, 1, 2),
929 { }
930};
931
866static struct clk_dyn_rcg gfx3d_src = { 932static struct clk_dyn_rcg gfx3d_src = {
867 .ns_reg = 0x008c, 933 .ns_reg = 0x008c,
868 .md_reg[0] = 0x0084, 934 .md_reg[0] = 0x0084,
@@ -905,6 +971,13 @@ static struct clk_dyn_rcg gfx3d_src = {
905 }, 971 },
906}; 972};
907 973
974static const struct clk_init_data gfx3d_8064_init = {
975 .name = "gfx3d_src",
976 .parent_names = mmcc_pxo_pll8_pll2_pll15,
977 .num_parents = 4,
978 .ops = &clk_dyn_rcg_ops,
979};
980
908static struct clk_branch gfx3d_clk = { 981static struct clk_branch gfx3d_clk = {
909 .halt_reg = 0x01c8, 982 .halt_reg = 0x01c8,
910 .halt_bit = 4, 983 .halt_bit = 4,
@@ -921,6 +994,91 @@ static struct clk_branch gfx3d_clk = {
921 }, 994 },
922}; 995};
923 996
997static struct freq_tbl clk_tbl_vcap[] = {
998 F_MN( 27000000, P_PXO, 0, 0),
999 F_MN( 54860000, P_PLL8, 1, 7),
1000 F_MN( 64000000, P_PLL8, 1, 6),
1001 F_MN( 76800000, P_PLL8, 1, 5),
1002 F_MN(128000000, P_PLL8, 1, 3),
1003 F_MN(160000000, P_PLL2, 1, 5),
1004 F_MN(200000000, P_PLL2, 1, 4),
1005 { }
1006};
1007
1008static struct clk_dyn_rcg vcap_src = {
1009 .ns_reg = 0x021c,
1010 .md_reg[0] = 0x01ec,
1011 .md_reg[1] = 0x0218,
1012 .mn[0] = {
1013 .mnctr_en_bit = 8,
1014 .mnctr_reset_bit = 23,
1015 .mnctr_mode_shift = 9,
1016 .n_val_shift = 18,
1017 .m_val_shift = 4,
1018 .width = 4,
1019 },
1020 .mn[1] = {
1021 .mnctr_en_bit = 5,
1022 .mnctr_reset_bit = 22,
1023 .mnctr_mode_shift = 6,
1024 .n_val_shift = 14,
1025 .m_val_shift = 4,
1026 .width = 4,
1027 },
1028 .s[0] = {
1029 .src_sel_shift = 3,
1030 .parent_map = mmcc_pxo_pll8_pll2_map,
1031 },
1032 .s[1] = {
1033 .src_sel_shift = 0,
1034 .parent_map = mmcc_pxo_pll8_pll2_map,
1035 },
1036 .mux_sel_bit = 11,
1037 .freq_tbl = clk_tbl_vcap,
1038 .clkr = {
1039 .enable_reg = 0x0178,
1040 .enable_mask = BIT(2),
1041 .hw.init = &(struct clk_init_data){
1042 .name = "vcap_src",
1043 .parent_names = mmcc_pxo_pll8_pll2,
1044 .num_parents = 3,
1045 .ops = &clk_dyn_rcg_ops,
1046 },
1047 },
1048};
1049
1050static struct clk_branch vcap_clk = {
1051 .halt_reg = 0x0240,
1052 .halt_bit = 15,
1053 .clkr = {
1054 .enable_reg = 0x0178,
1055 .enable_mask = BIT(0),
1056 .hw.init = &(struct clk_init_data){
1057 .name = "vcap_clk",
1058 .parent_names = (const char *[]){ "vcap_src" },
1059 .num_parents = 1,
1060 .ops = &clk_branch_ops,
1061 .flags = CLK_SET_RATE_PARENT,
1062 },
1063 },
1064};
1065
1066static struct clk_branch vcap_npl_clk = {
1067 .halt_reg = 0x0240,
1068 .halt_bit = 25,
1069 .clkr = {
1070 .enable_reg = 0x0178,
1071 .enable_mask = BIT(13),
1072 .hw.init = &(struct clk_init_data){
1073 .name = "vcap_npl_clk",
1074 .parent_names = (const char *[]){ "vcap_src" },
1075 .num_parents = 1,
1076 .ops = &clk_branch_ops,
1077 .flags = CLK_SET_RATE_PARENT,
1078 },
1079 },
1080};
1081
924static struct freq_tbl clk_tbl_ijpeg[] = { 1082static struct freq_tbl clk_tbl_ijpeg[] = {
925 { 27000000, P_PXO, 1, 0, 0 }, 1083 { 27000000, P_PXO, 1, 0, 0 },
926 { 36570000, P_PLL8, 1, 2, 21 }, 1084 { 36570000, P_PLL8, 1, 2, 21 },
@@ -1323,6 +1481,38 @@ static struct clk_branch hdmi_tv_clk = {
1323 }, 1481 },
1324}; 1482};
1325 1483
1484static struct clk_branch rgb_tv_clk = {
1485 .halt_reg = 0x0240,
1486 .halt_bit = 27,
1487 .clkr = {
1488 .enable_reg = 0x0124,
1489 .enable_mask = BIT(14),
1490 .hw.init = &(struct clk_init_data){
1491 .parent_names = tv_src_name,
1492 .num_parents = 1,
1493 .name = "rgb_tv_clk",
1494 .ops = &clk_branch_ops,
1495 .flags = CLK_SET_RATE_PARENT,
1496 },
1497 },
1498};
1499
1500static struct clk_branch npl_tv_clk = {
1501 .halt_reg = 0x0240,
1502 .halt_bit = 26,
1503 .clkr = {
1504 .enable_reg = 0x0124,
1505 .enable_mask = BIT(16),
1506 .hw.init = &(struct clk_init_data){
1507 .parent_names = tv_src_name,
1508 .num_parents = 1,
1509 .name = "npl_tv_clk",
1510 .ops = &clk_branch_ops,
1511 .flags = CLK_SET_RATE_PARENT,
1512 },
1513 },
1514};
1515
1326static struct clk_branch hdmi_app_clk = { 1516static struct clk_branch hdmi_app_clk = {
1327 .halt_reg = 0x01cc, 1517 .halt_reg = 0x01cc,
1328 .halt_bit = 25, 1518 .halt_bit = 25,
@@ -1698,6 +1888,22 @@ static struct clk_branch rot_axi_clk = {
1698 }, 1888 },
1699}; 1889};
1700 1890
1891static struct clk_branch vcap_axi_clk = {
1892 .halt_reg = 0x0240,
1893 .halt_bit = 20,
1894 .hwcg_reg = 0x0244,
1895 .hwcg_bit = 11,
1896 .clkr = {
1897 .enable_reg = 0x0244,
1898 .enable_mask = BIT(12),
1899 .hw.init = &(struct clk_init_data){
1900 .name = "vcap_axi_clk",
1901 .ops = &clk_branch_ops,
1902 .flags = CLK_IS_ROOT,
1903 },
1904 },
1905};
1906
1701static struct clk_branch vpe_axi_clk = { 1907static struct clk_branch vpe_axi_clk = {
1702 .hwcg_reg = 0x0020, 1908 .hwcg_reg = 0x0020,
1703 .hwcg_bit = 27, 1909 .hwcg_bit = 27,
@@ -2000,6 +2206,20 @@ static struct clk_branch tv_enc_ahb_clk = {
2000 }, 2206 },
2001}; 2207};
2002 2208
2209static struct clk_branch vcap_ahb_clk = {
2210 .halt_reg = 0x0240,
2211 .halt_bit = 23,
2212 .clkr = {
2213 .enable_reg = 0x0248,
2214 .enable_mask = BIT(1),
2215 .hw.init = &(struct clk_init_data){
2216 .name = "vcap_ahb_clk",
2217 .ops = &clk_branch_ops,
2218 .flags = CLK_IS_ROOT,
2219 },
2220 },
2221};
2222
2003static struct clk_branch vcodec_ahb_clk = { 2223static struct clk_branch vcodec_ahb_clk = {
2004 .hwcg_reg = 0x0038, 2224 .hwcg_reg = 0x0038,
2005 .hwcg_bit = 26, 2225 .hwcg_bit = 26,
@@ -2212,6 +2432,175 @@ static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2212 [CSI_RDI2_RESET] = { 0x0214 }, 2432 [CSI_RDI2_RESET] = { 0x0214 },
2213}; 2433};
2214 2434
2435static struct clk_regmap *mmcc_apq8064_clks[] = {
2436 [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2437 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2438 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2439 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2440 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2441 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2442 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2443 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2444 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2445 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2446 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2447 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2448 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2449 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2450 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2451 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2452 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2453 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2454 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2455 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2456 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2457 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2458 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2459 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2460 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2461 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2462 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2463 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2464 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2465 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2466 [CSI0_SRC] = &csi0_src.clkr,
2467 [CSI0_CLK] = &csi0_clk.clkr,
2468 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2469 [CSI1_SRC] = &csi1_src.clkr,
2470 [CSI1_CLK] = &csi1_clk.clkr,
2471 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2472 [CSI2_SRC] = &csi2_src.clkr,
2473 [CSI2_CLK] = &csi2_clk.clkr,
2474 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2475 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2476 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2477 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2478 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2479 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2480 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2481 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2482 [GFX3D_SRC] = &gfx3d_src.clkr,
2483 [GFX3D_CLK] = &gfx3d_clk.clkr,
2484 [IJPEG_SRC] = &ijpeg_src.clkr,
2485 [IJPEG_CLK] = &ijpeg_clk.clkr,
2486 [JPEGD_SRC] = &jpegd_src.clkr,
2487 [JPEGD_CLK] = &jpegd_clk.clkr,
2488 [MDP_SRC] = &mdp_src.clkr,
2489 [MDP_CLK] = &mdp_clk.clkr,
2490 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2491 [ROT_SRC] = &rot_src.clkr,
2492 [ROT_CLK] = &rot_clk.clkr,
2493 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2494 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2495 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2496 [TV_SRC] = &tv_src.clkr,
2497 [VCODEC_SRC] = &vcodec_src.clkr,
2498 [VCODEC_CLK] = &vcodec_clk.clkr,
2499 [VFE_SRC] = &vfe_src.clkr,
2500 [VFE_CLK] = &vfe_clk.clkr,
2501 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2502 [VPE_SRC] = &vpe_src.clkr,
2503 [VPE_CLK] = &vpe_clk.clkr,
2504 [CAMCLK0_SRC] = &camclk0_src.clkr,
2505 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2506 [CAMCLK1_SRC] = &camclk1_src.clkr,
2507 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2508 [CAMCLK2_SRC] = &camclk2_src.clkr,
2509 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2510 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2511 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2512 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2513 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2514 [PLL2] = &pll2.clkr,
2515 [RGB_TV_CLK] = &rgb_tv_clk.clkr,
2516 [NPL_TV_CLK] = &npl_tv_clk.clkr,
2517 [VCAP_AHB_CLK] = &vcap_ahb_clk.clkr,
2518 [VCAP_AXI_CLK] = &vcap_axi_clk.clkr,
2519 [VCAP_SRC] = &vcap_src.clkr,
2520 [VCAP_CLK] = &vcap_clk.clkr,
2521 [VCAP_NPL_CLK] = &vcap_npl_clk.clkr,
2522 [PLL15] = &pll15.clkr,
2523};
2524
2525static const struct qcom_reset_map mmcc_apq8064_resets[] = {
2526 [GFX3D_AXI_RESET] = { 0x0208, 17 },
2527 [VCAP_AXI_RESET] = { 0x0208, 16 },
2528 [VPE_AXI_RESET] = { 0x0208, 15 },
2529 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2530 [MPD_AXI_RESET] = { 0x0208, 13 },
2531 [VFE_AXI_RESET] = { 0x0208, 9 },
2532 [SP_AXI_RESET] = { 0x0208, 8 },
2533 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2534 [ROT_AXI_RESET] = { 0x0208, 6 },
2535 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2536 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2537 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2538 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2539 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2540 [FAB_S0_AXI_RESET] = { 0x0208 },
2541 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2542 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2543 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2544 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2545 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2546 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2547 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2548 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2549 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2550 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2551 [APU_AHB_RESET] = { 0x020c, 18 },
2552 [CSI_AHB_RESET] = { 0x020c, 17 },
2553 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2554 [VPE_AHB_RESET] = { 0x020c, 14 },
2555 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2556 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2557 [HDMI_AHB_RESET] = { 0x020c, 9 },
2558 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2559 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2560 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2561 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2562 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2563 [MDP_AHB_RESET] = { 0x020c, 3 },
2564 [ROT_AHB_RESET] = { 0x020c, 2 },
2565 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2566 [VFE_AHB_RESET] = { 0x020c, 0 },
2567 [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 },
2568 [VCAP_AHB_RESET] = { 0x0200, 2 },
2569 [DSI2_M_AHB_RESET] = { 0x0200, 1 },
2570 [DSI2_S_AHB_RESET] = { 0x0200, 0 },
2571 [CSIPHY2_RESET] = { 0x0210, 31 },
2572 [CSI_PIX1_RESET] = { 0x0210, 30 },
2573 [CSIPHY0_RESET] = { 0x0210, 29 },
2574 [CSIPHY1_RESET] = { 0x0210, 28 },
2575 [CSI_RDI_RESET] = { 0x0210, 27 },
2576 [CSI_PIX_RESET] = { 0x0210, 26 },
2577 [DSI2_RESET] = { 0x0210, 25 },
2578 [VFE_CSI_RESET] = { 0x0210, 24 },
2579 [MDP_RESET] = { 0x0210, 21 },
2580 [AMP_RESET] = { 0x0210, 20 },
2581 [JPEGD_RESET] = { 0x0210, 19 },
2582 [CSI1_RESET] = { 0x0210, 18 },
2583 [VPE_RESET] = { 0x0210, 17 },
2584 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2585 [VFE_RESET] = { 0x0210, 15 },
2586 [GFX3D_RESET] = { 0x0210, 12 },
2587 [HDMI_RESET] = { 0x0210, 11 },
2588 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2589 [IJPEG_RESET] = { 0x0210, 9 },
2590 [CSI0_RESET] = { 0x0210, 8 },
2591 [DSI_RESET] = { 0x0210, 7 },
2592 [VCODEC_RESET] = { 0x0210, 6 },
2593 [MDP_TV_RESET] = { 0x0210, 4 },
2594 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2595 [ROT_RESET] = { 0x0210, 2 },
2596 [TV_HDMI_RESET] = { 0x0210, 1 },
2597 [VCAP_NPL_RESET] = { 0x0214, 4 },
2598 [VCAP_RESET] = { 0x0214, 3 },
2599 [CSI2_RESET] = { 0x0214, 2 },
2600 [CSI_RDI1_RESET] = { 0x0214, 1 },
2601 [CSI_RDI2_RESET] = { 0x0214 },
2602};
2603
2215static const struct regmap_config mmcc_msm8960_regmap_config = { 2604static const struct regmap_config mmcc_msm8960_regmap_config = {
2216 .reg_bits = 32, 2605 .reg_bits = 32,
2217 .reg_stride = 4, 2606 .reg_stride = 4,
@@ -2220,6 +2609,14 @@ static const struct regmap_config mmcc_msm8960_regmap_config = {
2220 .fast_io = true, 2609 .fast_io = true,
2221}; 2610};
2222 2611
2612static const struct regmap_config mmcc_apq8064_regmap_config = {
2613 .reg_bits = 32,
2614 .reg_stride = 4,
2615 .val_bits = 32,
2616 .max_register = 0x350,
2617 .fast_io = true,
2618};
2619
2223static const struct qcom_cc_desc mmcc_msm8960_desc = { 2620static const struct qcom_cc_desc mmcc_msm8960_desc = {
2224 .config = &mmcc_msm8960_regmap_config, 2621 .config = &mmcc_msm8960_regmap_config,
2225 .clks = mmcc_msm8960_clks, 2622 .clks = mmcc_msm8960_clks,
@@ -2228,15 +2625,47 @@ static const struct qcom_cc_desc mmcc_msm8960_desc = {
2228 .num_resets = ARRAY_SIZE(mmcc_msm8960_resets), 2625 .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2229}; 2626};
2230 2627
2628static const struct qcom_cc_desc mmcc_apq8064_desc = {
2629 .config = &mmcc_apq8064_regmap_config,
2630 .clks = mmcc_apq8064_clks,
2631 .num_clks = ARRAY_SIZE(mmcc_apq8064_clks),
2632 .resets = mmcc_apq8064_resets,
2633 .num_resets = ARRAY_SIZE(mmcc_apq8064_resets),
2634};
2635
2231static const struct of_device_id mmcc_msm8960_match_table[] = { 2636static const struct of_device_id mmcc_msm8960_match_table[] = {
2232 { .compatible = "qcom,mmcc-msm8960" }, 2637 { .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc },
2638 { .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc },
2233 { } 2639 { }
2234}; 2640};
2235MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table); 2641MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2236 2642
2237static int mmcc_msm8960_probe(struct platform_device *pdev) 2643static int mmcc_msm8960_probe(struct platform_device *pdev)
2238{ 2644{
2239 return qcom_cc_probe(pdev, &mmcc_msm8960_desc); 2645 const struct of_device_id *match;
2646 struct regmap *regmap;
2647 bool is_8064;
2648 struct device *dev = &pdev->dev;
2649
2650 match = of_match_device(mmcc_msm8960_match_table, dev);
2651 if (!match)
2652 return -EINVAL;
2653
2654 is_8064 = of_device_is_compatible(dev->of_node, "qcom,mmcc-apq8064");
2655 if (is_8064) {
2656 gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064;
2657 gfx3d_src.clkr.hw.init = &gfx3d_8064_init;
2658 gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
2659 gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
2660 }
2661
2662 regmap = qcom_cc_map(pdev, match->data);
2663 if (IS_ERR(regmap))
2664 return PTR_ERR(regmap);
2665
2666 clk_pll_configure_sr(&pll15, regmap, &pll15_config, false);
2667
2668 return qcom_cc_really_probe(pdev, match->data, regmap);
2240} 2669}
2241 2670
2242static int mmcc_msm8960_remove(struct platform_device *pdev) 2671static int mmcc_msm8960_remove(struct platform_device *pdev)
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/include/dt-bindings/clock/qcom,mmcc-msm8960.h
index 5868ef14a777..85041b28f97f 100644
--- a/include/dt-bindings/clock/qcom,mmcc-msm8960.h
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8960.h
@@ -133,5 +133,13 @@
133#define CSIPHY0_TIMER_CLK 116 133#define CSIPHY0_TIMER_CLK 116
134#define PLL1 117 134#define PLL1 117
135#define PLL2 118 135#define PLL2 118
136#define RGB_TV_CLK 119
137#define NPL_TV_CLK 120
138#define VCAP_AHB_CLK 121
139#define VCAP_AXI_CLK 122
140#define VCAP_SRC 123
141#define VCAP_CLK 124
142#define VCAP_NPL_CLK 125
143#define PLL15 126
136 144
137#endif 145#endif
diff --git a/include/dt-bindings/reset/qcom,mmcc-msm8960.h b/include/dt-bindings/reset/qcom,mmcc-msm8960.h
index ba36ec680118..11741113a841 100644
--- a/include/dt-bindings/reset/qcom,mmcc-msm8960.h
+++ b/include/dt-bindings/reset/qcom,mmcc-msm8960.h
@@ -89,5 +89,13 @@
89#define CSI2_RESET 72 89#define CSI2_RESET 72
90#define CSI_RDI1_RESET 73 90#define CSI_RDI1_RESET 73
91#define CSI_RDI2_RESET 74 91#define CSI_RDI2_RESET 74
92#define GFX3D_AXI_RESET 75
93#define VCAP_AXI_RESET 76
94#define SMMU_VCAP_AHB_RESET 77
95#define VCAP_AHB_RESET 78
96#define CSI_RDI_RESET 79
97#define CSI_PIX_RESET 80
98#define VCAP_NPL_RESET 81
99#define VCAP_RESET 82
92 100
93#endif 101#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-08 22:19:39 -0400