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authorLudovic Desroches <ludovic.desroches@atmel.com>2014-10-22 11:22:18 -0400
committerVinod Koul <vinod.koul@intel.com>2014-11-06 00:30:08 -0500
commite1f7c9eee70730d7e6ec77f7ecc76f936e262cf0 (patch)
treef6171edef13157c8af7a54f58aebe3ae55d24bcd /include
parent0df1f2487d2f0d04703f142813d53615d62a1da4 (diff)
dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver
New atmel DMA controller known as XDMAC, introduced with SAMA5D4 devices. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/dma/at91.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/include/dt-bindings/dma/at91.h b/include/dt-bindings/dma/at91.h
index e835037a77b4..ab6cbba45401 100644
--- a/include/dt-bindings/dma/at91.h
+++ b/include/dt-bindings/dma/at91.h
@@ -9,6 +9,8 @@
9#ifndef __DT_BINDINGS_AT91_DMA_H__ 9#ifndef __DT_BINDINGS_AT91_DMA_H__
10#define __DT_BINDINGS_AT91_DMA_H__ 10#define __DT_BINDINGS_AT91_DMA_H__
11 11
12/* ---------- HDMAC ---------- */
13
12/* 14/*
13 * Source and/or destination peripheral ID 15 * Source and/or destination peripheral ID
14 */ 16 */
@@ -24,4 +26,27 @@
24#define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ 26#define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */
25#define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ 27#define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */
26 28
29
30/* ---------- XDMAC ---------- */
31#define AT91_XDMAC_DT_MEM_IF_MASK (0x1)
32#define AT91_XDMAC_DT_MEM_IF_OFFSET (13)
33#define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \
34 << AT91_XDMAC_DT_MEM_IF_OFFSET)
35#define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
36 & AT91_XDMAC_DT_MEM_IF_MASK)
37
38#define AT91_XDMAC_DT_PER_IF_MASK (0x1)
39#define AT91_XDMAC_DT_PER_IF_OFFSET (14)
40#define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \
41 << AT91_XDMAC_DT_PER_IF_OFFSET)
42#define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
43 & AT91_XDMAC_DT_PER_IF_MASK)
44
45#define AT91_XDMAC_DT_PERID_MASK (0x7f)
46#define AT91_XDMAC_DT_PERID_OFFSET (24)
47#define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \
48 << AT91_XDMAC_DT_PERID_OFFSET)
49#define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
50 & AT91_XDMAC_DT_PERID_MASK)
51
27#endif /* __DT_BINDINGS_AT91_DMA_H__ */ 52#endif /* __DT_BINDINGS_AT91_DMA_H__ */