4 files changed, 1543 insertions, 0 deletions

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index de469821bc1b..607271a999a9 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -107,6 +107,13 @@ config AT_HDMAC
         help
           Support the Atmel AHB DMA controller.
 
+config AT_XDMAC
+        tristate "Atmel XDMA support"
+        depends on (ARCH_AT91 || COMPILE_TEST)
+        select DMA_ENGINE
+        help
+          Support the Atmel XDMA controller.
+
 config FSL_DMA
         tristate "Freescale Elo series DMA support"
         depends on FSL_SOC
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index cb626c179911..2022b5451377 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
 obj-$(CONFIG_MV_XOR) += mv_xor.o
 obj-$(CONFIG_DW_DMAC_CORE) += dw/
 obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
+obj-$(CONFIG_AT_XDMAC) += at_xdmac.o
 obj-$(CONFIG_MX3_IPU) += ipu/
 obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
 obj-$(CONFIG_SH_DMAE_BASE) += sh/
diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
new file mode 100644
index 000000000000..4e9b023990ae
--- /dev/null
+++ b/drivers/dma/at_xdmac.c
@@ -0,0 +1,1510 @@
+/*
+ * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)
+ *
+ * Copyright (C) 2014 Atmel Corporation
+ *
+ * Author: Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <asm/barrier.h>
+#include <dt-bindings/dma/at91.h>
+#include <linux/clk.h>
+#include <linux/dmaengine.h>
+#include <linux/dmapool.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/of_dma.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+
+#include "dmaengine.h"
+
+/* Global registers */
+#define AT_XDMAC_GTYPE          0x00    /* Global Type Register */
+#define         AT_XDMAC_NB_CH(i)       (((i) & 0x1F) + 1)              /* Number of Channels Minus One */
+#define         AT_XDMAC_FIFO_SZ(i)     (((i) >> 5) & 0x7FF)            /* Number of Bytes */
+#define         AT_XDMAC_NB_REQ(i)      ((((i) >> 16) & 0x3F) + 1)      /* Number of Peripheral Requests Minus One */
+#define AT_XDMAC_GCFG           0x04    /* Global Configuration Register */
+#define AT_XDMAC_GWAC           0x08    /* Global Weighted Arbiter Configuration Register */
+#define AT_XDMAC_GIE            0x0C    /* Global Interrupt Enable Register */
+#define AT_XDMAC_GID            0x10    /* Global Interrupt Disable Register */
+#define AT_XDMAC_GIM            0x14    /* Global Interrupt Mask Register */
+#define AT_XDMAC_GIS            0x18    /* Global Interrupt Status Register */
+#define AT_XDMAC_GE             0x1C    /* Global Channel Enable Register */
+#define AT_XDMAC_GD             0x20    /* Global Channel Disable Register */
+#define AT_XDMAC_GS             0x24    /* Global Channel Status Register */
+#define AT_XDMAC_GRS            0x28    /* Global Channel Read Suspend Register */
+#define AT_XDMAC_GWS            0x2C    /* Global Write Suspend Register */
+#define AT_XDMAC_GRWS           0x30    /* Global Channel Read Write Suspend Register */
+#define AT_XDMAC_GRWR           0x34    /* Global Channel Read Write Resume Register */
+#define AT_XDMAC_GSWR           0x38    /* Global Channel Software Request Register */
+#define AT_XDMAC_GSWS           0x3C    /* Global channel Software Request Status Register */
+#define AT_XDMAC_GSWF           0x40    /* Global Channel Software Flush Request Register */
+#define AT_XDMAC_VERSION        0xFFC   /* XDMAC Version Register */
+
+/* Channel relative registers offsets */
+#define AT_XDMAC_CIE            0x00    /* Channel Interrupt Enable Register */
+#define         AT_XDMAC_CIE_BIE        BIT(0)  /* End of Block Interrupt Enable Bit */
+#define         AT_XDMAC_CIE_LIE        BIT(1)  /* End of Linked List Interrupt Enable Bit */
+#define         AT_XDMAC_CIE_DIE        BIT(2)  /* End of Disable Interrupt Enable Bit */
+#define         AT_XDMAC_CIE_FIE        BIT(3)  /* End of Flush Interrupt Enable Bit */
+#define         AT_XDMAC_CIE_RBEIE      BIT(4)  /* Read Bus Error Interrupt Enable Bit */
+#define         AT_XDMAC_CIE_WBEIE      BIT(5)  /* Write Bus Error Interrupt Enable Bit */
+#define         AT_XDMAC_CIE_ROIE       BIT(6)  /* Request Overflow Interrupt Enable Bit */
+#define AT_XDMAC_CID            0x04    /* Channel Interrupt Disable Register */
+#define         AT_XDMAC_CID_BID        BIT(0)  /* End of Block Interrupt Disable Bit */
+#define         AT_XDMAC_CID_LID        BIT(1)  /* End of Linked List Interrupt Disable Bit */
+#define         AT_XDMAC_CID_DID        BIT(2)  /* End of Disable Interrupt Disable Bit */
+#define         AT_XDMAC_CID_FID        BIT(3)  /* End of Flush Interrupt Disable Bit */
+#define         AT_XDMAC_CID_RBEID      BIT(4)  /* Read Bus Error Interrupt Disable Bit */
+#define         AT_XDMAC_CID_WBEID      BIT(5)  /* Write Bus Error Interrupt Disable Bit */
+#define         AT_XDMAC_CID_ROID       BIT(6)  /* Request Overflow Interrupt Disable Bit */
+#define AT_XDMAC_CIM            0x08    /* Channel Interrupt Mask Register */
+#define         AT_XDMAC_CIM_BIM        BIT(0)  /* End of Block Interrupt Mask Bit */
+#define         AT_XDMAC_CIM_LIM        BIT(1)  /* End of Linked List Interrupt Mask Bit */
+#define         AT_XDMAC_CIM_DIM        BIT(2)  /* End of Disable Interrupt Mask Bit */
+#define         AT_XDMAC_CIM_FIM        BIT(3)  /* End of Flush Interrupt Mask Bit */
+#define         AT_XDMAC_CIM_RBEIM      BIT(4)  /* Read Bus Error Interrupt Mask Bit */
+#define         AT_XDMAC_CIM_WBEIM      BIT(5)  /* Write Bus Error Interrupt Mask Bit */
+#define         AT_XDMAC_CIM_ROIM       BIT(6)  /* Request Overflow Interrupt Mask Bit */
+#define AT_XDMAC_CIS            0x0C    /* Channel Interrupt Status Register */
+#define         AT_XDMAC_CIS_BIS        BIT(0)  /* End of Block Interrupt Status Bit */
+#define         AT_XDMAC_CIS_LIS        BIT(1)  /* End of Linked List Interrupt Status Bit */
+#define         AT_XDMAC_CIS_DIS        BIT(2)  /* End of Disable Interrupt Status Bit */
+#define         AT_XDMAC_CIS_FIS        BIT(3)  /* End of Flush Interrupt Status Bit */
+#define         AT_XDMAC_CIS_RBEIS      BIT(4)  /* Read Bus Error Interrupt Status Bit */
+#define         AT_XDMAC_CIS_WBEIS      BIT(5)  /* Write Bus Error Interrupt Status Bit */
+#define         AT_XDMAC_CIS_ROIS       BIT(6)  /* Request Overflow Interrupt Status Bit */
+#define AT_XDMAC_CSA            0x10    /* Channel Source Address Register */
+#define AT_XDMAC_CDA            0x14    /* Channel Destination Address Register */
+#define AT_XDMAC_CNDA           0x18    /* Channel Next Descriptor Address Register */
+#define         AT_XDMAC_CNDA_NDAIF(i)  ((i) & 0x1)                     /* Channel x Next Descriptor Interface */
+#define         AT_XDMAC_CNDA_NDA(i)    ((i) & 0xfffffffc)              /* Channel x Next Descriptor Address */
+#define AT_XDMAC_CNDC           0x1C    /* Channel Next Descriptor Control Register */
+#define         AT_XDMAC_CNDC_NDE               (0x1 << 0)              /* Channel x Next Descriptor Enable */
+#define         AT_XDMAC_CNDC_NDSUP             (0x1 << 1)              /* Channel x Next Descriptor Source Update */
+#define         AT_XDMAC_CNDC_NDDUP             (0x1 << 2)              /* Channel x Next Descriptor Destination Update */
+#define         AT_XDMAC_CNDC_NDVIEW_NDV0       (0x0 << 3)              /* Channel x Next Descriptor View 0 */
+#define         AT_XDMAC_CNDC_NDVIEW_NDV1       (0x1 << 3)              /* Channel x Next Descriptor View 1 */
+#define         AT_XDMAC_CNDC_NDVIEW_NDV2       (0x2 << 3)              /* Channel x Next Descriptor View 2 */
+#define         AT_XDMAC_CNDC_NDVIEW_NDV3       (0x3 << 3)              /* Channel x Next Descriptor View 3 */
+#define AT_XDMAC_CUBC           0x20    /* Channel Microblock Control Register */
+#define AT_XDMAC_CBC            0x24    /* Channel Block Control Register */
+#define AT_XDMAC_CC             0x28    /* Channel Configuration Register */
+#define         AT_XDMAC_CC_TYPE        (0x1 << 0)      /* Channel Transfer Type */
+#define                 AT_XDMAC_CC_TYPE_MEM_TRAN       (0x0 << 0)      /* Memory to Memory Transfer */
+#define                 AT_XDMAC_CC_TYPE_PER_TRAN       (0x1 << 0)      /* Peripheral to Memory or Memory to Peripheral Transfer */
+#define         AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1)
+#define                 AT_XDMAC_CC_MBSIZE_SINGLE       (0x0 << 1)
+#define                 AT_XDMAC_CC_MBSIZE_FOUR         (0x1 << 1)
+#define                 AT_XDMAC_CC_MBSIZE_EIGHT        (0x2 << 1)
+#define                 AT_XDMAC_CC_MBSIZE_SIXTEEN      (0x3 << 1)
+#define         AT_XDMAC_CC_DSYNC       (0x1 << 4)      /* Channel Synchronization */
+#define                 AT_XDMAC_CC_DSYNC_PER2MEM       (0x0 << 4)
+#define                 AT_XDMAC_CC_DSYNC_MEM2PER       (0x1 << 4)
+#define         AT_XDMAC_CC_PROT        (0x1 << 5)      /* Channel Protection */
+#define                 AT_XDMAC_CC_PROT_SEC            (0x0 << 5)
+#define                 AT_XDMAC_CC_PROT_UNSEC          (0x1 << 5)
+#define         AT_XDMAC_CC_SWREQ       (0x1 << 6)      /* Channel Software Request Trigger */
+#define                 AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6)
+#define                 AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6)
+#define         AT_XDMAC_CC_MEMSET      (0x1 << 7)      /* Channel Fill Block of memory */
+#define                 AT_XDMAC_CC_MEMSET_NORMAL_MODE  (0x0 << 7)
+#define                 AT_XDMAC_CC_MEMSET_HW_MODE      (0x1 << 7)
+#define         AT_XDMAC_CC_CSIZE(i)    ((0x7 & (i)) << 8)      /* Channel Chunk Size */
+#define         AT_XDMAC_CC_DWIDTH_OFFSET       11
+#define         AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET)
+#define         AT_XDMAC_CC_DWIDTH(i)   ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET)      /* Channel Data Width */
+#define                 AT_XDMAC_CC_DWIDTH_BYTE         0x0
+#define                 AT_XDMAC_CC_DWIDTH_HALFWORD     0x1
+#define                 AT_XDMAC_CC_DWIDTH_WORD         0x2
+#define                 AT_XDMAC_CC_DWIDTH_DWORD        0x3
+#define         AT_XDMAC_CC_SIF(i)      ((0x1 & (i)) << 13)     /* Channel Source Interface Identifier */
+#define         AT_XDMAC_CC_DIF(i)      ((0x1 & (i)) << 14)     /* Channel Destination Interface Identifier */
+#define         AT_XDMAC_CC_SAM_MASK    (0x3 << 16)     /* Channel Source Addressing Mode */
+#define                 AT_XDMAC_CC_SAM_FIXED_AM        (0x0 << 16)
+#define                 AT_XDMAC_CC_SAM_INCREMENTED_AM  (0x1 << 16)
+#define                 AT_XDMAC_CC_SAM_UBS_AM          (0x2 << 16)
+#define                 AT_XDMAC_CC_SAM_UBS_DS_AM       (0x3 << 16)
+#define         AT_XDMAC_CC_DAM_MASK    (0x3 << 18)     /* Channel Source Addressing Mode */
+#define                 AT_XDMAC_CC_DAM_FIXED_AM        (0x0 << 18)
+#define                 AT_XDMAC_CC_DAM_INCREMENTED_AM  (0x1 << 18)
+#define                 AT_XDMAC_CC_DAM_UBS_AM          (0x2 << 18)
+#define                 AT_XDMAC_CC_DAM_UBS_DS_AM       (0x3 << 18)
+#define         AT_XDMAC_CC_INITD       (0x1 << 21)     /* Channel Initialization Terminated (read only) */