Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6

* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (98 commits)
  PCI PM: Put PM callbacks in the order of execution
  PCI PM: Run default PM callbacks for all devices using new framework
  PCI PM: Register power state of devices during initialization
  PCI PM: Call pci_fixup_device from legacy routines
  PCI PM: Rearrange code in pci-driver.c
  PCI PM: Avoid touching devices behind bridges in unknown state
  PCI PM: Move pci_has_legacy_pm_support
  PCI PM: Power-manage devices without drivers during suspend-resume
  PCI PM: Add suspend counterpart of pci_reenable_device
  PCI PM: Fix poweroff and restore callbacks
  PCI: Use msleep instead of cpu_relax during ASPM link retraining
  PCI: PCIe portdrv: Add kerneldoc comments to remining core funtions
  PCI: PCIe portdrv: Rearrange code so that related things are together
  PCI: PCIe portdrv: Fix suspend and resume of PCI Express port services
  PCI: PCIe portdrv: Add kerneldoc comments to some core functions
  x86/PCI: Do not use interrupt links for devices using MSI-X
  net: sfc: Use pci_clear_master() to disable bus mastering
  PCI: Add pci_clear_master() as opposite of pci_set_master()
  PCI hotplug: remove redundant test in cpq hotplug
  PCI: pciehp: cleanup register and field definitions
  ...

5 files changed, 153 insertions, 49 deletions

diff --git a/include/linux/ioport.h b/include/linux/ioport.h
index 041e95aac2bf..f6bb2ca8e3ba 100644
--- a/include/linux/ioport.h
+++ b/include/linux/ioport.h
@@ -49,6 +49,7 @@ struct resource_list {
 #define IORESOURCE_SIZEALIGN    0x00020000      /* size indicates alignment */
 #define IORESOURCE_STARTALIGN   0x00040000      /* start field is alignment */
 
+#define IORESOURCE_EXCLUSIVE    0x08000000      /* Userland may not map this resource */
 #define IORESOURCE_DISABLED     0x10000000
 #define IORESOURCE_UNSET        0x20000000
 #define IORESOURCE_AUTO         0x40000000
@@ -133,13 +134,16 @@ static inline unsigned long resource_type(struct resource *res)
 }
 
 /* Convenience shorthand with allocation */
-#define request_region(start,n,name)    __request_region(&ioport_resource, (start), (n), (name))
-#define request_mem_region(start,n,name) __request_region(&iomem_resource, (start), (n), (name))
+#define request_region(start,n,name)    __request_region(&ioport_resource, (start), (n), (name), 0)
+#define __request_mem_region(start,n,name, excl) __request_region(&iomem_resource, (start), (n), (name), excl)
+#define request_mem_region(start,n,name) __request_region(&iomem_resource, (start), (n), (name), 0)
+#define request_mem_region_exclusive(start,n,name) \
+        __request_region(&iomem_resource, (start), (n), (name), IORESOURCE_EXCLUSIVE)
 #define rename_region(region, newname) do { (region)->name = (newname); } while (0)
 
 extern struct resource * __request_region(struct resource *,
                                         resource_size_t start,
-                                        resource_size_t n, const char *name);
+                                        resource_size_t n, const char *name, int relaxed);
 
 /* Compatibility cruft */
 #define release_region(start,n) __release_region(&ioport_resource, (start), (n))
@@ -175,6 +179,7 @@ extern struct resource * __devm_request_region(struct device *dev,
 extern void __devm_release_region(struct device *dev, struct resource *parent,
                                   resource_size_t start, resource_size_t n);
 extern int iomem_map_sanity_check(resource_size_t addr, unsigned long size);
+extern int iomem_is_exclusive(u64 addr);
 
 #endif /* __ASSEMBLY__ */
 #endif  /* _LINUX_IOPORT_H */
diff --git a/include/linux/pci-acpi.h b/include/linux/pci-acpi.h
index 8837928fbf33..042c166f65d5 100644
--- a/include/linux/pci-acpi.h
+++ b/include/linux/pci-acpi.h
@@ -8,6 +8,8 @@
 #ifndef _PCI_ACPI_H_
 #define _PCI_ACPI_H_
 
+#include <linux/acpi.h>
+
 #define OSC_QUERY_TYPE                  0
 #define OSC_SUPPORT_TYPE                1
 #define OSC_CONTROL_TYPE                2
@@ -48,15 +50,7 @@
 
 #ifdef CONFIG_ACPI
 extern acpi_status pci_osc_control_set(acpi_handle handle, u32 flags);
-extern acpi_status __pci_osc_support_set(u32 flags, const char *hid);
-static inline acpi_status pci_osc_support_set(u32 flags)
-{
-        return __pci_osc_support_set(flags, PCI_ROOT_HID_STRING);
-}
-static inline acpi_status pcie_osc_support_set(u32 flags)
-{
-        return __pci_osc_support_set(flags, PCI_EXPRESS_ROOT_HID_STRING);
-}
+int pci_acpi_osc_support(acpi_handle handle, u32 flags);
 static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
 {
         /* Find root host bridge */
@@ -66,6 +60,15 @@ static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
         return acpi_get_pci_rootbridge_handle(pci_domain_nr(pdev->bus),
                         pdev->bus->number);
 }
+
+static inline acpi_handle acpi_pci_get_bridge_handle(struct pci_bus *pbus)
+{
+        int seg = pci_domain_nr(pbus), busnr = pbus->number;
+        struct pci_dev *bridge = pbus->self;
+        if (bridge)
+                return DEVICE_ACPI_HANDLE(&(bridge->dev));
+        return acpi_get_pci_rootbridge_handle(seg, busnr);
+}
 #else
 #if !defined(AE_ERROR)
 typedef u32             acpi_status;
@@ -73,8 +76,6 @@ typedef u32 		acpi_status;
 #endif    
 static inline acpi_status pci_osc_control_set(acpi_handle handle, u32 flags)
 {return AE_ERROR;}
-static inline acpi_status pci_osc_support_set(u32 flags) {return AE_ERROR;} 
-static inline acpi_status pcie_osc_support_set(u32 flags) {return AE_ERROR;}
 static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
 { return NULL; }
 #endif
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 4bb156ba854a..80f8b8b65fde 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -82,7 +82,30 @@ enum pci_mmap_state {
 #define PCI_DMA_FROMDEVICE      2
 #define PCI_DMA_NONE            3
 
-#define DEVICE_COUNT_RESOURCE   12
+/*
+ *  For PCI devices, the region numbers are assigned this way:
+ */
+enum {
+        /* #0-5: standard PCI resources */
+        PCI_STD_RESOURCES,
+        PCI_STD_RESOURCE_END = 5,
+
+        /* #6: expansion ROM resource */
+        PCI_ROM_RESOURCE,
+
+        /* resources assigned to buses behind the bridge */
+#define PCI_BRIDGE_RESOURCE_NUM 4
+
+        PCI_BRIDGE_RESOURCES,
+        PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
+                                  PCI_BRIDGE_RESOURCE_NUM - 1,
+
+        /* total resources associated with a PCI device */
+        PCI_NUM_RESOURCES,
+
+        /* preserve this for compatibility */
+        DEVICE_COUNT_RESOURCE
+};
 
 typedef int __bitwise pci_power_t;
 
@@ -274,18 +297,6 @@ static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
         hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
 }
 
-/*
- *  For PCI devices, the region numbers are assigned this way:
- *
- *      0-5     standard PCI regions
- *      6       expansion ROM
- *      7-10    bridges: address space assigned to buses behind the bridge
- */
-
-#define PCI_ROM_RESOURCE        6
-#define PCI_BRIDGE_RESOURCES    7
-#define PCI_NUM_RESOURCES       11
-
 #ifndef PCI_BUS_NUM_RESOURCES
 #define PCI_BUS_NUM_RESOURCES   16
 #endif
@@ -325,6 +336,15 @@ struct pci_bus {
 #define pci_bus_b(n)    list_entry(n, struct pci_bus, node)
 #define to_pci_bus(n)   container_of(n, struct pci_bus, dev)
 
+#ifdef CONFIG_PCI_MSI
+static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
+{
+        return pci_dev->msi_enabled || pci_dev->msix_enabled;
+}
+#else
+static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
+#endif
+
 /*
  * Error values that may be returned by PCI functions.
  */
@@ -532,7 +552,9 @@ int __must_check pci_bus_add_device(struct pci_dev *dev);
 void pci_read_bridge_bases(struct pci_bus *child);
 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
                                           struct resource *res);
+u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
+u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
 extern void pci_dev_put(struct pci_dev *dev);
 extern void pci_remove_bus(struct pci_bus *b);
@@ -629,6 +651,7 @@ static inline int pci_is_managed(struct pci_dev *pdev)
 
 void pci_disable_device(struct pci_dev *dev);
 void pci_set_master(struct pci_dev *dev);
+void pci_clear_master(struct pci_dev *dev);
 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
 #define HAVE_PCI_SET_MWI
 int __must_check pci_set_mwi(struct pci_dev *dev);
@@ -647,7 +670,7 @@ int pcie_get_readrq(struct pci_dev *dev);
 int pcie_set_readrq(struct pci_dev *dev, int rq);
 int pci_reset_function(struct pci_dev *dev);
 int pci_execute_reset_function(struct pci_dev *dev);
-void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
+void pci_update_resource(struct pci_dev *dev, int resno);
 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
 
@@ -674,6 +697,11 @@ int pci_back_from_sleep(struct pci_dev *dev);
 /* Functions for PCI Hotplug drivers to use */
 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
 
+/* Vital product data routines */
+ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
+ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
+int pci_vpd_truncate(struct pci_dev *dev, size_t size);
+
 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
 void pci_bus_assign_resources(struct pci_bus *bus);
 void pci_bus_size_bridges(struct pci_bus *bus);
@@ -686,10 +714,13 @@ void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
                     int (*)(struct pci_dev *, u8, u8));
 #define HAVE_PCI_REQ_REGIONS    2
 int __must_check pci_request_regions(struct pci_dev *, const char *);
+int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
 void pci_release_regions(struct pci_dev *);
 int __must_check pci_request_region(struct pci_dev *, int, const char *);
+int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
 void pci_release_region(struct pci_dev *, int);
 int pci_request_selected_regions(struct pci_dev *, int, const char *);
+int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
 void pci_release_selected_regions(struct pci_dev *, int);
 
 /* drivers/pci/bus.c */
@@ -779,6 +810,10 @@ static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
 
 static inline void pci_restore_msi_state(struct pci_dev *dev)
 { }
+static inline int pci_msi_enabled(void)
+{
+        return 0;
+}
 #else
 extern int pci_enable_msi(struct pci_dev *dev);
 extern void pci_msi_shutdown(struct pci_dev *dev);
@@ -789,6 +824,16 @@ extern void pci_msix_shutdown(struct pci_dev *dev);
 extern void pci_disable_msix(struct pci_dev *dev);
 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
 extern void pci_restore_msi_state(struct pci_dev *dev);
+extern int pci_msi_enabled(void);
+#endif
+
+#ifndef CONFIG_PCIEASPM
+static inline int pcie_aspm_enabled(void)
+{
+        return 0;
+}
+#else
+extern int pcie_aspm_enabled(void);
 #endif
 
 #ifdef CONFIG_HT_IRQ
@@ -1140,20 +1185,9 @@ static inline void pci_mmcfg_early_init(void) { }
 static inline void pci_mmcfg_late_init(void) { }
 #endif
 
-#ifdef CONFIG_HAS_IOMEM
-static inline void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
-{
-        /*
-         * Make sure the BAR is actually a memory resource, not an IO resource
-         */
-        if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
-                WARN_ON(1);
-                return NULL;
-        }
-        return ioremap_nocache(pci_resource_start(pdev, bar),
-                                     pci_resource_len(pdev, bar));
-}
-#endif
+int pci_ext_cfg_avail(struct pci_dev *dev);
+
+void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
 
 #endif /* __KERNEL__ */
 #endif /* LINUX_PCI_H */
diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h
index a00bd1a0f156..f7cc204fab07 100644
--- a/include/linux/pci_hotplug.h
+++ b/include/linux/pci_hotplug.h
@@ -228,6 +228,8 @@ extern acpi_status acpi_get_hp_params_from_firmware(struct pci_bus *bus,
                                 struct hotplug_params *hpp);
 int acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev, u32 flags);
 int acpi_root_bridge(acpi_handle handle);
+int acpi_pci_check_ejectable(struct pci_bus *pbus, acpi_handle handle);
+int acpi_pci_detect_ejectable(struct pci_bus *pbus);
 #endif
 #endif
 
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index e5effd47ed74..027815b4635e 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -210,6 +210,7 @@
 #define  PCI_CAP_ID_AGP3        0x0E    /* AGP Target PCI-PCI bridge */
 #define  PCI_CAP_ID_EXP         0x10    /* PCI Express */
 #define  PCI_CAP_ID_MSIX        0x11    /* MSI-X */
+#define  PCI_CAP_ID_AF          0x13    /* PCI Advanced Features */
 #define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */
 #define PCI_CAP_FLAGS           2       /* Capability defined flags (16 bits) */
 #define PCI_CAP_SIZEOF          4
@@ -316,6 +317,17 @@
 #define  PCI_CHSWP_EXT          0x40    /* ENUM# status - extraction */
 #define  PCI_CHSWP_INS          0x80    /* ENUM# status - insertion */
 
+/* PCI Advanced Feature registers */
+
+#define PCI_AF_LENGTH           2
+#define PCI_AF_CAP              3
+#define  PCI_AF_CAP_TP          0x01
+#define  PCI_AF_CAP_FLR         0x02
+#define PCI_AF_CTRL             4
+#define  PCI_AF_CTRL_FLR        0x01
+#define PCI_AF_STATUS           5
+#define  PCI_AF_STATUS_TP       0x01
+
 /* PCI-X registers */
 
 #define PCI_X_CMD               2       /* Modes & Features */
@@ -399,20 +411,70 @@
 #define  PCI_EXP_DEVSTA_AUXPD   0x10    /* AUX Power Detected */
 #define  PCI_EXP_DEVSTA_TRPND   0x20    /* Transactions Pending */
 #define PCI_EXP_LNKCAP          12      /* Link Capabilities */
-#define  PCI_EXP_LNKCAP_ASPMS   0xc00   /* ASPM Support */
-#define  PCI_EXP_LNKCAP_L0SEL   0x7000  /* L0s Exit Latency */
-#define  PCI_EXP_LNKCAP_L1EL    0x38000 /* L1 Exit Latency */
-#define  PCI_EXP_LNKCAP_CLKPM   0x40000 /* L1 Clock Power Management */
+#define  PCI_EXP_LNKCAP_SLS     0x0000000f /* Supported Link Speeds */
+#define  PCI_EXP_LNKCAP_MLW     0x000003f0 /* Maximum Link Width */
+#define  PCI_EXP_LNKCAP_ASPMS   0x00000c00 /* ASPM Support */
+#define  PCI_EXP_LNKCAP_L0SEL   0x00007000 /* L0s Exit Latency */
+#define  PCI_EXP_LNKCAP_L1EL    0x00038000 /* L1 Exit Latency */
+#define  PCI_EXP_LNKCAP_CLKPM   0x00040000 /* L1 Clock Power Management */
+#define  PCI_EXP_LNKCAP_SDERC   0x00080000 /* Suprise Down Error Reporting Capable */
+#define  PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
+#define  PCI_EXP_LNKCAP_LBNC    0x00200000 /* Link Bandwidth Notification Capability */
+#define  PCI_EXP_LNKCAP_PN      0xff000000 /* Port Number */
 #define PCI_EXP_LNKCTL          16      /* Link Control */
-#define  PCI_EXP_LNKCTL_RL      0x20    /* Retrain Link */
-#define  PCI_EXP_LNKCTL_CCC     0x40    /* Common Clock COnfiguration */
+#define  PCI_EXP_LNKCTL_ASPMC   0x0003  /* ASPM Control */
+#define  PCI_EXP_LNKCTL_RCB     0x0008  /* Read Completion Boundary */
+#define  PCI_EXP_LNKCTL_LD      0x0010  /* Link Disable */
+#define  PCI_EXP_LNKCTL_RL      0x0020  /* Retrain Link */
+#define  PCI_EXP_LNKCTL_CCC     0x0040  /* Common Clock Configuration */
+#define  PCI_EXP_LNKCTL_ES      0x0080  /* Extended Synch */
 #define  PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
+#define  PCI_EXP_LNKCTL_HAWD    0x0200  /* Hardware Autonomous Width Disable */
+#define  PCI_EXP_LNKCTL_LBMIE   0x0400  /* Link Bandwidth Management Interrupt Enable */
+#define  PCI_EXP_LNKCTL_LABIE   0x0800  /* Lnk Autonomous Bandwidth Interrupt Enable */
 #define PCI_EXP_LNKSTA          18      /* Link Status */
-#define  PCI_EXP_LNKSTA_LT      0x800   /* Link Training */
+#define  PCI_EXP_LNKSTA_CLS     0x000f  /* Current Link Speed */
+#define  PCI_EXP_LNKSTA_NLW     0x03f0  /* Nogotiated Link Width */
+#define  PCI_EXP_LNKSTA_LT      0x0800  /* Link Training */
 #define  PCI_EXP_LNKSTA_SLC     0x1000  /* Slot Clock Configuration */
+#define  PCI_EXP_LNKSTA_DLLLA   0x2000  /* Data Link Layer Link Active */
+#define  PCI_EXP_LNKSTA_LBMS    0x4000  /* Link Bandwidth Management Status */
+#define  PCI_EXP_LNKSTA_LABS    0x8000  /* Link Autonomous Bandwidth Status */
 #define PCI_EXP_SLTCAP          20      /* Slot Capabilities */
+#define  PCI_EXP_SLTCAP_ABP     0x00000001 /* Attention Button Present */
+#define  PCI_EXP_SLTCAP_PCP     0x00000002 /* Power Controller Present */
+#define  PCI_EXP_SLTCAP_MRLSP   0x00000004 /* MRL Sensor Present */
+#define  PCI_EXP_SLTCAP_AIP     0x00000008 /* Attention Indicator Present */
+#define  PCI_EXP_SLTCAP_PIP     0x00000010 /* Power Indicator Present */
+#define  PCI_EXP_SLTCAP_HPS     0x00000020 /* Hot-Plug Surprise */
+#define  PCI_EXP_SLTCAP_HPC     0x00000040 /* Hot-Plug Capable */
+#define  PCI_EXP_SLTCAP_SPLV    0x00007f80 /* Slot Power Limit Value */
+#define  PCI_EXP_SLTCAP_SPLS    0x00018000 /* Slot Power Limit Scale */
+#define  PCI_EXP_SLTCAP_EIP     0x00020000 /* Electromechanical Interlock Present */
+#define  PCI_EXP_SLTCAP_NCCS    0x00040000 /* No Command Completed Support */
+#define  PCI_EXP_SLTCAP_PSN     0xfff80000 /* Physical Slot Number */
 #define PCI_EXP_SLTCTL          24      /* Slot Control */
+#define  PCI_EXP_SLTCTL_ABPE    0x0001  /* Attention Button Pressed Enable */
+#define  PCI_EXP_SLTCTL_PFDE    0x0002  /* Power Fault Detected Enable */
+#define  PCI_EXP_SLTCTL_MRLSCE  0x0004  /* MRL Sensor Changed Enable */
+#define  PCI_EXP_SLTCTL_PDCE    0x0008  /* Presence Detect Changed Enable */
+#define  PCI_EXP_SLTCTL_CCIE    0x0010  /* Command Completed Interrupt Enable */
+#define  PCI_EXP_SLTCTL_HPIE    0x0020  /* Hot-Plug Interrupt Enable */
+#define  PCI_EXP_SLTCTL_AIC     0x00c0  /* Attention Indicator Control */
+#define  PCI_EXP_SLTCTL_PIC     0x0300  /* Power Indicator Control */
+#define  PCI_EXP_SLTCTL_PCC     0x0400  /* Power Controller Control */
+#define  PCI_EXP_SLTCTL_EIC     0x0800  /* Electromechanical Interlock Control */
+#define  PCI_EXP_SLTCTL_DLLSCE  0x1000  /* Data Link Layer State Changed Enable */
 #define PCI_EXP_SLTSTA          26      /* Slot Status */
+#define  PCI_EXP_SLTSTA_ABP     0x0001  /* Attention Button Pressed */
+#define  PCI_EXP_SLTSTA_PFD     0x0002  /* Power Fault Detected */
+#define  PCI_EXP_SLTSTA_MRLSC   0x0004  /* MRL Sensor Changed */
+#define  PCI_EXP_SLTSTA_PDC     0x0008  /* Presence Detect Changed */
+#define  PCI_EXP_SLTSTA_CC      0x0010  /* Command Completed */
+#define  PCI_EXP_SLTSTA_MRLSS   0x0020  /* MRL Sensor State */
+#define  PCI_EXP_SLTSTA_PDS     0x0040  /* Presence Detect State */
+#define  PCI_EXP_SLTSTA_EIS     0x0080  /* Electromechanical Interlock Status */
+#define  PCI_EXP_SLTSTA_DLLSC   0x0100  /* Data Link Layer State Changed */
 #define PCI_EXP_RTCTL           28      /* Root Control */
 #define  PCI_EXP_RTCTL_SECEE    0x01    /* System Error on Correctable Error */
 #define  PCI_EXP_RTCTL_SENFEE   0x02    /* System Error on Non-Fatal Error */