1 files changed, 69 insertions, 7 deletions

diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index e5effd47ed74..027815b4635e 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -210,6 +210,7 @@
 #define  PCI_CAP_ID_AGP3        0x0E    /* AGP Target PCI-PCI bridge */
 #define  PCI_CAP_ID_EXP         0x10    /* PCI Express */
 #define  PCI_CAP_ID_MSIX        0x11    /* MSI-X */
+#define  PCI_CAP_ID_AF          0x13    /* PCI Advanced Features */
 #define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */
 #define PCI_CAP_FLAGS           2       /* Capability defined flags (16 bits) */
 #define PCI_CAP_SIZEOF          4
@@ -316,6 +317,17 @@
 #define  PCI_CHSWP_EXT          0x40    /* ENUM# status - extraction */
 #define  PCI_CHSWP_INS          0x80    /* ENUM# status - insertion */
 
+/* PCI Advanced Feature registers */
+
+#define PCI_AF_LENGTH           2
+#define PCI_AF_CAP              3
+#define  PCI_AF_CAP_TP          0x01
+#define  PCI_AF_CAP_FLR         0x02
+#define PCI_AF_CTRL             4
+#define  PCI_AF_CTRL_FLR        0x01
+#define PCI_AF_STATUS           5
+#define  PCI_AF_STATUS_TP       0x01
+
 /* PCI-X registers */
 
 #define PCI_X_CMD               2       /* Modes & Features */
@@ -399,20 +411,70 @@
 #define  PCI_EXP_DEVSTA_AUXPD   0x10    /* AUX Power Detected */
 #define  PCI_EXP_DEVSTA_TRPND   0x20    /* Transactions Pending */
 #define PCI_EXP_LNKCAP          12      /* Link Capabilities */
-#define  PCI_EXP_LNKCAP_ASPMS   0xc00   /* ASPM Support */
-#define  PCI_EXP_LNKCAP_L0SEL   0x7000  /* L0s Exit Latency */
-#define  PCI_EXP_LNKCAP_L1EL    0x38000 /* L1 Exit Latency */
-#define  PCI_EXP_LNKCAP_CLKPM   0x40000 /* L1 Clock Power Management */
+#define  PCI_EXP_LNKCAP_SLS     0x0000000f /* Supported Link Speeds */
+#define  PCI_EXP_LNKCAP_MLW     0x000003f0 /* Maximum Link Width */
+#define  PCI_EXP_LNKCAP_ASPMS   0x00000c00 /* ASPM Support */
+#define  PCI_EXP_LNKCAP_L0SEL   0x00007000 /* L0s Exit Latency */
+#define  PCI_EXP_LNKCAP_L1EL    0x00038000 /* L1 Exit Latency */
+#define  PCI_EXP_LNKCAP_CLKPM   0x00040000 /* L1 Clock Power Management */
+#define  PCI_EXP_LNKCAP_SDERC   0x00080000 /* Suprise Down Error Reporting Capable */
+#define  PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
+#define  PCI_EXP_LNKCAP_LBNC    0x00200000 /* Link Bandwidth Notification Capability */
+#define  PCI_EXP_LNKCAP_PN      0xff000000 /* Port Number */
 #define PCI_EXP_LNKCTL          16      /* Link Control */
-#define  PCI_EXP_LNKCTL_RL      0x20    /* Retrain Link */
-#define  PCI_EXP_LNKCTL_CCC     0x40    /* Common Clock COnfiguration */
+#define  PCI_EXP_LNKCTL_ASPMC   0x0003  /* ASPM Control */
+#define  PCI_EXP_LNKCTL_RCB     0x0008  /* Read Completion Boundary */
+#define  PCI_EXP_LNKCTL_LD      0x0010  /* Link Disable */
+#define  PCI_EXP_LNKCTL_RL      0x0020  /* Retrain Link */
+#define  PCI_EXP_LNKCTL_CCC     0x0040  /* Common Clock Configuration */
+#define  PCI_EXP_LNKCTL_ES      0x0080  /* Extended Synch */
 #define  PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
+#define  PCI_EXP_LNKCTL_HAWD    0x0200  /* Hardware Autonomous Width Disable */
+#define  PCI_EXP_LNKCTL_LBMIE   0x0400  /* Link Bandwidth Management Interrupt Enable */
+#define  PCI_EXP_LNKCTL_LABIE   0x0800  /* Lnk Autonomous Bandwidth Interrupt Enable */
 #define PCI_EXP_LNKSTA          18      /* Link Status */
-#define  PCI_EXP_LNKSTA_LT      0x800   /* Link Training */
+#define  PCI_EXP_LNKSTA_CLS     0x000f  /* Current Link Speed */
+#define  PCI_EXP_LNKSTA_NLW     0x03f0  /* Nogotiated Link Width */
+#define  PCI_EXP_LNKSTA_LT      0x0800  /* Link Training */
 #define  PCI_EXP_LNKSTA_SLC     0x1000  /* Slot Clock Configuration */
+#define  PCI_EXP_LNKSTA_DLLLA   0x2000  /* Data Link Layer Link Active */
+#define  PCI_EXP_LNKSTA_LBMS    0x4000  /* Link Bandwidth Management Status */
+#define  PCI_EXP_LNKSTA_LABS    0x8000  /* Link Autonomous Bandwidth Status */
 #define PCI_EXP_SLTCAP          20      /* Slot Capabilities */
+#define  PCI_EXP_SLTCAP_ABP     0x00000001 /* Attention Button Present */
+#define  PCI_EXP_SLTCAP_PCP     0x00000002 /* Power Controller Present */
+#define  PCI_EXP_SLTCAP_MRLSP   0x00000004 /* MRL Sensor Present */
+#define  PCI_EXP_SLTCAP_AIP     0x00000008 /* Attention Indicator Present */
+#define  PCI_EXP_SLTCAP_PIP     0x00000010 /* Power Indicator Present */
+#define  PCI_EXP_SLTCAP_HPS     0x00000020 /* Hot-Plug Surprise */
+#define  PCI_EXP_SLTCAP_HPC     0x00000040 /* Hot-Plug Capable */
+#define  PCI_EXP_SLTCAP_SPLV    0x00007f80 /* Slot Power Limit Value */
+#define  PCI_EXP_SLTCAP_SPLS    0x00018000 /* Slot Power Limit Scale */
+#define  PCI_EXP_SLTCAP_EIP     0x00020000 /* Electromechanical Interlock Present */
+#define  PCI_EXP_SLTCAP_NCCS    0x00040000 /* No Command Completed Support */
+#define  PCI_EXP_SLTCAP_PSN     0xfff80000 /* Physical Slot Number */
 #define PCI_EXP_SLTCTL          24      /* Slot Control */
+#define  PCI_EXP_SLTCTL_ABPE    0x0001  /* Attention Button Pressed Enable */
+#define  PCI_EXP_SLTCTL_PFDE    0x0002  /* Power Fault Detected Enable */
+#define  PCI_EXP_SLTCTL_MRLSCE  0x0004  /* MRL Sensor Changed Enable */
+#define  PCI_EXP_SLTCTL_PDCE    0x0008  /* Presence Detect Changed Enable */
+#define  PCI_EXP_SLTCTL_CCIE    0x0010  /* Command Completed Interrupt Enable */
+#define  PCI_EXP_SLTCTL_HPIE    0x0020  /* Hot-Plug Interrupt Enable */
+#define  PCI_EXP_SLTCTL_AIC     0x00c0  /* Attention Indicator Control */
+#define  PCI_EXP_SLTCTL_PIC     0x0300  /* Power Indicator Control */
+#define  PCI_EXP_SLTCTL_PCC     0x0400  /* Power Controller Control */
+#define  PCI_EXP_SLTCTL_EIC     0x0800  /* Electromechanical Interlock Control */
+#define  PCI_EXP_SLTCTL_DLLSCE  0x1000  /* Data Link Layer State Changed Enable */
 #define PCI_EXP_SLTSTA          26      /* Slot Status */
+#define  PCI_EXP_SLTSTA_ABP     0x0001  /* Attention Button Pressed */
+#define  PCI_EXP_SLTSTA_PFD     0x0002  /* Power Fault Detected */
+#define  PCI_EXP_SLTSTA_MRLSC   0x0004  /* MRL Sensor Changed */
+#define  PCI_EXP_SLTSTA_PDC     0x0008  /* Presence Detect Changed */
+#define  PCI_EXP_SLTSTA_CC      0x0010  /* Command Completed */
+#define  PCI_EXP_SLTSTA_MRLSS   0x0020  /* MRL Sensor State */
+#define  PCI_EXP_SLTSTA_PDS     0x0040  /* Presence Detect State */
+#define  PCI_EXP_SLTSTA_EIS     0x0080  /* Electromechanical Interlock Status */
+#define  PCI_EXP_SLTSTA_DLLSC   0x0100  /* Data Link Layer State Changed */
 #define PCI_EXP_RTCTL           28      /* Root Control */
 #define  PCI_EXP_RTCTL_SECEE    0x01    /* System Error on Correctable Error */
 #define  PCI_EXP_RTCTL_SENFEE   0x02    /* System Error on Non-Fatal Error */