diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-11-09 17:46:36 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-11-09 17:46:36 -0500 |
| commit | b1f368b58b3c8095de4cff9eeb69babffab4e3d3 (patch) | |
| tree | efd28998e71ad2a5433ca79e858a2cfc71f30a2d /include | |
| parent | a3157809772c4a5256ef68a4d5b21ea4ecc80ad4 (diff) | |
| parent | 92c9e0c780e61f821ab8a08f0d4d4fd33ba1197c (diff) | |
Merge tag 'armsoc-for-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Another quiet week:
- a fix to silence edma probe error on non-supported platforms from
Arnd
- a fix to enable the PL clock for Parallella, to make mainline
usable with the SDK.
- a somewhat verbose fix for the PLL clock tree on VF610
- enabling of SD/MMC on one of the VF610-based boards (for testing)
- a fix for i.MX where CONFIG_SPI used to be implicitly enabled and
now needs to be added to the defconfig instead
- another maintainer added for bcm2835: Lee Jones"
* tag 'armsoc-for-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: dts: zynq: Enable PL clocks for Parallella
dma: edma: move device registration to platform code
ARM: dts: vf610: add SD node to cosmic dts
MAINTAINERS: update bcm2835 entry
ARM: imx: Fix the removal of CONFIG_SPI option
ARM: imx: clk-vf610: define PLL's clock tree
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/vf610-clock.h | 39 |
1 files changed, 31 insertions, 8 deletions
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h index d6b56b21539b..801c0ac50c47 100644 --- a/include/dt-bindings/clock/vf610-clock.h +++ b/include/dt-bindings/clock/vf610-clock.h | |||
| @@ -21,24 +21,24 @@ | |||
| 21 | #define VF610_CLK_FASK_CLK_SEL 8 | 21 | #define VF610_CLK_FASK_CLK_SEL 8 |
| 22 | #define VF610_CLK_AUDIO_EXT 9 | 22 | #define VF610_CLK_AUDIO_EXT 9 |
| 23 | #define VF610_CLK_ENET_EXT 10 | 23 | #define VF610_CLK_ENET_EXT 10 |
| 24 | #define VF610_CLK_PLL1_MAIN 11 | 24 | #define VF610_CLK_PLL1_SYS 11 |
| 25 | #define VF610_CLK_PLL1_PFD1 12 | 25 | #define VF610_CLK_PLL1_PFD1 12 |
| 26 | #define VF610_CLK_PLL1_PFD2 13 | 26 | #define VF610_CLK_PLL1_PFD2 13 |
| 27 | #define VF610_CLK_PLL1_PFD3 14 | 27 | #define VF610_CLK_PLL1_PFD3 14 |
| 28 | #define VF610_CLK_PLL1_PFD4 15 | 28 | #define VF610_CLK_PLL1_PFD4 15 |
| 29 | #define VF610_CLK_PLL2_MAIN 16 | 29 | #define VF610_CLK_PLL2_BUS 16 |
| 30 | #define VF610_CLK_PLL2_PFD1 17 | 30 | #define VF610_CLK_PLL2_PFD1 17 |
| 31 | #define VF610_CLK_PLL2_PFD2 18 | 31 | #define VF610_CLK_PLL2_PFD2 18 |
| 32 | #define VF610_CLK_PLL2_PFD3 19 | 32 | #define VF610_CLK_PLL2_PFD3 19 |
| 33 | #define VF610_CLK_PLL2_PFD4 20 | 33 | #define VF610_CLK_PLL2_PFD4 20 |
| 34 | #define VF610_CLK_PLL3_MAIN 21 | 34 | #define VF610_CLK_PLL3_USB_OTG 21 |
| 35 | #define VF610_CLK_PLL3_PFD1 22 | 35 | #define VF610_CLK_PLL3_PFD1 22 |
| 36 | #define VF610_CLK_PLL3_PFD2 23 | 36 | #define VF610_CLK_PLL3_PFD2 23 |
| 37 | #define VF610_CLK_PLL3_PFD3 24 | 37 | #define VF610_CLK_PLL3_PFD3 24 |
| 38 | #define VF610_CLK_PLL3_PFD4 25 | 38 | #define VF610_CLK_PLL3_PFD4 25 |
| 39 | #define VF610_CLK_PLL4_MAIN 26 | 39 | #define VF610_CLK_PLL4_AUDIO 26 |
| 40 | #define VF610_CLK_PLL5_MAIN 27 | 40 | #define VF610_CLK_PLL5_ENET 27 |
| 41 | #define VF610_CLK_PLL6_MAIN 28 | 41 | #define VF610_CLK_PLL6_VIDEO 28 |
| 42 | #define VF610_CLK_PLL3_MAIN_DIV 29 | 42 | #define VF610_CLK_PLL3_MAIN_DIV 29 |
| 43 | #define VF610_CLK_PLL4_MAIN_DIV 30 | 43 | #define VF610_CLK_PLL4_MAIN_DIV 30 |
| 44 | #define VF610_CLK_PLL6_MAIN_DIV 31 | 44 | #define VF610_CLK_PLL6_MAIN_DIV 31 |
| @@ -166,9 +166,32 @@ | |||
| 166 | #define VF610_CLK_DMAMUX3 153 | 166 | #define VF610_CLK_DMAMUX3 153 |
| 167 | #define VF610_CLK_FLEXCAN0_EN 154 | 167 | #define VF610_CLK_FLEXCAN0_EN 154 |
| 168 | #define VF610_CLK_FLEXCAN1_EN 155 | 168 | #define VF610_CLK_FLEXCAN1_EN 155 |
| 169 | #define VF610_CLK_PLL7_MAIN 156 | 169 | #define VF610_CLK_PLL7_USB_HOST 156 |
| 170 | #define VF610_CLK_USBPHY0 157 | 170 | #define VF610_CLK_USBPHY0 157 |
| 171 | #define VF610_CLK_USBPHY1 158 | 171 | #define VF610_CLK_USBPHY1 158 |
| 172 | #define VF610_CLK_END 159 | 172 | #define VF610_CLK_LVDS1_IN 159 |
| 173 | #define VF610_CLK_ANACLK1 160 | ||
| 174 | #define VF610_CLK_PLL1_BYPASS_SRC 161 | ||
| 175 | #define VF610_CLK_PLL2_BYPASS_SRC 162 | ||
| 176 | #define VF610_CLK_PLL3_BYPASS_SRC 163 | ||
| 177 | #define VF610_CLK_PLL4_BYPASS_SRC 164 | ||
| 178 | #define VF610_CLK_PLL5_BYPASS_SRC 165 | ||
| 179 | #define VF610_CLK_PLL6_BYPASS_SRC 166 | ||
| 180 | #define VF610_CLK_PLL7_BYPASS_SRC 167 | ||
| 181 | #define VF610_CLK_PLL1 168 | ||
| 182 | #define VF610_CLK_PLL2 169 | ||
| 183 | #define VF610_CLK_PLL3 170 | ||
| 184 | #define VF610_CLK_PLL4 171 | ||
| 185 | #define VF610_CLK_PLL5 172 | ||
| 186 | #define VF610_CLK_PLL6 173 | ||
| 187 | #define VF610_CLK_PLL7 174 | ||
| 188 | #define VF610_PLL1_BYPASS 175 | ||
| 189 | #define VF610_PLL2_BYPASS 176 | ||
| 190 | #define VF610_PLL3_BYPASS 177 | ||
| 191 | #define VF610_PLL4_BYPASS 178 | ||
| 192 | #define VF610_PLL5_BYPASS 179 | ||
| 193 | #define VF610_PLL6_BYPASS 180 | ||
| 194 | #define VF610_PLL7_BYPASS 181 | ||
| 195 | #define VF610_CLK_END 182 | ||
| 173 | 196 | ||
| 174 | #endif /* __DT_BINDINGS_CLOCK_VF610_H */ | 197 | #endif /* __DT_BINDINGS_CLOCK_VF610_H */ |
