Merge tag 'qcom-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into clk-next-msm

qcom clock changes for 3.17

These patches add support for a handful of Qualcomm's SoC clock
controllers: APQ8084 gcc and mmcc, IPQ8064 gcc, and APQ8064.
There's also a small collection of bug fixes that aren't critical
-rc worthy regressions because the consumer drivers aren't present
or using the buggy clocks and one optimization for HDMI.

10 files changed, 1175 insertions, 0 deletions

diff --git a/include/dt-bindings/clock/qcom,gcc-apq8084.h b/include/dt-bindings/clock/qcom,gcc-apq8084.h
new file mode 100644
index 000000000000..2c0da566c46a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-apq8084.h
@@ -0,0 +1,351 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H
+#define _DT_BINDINGS_CLK_APQ_GCC_8084_H
+
+#define GPLL0                                           0
+#define GPLL0_VOTE                                      1
+#define GPLL1                                           2
+#define GPLL1_VOTE                                      3
+#define GPLL2                                           4
+#define GPLL2_VOTE                                      5
+#define GPLL3                                           6
+#define GPLL3_VOTE                                      7
+#define GPLL4                                           8
+#define GPLL4_VOTE                                      9
+#define CONFIG_NOC_CLK_SRC                              10
+#define PERIPH_NOC_CLK_SRC                              11
+#define SYSTEM_NOC_CLK_SRC                              12
+#define BLSP_UART_SIM_CLK_SRC                           13
+#define QDSS_TSCTR_CLK_SRC                              14
+#define UFS_AXI_CLK_SRC                                 15
+#define RPM_CLK_SRC                                     16
+#define KPSS_AHB_CLK_SRC                                17
+#define QDSS_AT_CLK_SRC                                 18
+#define BIMC_DDR_CLK_SRC                                19
+#define USB30_MASTER_CLK_SRC                            20
+#define USB30_SEC_MASTER_CLK_SRC                        21
+#define USB_HSIC_AHB_CLK_SRC                            22
+#define MMSS_BIMC_GFX_CLK_SRC                           23
+#define QDSS_STM_CLK_SRC                                24
+#define ACC_CLK_SRC                                     25
+#define SEC_CTRL_CLK_SRC                                26
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC                     27
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC                     28
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC                     29
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC                     30
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC                     31
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC                     32
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC                     33
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC                     34
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC                     35
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC                     36
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC                     37
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC                     38
+#define BLSP1_UART1_APPS_CLK_SRC                        39
+#define BLSP1_UART2_APPS_CLK_SRC                        40
+#define BLSP1_UART3_APPS_CLK_SRC                        41
+#define BLSP1_UART4_APPS_CLK_SRC                        42
+#define BLSP1_UART5_APPS_CLK_SRC                        43
+#define BLSP1_UART6_APPS_CLK_SRC                        44
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC                     45
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC                     46
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC                     47
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC                     48
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC                     49
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC                     50
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC                     51
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC                     52
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC                     53
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC                     54
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC                     55
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC                     56
+#define BLSP2_UART1_APPS_CLK_SRC                        57
+#define BLSP2_UART2_APPS_CLK_SRC                        58
+#define BLSP2_UART3_APPS_CLK_SRC                        59
+#define BLSP2_UART4_APPS_CLK_SRC                        60
+#define BLSP2_UART5_APPS_CLK_SRC                        61
+#define BLSP2_UART6_APPS_CLK_SRC                        62
+#define CE1_CLK_SRC                                     63
+#define CE2_CLK_SRC                                     64
+#define CE3_CLK_SRC                                     65
+#define GP1_CLK_SRC                                     66
+#define GP2_CLK_SRC                                     67
+#define GP3_CLK_SRC                                     68
+#define PDM2_CLK_SRC                                    69
+#define QDSS_TRACECLKIN_CLK_SRC                         70
+#define RBCPR_CLK_SRC                                   71
+#define SATA_ASIC0_CLK_SRC                              72
+#define SATA_PMALIVE_CLK_SRC                            73
+#define SATA_RX_CLK_SRC                                 74
+#define SATA_RX_OOB_CLK_SRC                             75
+#define SDCC1_APPS_CLK_SRC                              76
+#define SDCC2_APPS_CLK_SRC                              77
+#define SDCC3_APPS_CLK_SRC                              78
+#define SDCC4_APPS_CLK_SRC                              79
+#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK                   80
+#define SPMI_AHB_CLK_SRC                                81
+#define SPMI_SER_CLK_SRC                                82
+#define TSIF_REF_CLK_SRC                                83
+#define USB30_MOCK_UTMI_CLK_SRC                         84
+#define USB30_SEC_MOCK_UTMI_CLK_SRC                     85
+#define USB_HS_SYSTEM_CLK_SRC                           86
+#define USB_HSIC_CLK_SRC                                87
+#define USB_HSIC_IO_CAL_CLK_SRC                         88
+#define USB_HSIC_MOCK_UTMI_CLK_SRC                      89
+#define USB_HSIC_SYSTEM_CLK_SRC                         90
+#define GCC_BAM_DMA_AHB_CLK                             91
+#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK               92
+#define DDR_CLK_SRC                                     93
+#define GCC_BIMC_CFG_AHB_CLK                            94
+#define GCC_BIMC_CLK                                    95
+#define GCC_BIMC_KPSS_AXI_CLK                           96
+#define GCC_BIMC_SLEEP_CLK                              97
+#define GCC_BIMC_SYSNOC_AXI_CLK                         98
+#define GCC_BIMC_XO_CLK                                 99
+#define GCC_BLSP1_AHB_CLK                               100
+#define GCC_BLSP1_SLEEP_CLK                             101
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK                     102
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK                     103
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK                     104
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK                     105
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK                     106
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK                     107
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK                     108
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK                     109
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK                     110
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK                     111
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK                     112
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK                     113
+#define GCC_BLSP1_UART1_APPS_CLK                        114
+#define GCC_BLSP1_UART1_SIM_CLK                         115
+#define GCC_BLSP1_UART2_APPS_CLK                        116
+#define GCC_BLSP1_UART2_SIM_CLK                         117
+#define GCC_BLSP1_UART3_APPS_CLK                        118
+#define GCC_BLSP1_UART3_SIM_CLK                         119
+#define GCC_BLSP1_UART4_APPS_CLK                        120
+#define GCC_BLSP1_UART4_SIM_CLK                         121
+#define GCC_BLSP1_UART5_APPS_CLK                        122
+#define GCC_BLSP1_UART5_SIM_CLK                         123
+#define GCC_BLSP1_UART6_APPS_CLK                        124
+#define GCC_BLSP1_UART6_SIM_CLK                         125
+#define GCC_BLSP2_AHB_CLK                               126
+#define GCC_BLSP2_SLEEP_CLK                             127
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK                     128
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK                     129
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK                     130
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK                     131
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK                     132
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK                     133
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK                     134
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK                     135
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK                     136
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK                     137
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK                     138
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK                     139
+#define GCC_BLSP2_UART1_APPS_CLK                        140
+#define GCC_BLSP2_UART1_SIM_CLK                         141
+#define GCC_BLSP2_UART2_APPS_CLK                        142
+#define GCC_BLSP2_UART2_SIM_CLK                         143
+#define GCC_BLSP2_UART3_APPS_CLK                        144
+#define GCC_BLSP2_UART3_SIM_CLK                         145
+#define GCC_BLSP2_UART4_APPS_CLK                        146
+#define GCC_BLSP2_UART4_SIM_CLK                         147
+#define GCC_BLSP2_UART5_APPS_CLK                        148
+#define GCC_BLSP2_UART5_SIM_CLK                         149
+#define GCC_BLSP2_UART6_APPS_CLK                        150
+#define GCC_BLSP2_UART6_SIM_CLK                         151
+#define GCC_BOOT_ROM_AHB_CLK                            152
+#define GCC_CE1_AHB_CLK                                 153
+#define GCC_CE1_AXI_CLK                                 154
+#define GCC_CE1_CLK                                     155
+#define GCC_CE2_AHB_CLK                                 156
+#define GCC_CE2_AXI_CLK                                 157
+#define GCC_CE2_CLK                                     158
+#define GCC_CE3_AHB_CLK                                 159
+#define GCC_CE3_AXI_CLK                                 160
+#define GCC_CE3_CLK                                     161
+#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK                   162
+#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK                   163
+#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK                   164
+#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK                   165
+#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK                   166
+#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK                   167
+#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK                   168
+#define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK                   169
+#define GCC_CFG_NOC_AHB_CLK                             170
+#define GCC_CFG_NOC_DDR_CFG_CLK                         171
+#define GCC_CFG_NOC_RPM_AHB_CLK                         172
+#define GCC_COPSS_SMMU_AHB_CLK                          173
+#define GCC_COPSS_SMMU_AXI_CLK                          174
+#define GCC_DCD_XO_CLK                                  175
+#define GCC_BIMC_DDR_CH0_CLK                            176
+#define GCC_BIMC_DDR_CH1_CLK                            177
+#define GCC_BIMC_DDR_CPLL0_CLK                          178
+#define GCC_BIMC_DDR_CPLL1_CLK                          179
+#define GCC_BIMC_GFX_CLK                                180
+#define GCC_DDR_DIM_CFG_CLK                             181
+#define GCC_DDR_DIM_SLEEP_CLK                           182
+#define GCC_DEHR_CLK                                    183
+#define GCC_AHB_CLK                                     184
+#define GCC_IM_SLEEP_CLK                                185
+#define GCC_XO_CLK                                      186
+#define GCC_XO_DIV4_CLK                                 187
+#define GCC_GP1_CLK                                     188
+#define GCC_GP2_CLK                                     189
+#define GCC_GP3_CLK                                     190
+#define GCC_IMEM_AXI_CLK                                191
+#define GCC_IMEM_CFG_AHB_CLK                            192
+#define GCC_KPSS_AHB_CLK                                193
+#define GCC_KPSS_AXI_CLK                                194
+#define GCC_LPASS_MPORT_AXI_CLK                         195
+#define GCC_LPASS_Q6_AXI_CLK                            196
+#define GCC_LPASS_SWAY_CLK                              197
+#define GCC_MMSS_BIMC_GFX_CLK                           198
+#define GCC_MMSS_NOC_AT_CLK                             199
+#define GCC_MMSS_NOC_CFG_AHB_CLK                        200
+#define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK              201
+#define GCC_OCMEM_NOC_CFG_AHB_CLK                       202
+#define GCC_OCMEM_SYS_NOC_AXI_CLK                       203
+#define GCC_MPM_AHB_CLK                                 204
+#define GCC_MSG_RAM_AHB_CLK                             205
+#define GCC_NOC_CONF_XPU_AHB_CLK                        206
+#define GCC_PDM2_CLK                                    207
+#define GCC_PDM_AHB_CLK                                 208
+#define GCC_PDM_XO4_CLK                                 209
+#define GCC_PERIPH_NOC_AHB_CLK                          210
+#define GCC_PERIPH_NOC_AT_CLK                           211
+#define GCC_PERIPH_NOC_CFG_AHB_CLK                      212
+#define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK                 213
+#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK                  214
+#define GCC_PERIPH_XPU_AHB_CLK                          215
+#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK                   216
+#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK                   217
+#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK                   218
+#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK                   219
+#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK                   220
+#define GCC_PRNG_AHB_CLK                                221
+#define GCC_QDSS_AT_CLK                                 222
+#define GCC_QDSS_CFG_AHB_CLK                            223
+#define GCC_QDSS_DAP_AHB_CLK                            224
+#define GCC_QDSS_DAP_CLK                                225
+#define GCC_QDSS_ETR_USB_CLK                            226
+#define GCC_QDSS_STM_CLK                                227
+#define GCC_QDSS_TRACECLKIN_CLK                         228
+#define GCC_QDSS_TSCTR_DIV16_CLK                        229
+#define GCC_QDSS_TSCTR_DIV2_CLK                         230
+#define GCC_QDSS_TSCTR_DIV3_CLK                         231
+#define GCC_QDSS_TSCTR_DIV4_CLK                         232
+#define GCC_QDSS_TSCTR_DIV8_CLK                         233
+#define GCC_QDSS_RBCPR_XPU_AHB_CLK                      234
+#define GCC_RBCPR_AHB_CLK                               235
+#define GCC_RBCPR_CLK                                   236
+#define GCC_RPM_BUS_AHB_CLK                             237
+#define GCC_RPM_PROC_HCLK                               238
+#define GCC_RPM_SLEEP_CLK                               239
+#define GCC_RPM_TIMER_CLK                               240
+#define GCC_SATA_ASIC0_CLK                              241
+#define GCC_SATA_AXI_CLK                                242
+#define GCC_SATA_CFG_AHB_CLK                            243
+#define GCC_SATA_PMALIVE_CLK                            244
+#define GCC_SATA_RX_CLK                                 245
+#define GCC_SATA_RX_OOB_CLK                             246
+#define GCC_SDCC1_AHB_CLK                               247
+#define GCC_SDCC1_APPS_CLK                              248
+#define GCC_SDCC1_CDCCAL_FF_CLK                         249
+#define GCC_SDCC1_CDCCAL_SLEEP_CLK                      250
+#define GCC_SDCC2_AHB_CLK                               251
+#define GCC_SDCC2_APPS_CLK                              252
+#define GCC_SDCC2_INACTIVITY_TIMERS_CLK                 253
+#define GCC_SDCC3_AHB_CLK                               254
+#define GCC_SDCC3_APPS_CLK                              255
+#define GCC_SDCC3_INACTIVITY_TIMERS_CLK                 256
+#define GCC_SDCC4_AHB_CLK                               257
+#define GCC_SDCC4_APPS_CLK                              258
+#define GCC_SDCC4_INACTIVITY_TIMERS_CLK                 259
+#define GCC_SEC_CTRL_ACC_CLK                            260
+#define GCC_SEC_CTRL_AHB_CLK                            261
+#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK                 262
+#define GCC_SEC_CTRL_CLK                                263
+#define GCC_SEC_CTRL_SENSE_CLK                          264
+#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK                   265
+#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK                   266
+#define GCC_SPDM_BIMC_CY_CLK                            267
+#define GCC_SPDM_CFG_AHB_CLK                            268
+#define GCC_SPDM_DEBUG_CY_CLK                           269
+#define GCC_SPDM_FF_CLK                                 270
+#define GCC_SPDM_MSTR_AHB_CLK                           271
+#define GCC_SPDM_PNOC_CY_CLK                            272
+#define GCC_SPDM_RPM_CY_CLK                             273
+#define GCC_SPDM_SNOC_CY_CLK                            274
+#define GCC_SPMI_AHB_CLK                                275
+#define GCC_SPMI_CNOC_AHB_CLK                           276
+#define GCC_SPMI_SER_CLK                                277
+#define GCC_SPSS_AHB_CLK                                278
+#define GCC_SNOC_CNOC_AHB_CLK                           279
+#define GCC_SNOC_PNOC_AHB_CLK                           280
+#define GCC_SYS_NOC_AT_CLK                              281
+#define GCC_SYS_NOC_AXI_CLK                             282
+#define GCC_SYS_NOC_KPSS_AHB_CLK                        283
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK                    284
+#define GCC_SYS_NOC_UFS_AXI_CLK                         285
+#define GCC_SYS_NOC_USB3_AXI_CLK                        286
+#define GCC_SYS_NOC_USB3_SEC_AXI_CLK                    287
+#define GCC_TCSR_AHB_CLK                                288
+#define GCC_TLMM_AHB_CLK                                289
+#define GCC_TLMM_CLK                                    290
+#define GCC_TSIF_AHB_CLK                                291
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK                  292
+#define GCC_TSIF_REF_CLK                                293
+#define GCC_UFS_AHB_CLK                                 294
+#define GCC_UFS_AXI_CLK                                 295
+#define GCC_UFS_RX_CFG_CLK                              296
+#define GCC_UFS_RX_SYMBOL_0_CLK                         297
+#define GCC_UFS_RX_SYMBOL_1_CLK                         298
+#define GCC_UFS_TX_CFG_CLK                              299
+#define GCC_UFS_TX_SYMBOL_0_CLK                         300
+#define GCC_UFS_TX_SYMBOL_1_CLK                         301
+#define GCC_USB2A_PHY_SLEEP_CLK                         302
+#define GCC_USB2B_PHY_SLEEP_CLK                         303
+#define GCC_USB30_MASTER_CLK                            304
+#define GCC_USB30_MOCK_UTMI_CLK                         305
+#define GCC_USB30_SLEEP_CLK                             306
+#define GCC_USB30_SEC_MASTER_CLK                        307
+#define GCC_USB30_SEC_MOCK_UTMI_CLK                     308
+#define GCC_USB30_SEC_SLEEP_CLK                         309
+#define GCC_USB_HS_AHB_CLK                              310
+#define GCC_USB_HS_INACTIVITY_TIMERS_CLK                311
+#define GCC_USB_HS_SYSTEM_CLK                           312
+#define GCC_USB_HSIC_AHB_CLK                            313
+#define GCC_USB_HSIC_CLK                                314
+#define GCC_USB_HSIC_IO_CAL_CLK                         315
+#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK                   316
+#define GCC_USB_HSIC_MOCK_UTMI_CLK                      317
+#define GCC_USB_HSIC_SYSTEM_CLK                         318
+#define PCIE_0_AUX_CLK_SRC                              319
+#define PCIE_0_PIPE_CLK_SRC                             320
+#define PCIE_1_AUX_CLK_SRC                              321
+#define PCIE_1_PIPE_CLK_SRC                             322
+#define GCC_PCIE_0_AUX_CLK                              323
+#define GCC_PCIE_0_CFG_AHB_CLK                          324
+#define GCC_PCIE_0_MSTR_AXI_CLK                         325
+#define GCC_PCIE_0_PIPE_CLK                             326
+#define GCC_PCIE_0_SLV_AXI_CLK                          327
+#define GCC_PCIE_1_AUX_CLK                              328
+#define GCC_PCIE_1_CFG_AHB_CLK                          329
+#define GCC_PCIE_1_MSTR_AXI_CLK                         330
+#define GCC_PCIE_1_PIPE_CLK                             331
+#define GCC_PCIE_1_SLV_AXI_CLK                          332
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
new file mode 100644
index 000000000000..b857cadb0bd4
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -0,0 +1,293 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H
+#define _DT_BINDINGS_CLK_GCC_IPQ806X_H
+
+#define AFAB_CLK_SRC                            0
+#define QDSS_STM_CLK                            1
+#define SCSS_A_CLK                              2
+#define SCSS_H_CLK                              3
+#define AFAB_CORE_CLK                           4
+#define SCSS_XO_SRC_CLK                         5
+#define AFAB_EBI1_CH0_A_CLK                     6
+#define AFAB_EBI1_CH1_A_CLK                     7
+#define AFAB_AXI_S0_FCLK                        8
+#define AFAB_AXI_S1_FCLK                        9
+#define AFAB_AXI_S2_FCLK                        10
+#define AFAB_AXI_S3_FCLK                        11
+#define AFAB_AXI_S4_FCLK                        12
+#define SFAB_CORE_CLK                           13
+#define SFAB_AXI_S0_FCLK                        14
+#define SFAB_AXI_S1_FCLK                        15
+#define SFAB_AXI_S2_FCLK                        16
+#define SFAB_AXI_S3_FCLK                        17
+#define SFAB_AXI_S4_FCLK                        18
+#define SFAB_AXI_S5_FCLK                        19
+#define SFAB_AHB_S0_FCLK                        20
+#define SFAB_AHB_S1_FCLK                        21
+#define SFAB_AHB_S2_FCLK                        22
+#define SFAB_AHB_S3_FCLK                        23
+#define SFAB_AHB_S4_FCLK                        24
+#define SFAB_AHB_S5_FCLK                        25
+#define SFAB_AHB_S6_FCLK                        26
+#define SFAB_AHB_S7_FCLK                        27
+#define QDSS_AT_CLK_SRC                         28
+#define QDSS_AT_CLK                             29
+#define QDSS_TRACECLKIN_CLK_SRC                 30
+#define QDSS_TRACECLKIN_CLK                     31
+#define QDSS_TSCTR_CLK_SRC                      32
+#define QDSS_TSCTR_CLK                          33
+#define SFAB_ADM0_M0_A_CLK                      34
+#define SFAB_ADM0_M1_A_CLK                      35
+#define SFAB_ADM0_M2_H_CLK                      36
+#define ADM0_CLK                                37
+#define ADM0_PBUS_CLK                           38
+#define IMEM0_A_CLK                             39
+#define QDSS_H_CLK                              40
+#define PCIE_A_CLK                              41
+#define PCIE_AUX_CLK                            42
+#define PCIE_H_CLK                              43
+#define PCIE_PHY_CLK                            44
+#define SFAB_CLK_SRC                            45
+#define SFAB_LPASS_Q6_A_CLK                     46
+#define SFAB_AFAB_M_A_CLK                       47
+#define AFAB_SFAB_M0_A_CLK                      48
+#define AFAB_SFAB_M1_A_CLK                      49
+#define SFAB_SATA_S_H_CLK                       50
+#define DFAB_CLK_SRC                            51
+#define DFAB_CLK                                52
+#define SFAB_DFAB_M_A_CLK                       53
+#define DFAB_SFAB_M_A_CLK                       54
+#define DFAB_SWAY0_H_CLK                        55
+#define DFAB_SWAY1_H_CLK                        56
+#define DFAB_ARB0_H_CLK                         57
+#define DFAB_ARB1_H_CLK                         58
+#define PPSS_H_CLK                              59
+#define PPSS_PROC_CLK                           60
+#define PPSS_TIMER0_CLK                         61
+#define PPSS_TIMER1_CLK                         62
+#define PMEM_A_CLK                              63
+#define DMA_BAM_H_CLK                           64
+#define SIC_H_CLK                               65
+#define SPS_TIC_H_CLK                           66
+#define CFPB_2X_CLK_SRC                         67
+#define CFPB_CLK                                68
+#define CFPB0_H_CLK                             69
+#define CFPB1_H_CLK                             70
+#define CFPB2_H_CLK                             71
+#define SFAB_CFPB_M_H_CLK                       72
+#define CFPB_MASTER_H_CLK                       73
+#define SFAB_CFPB_S_H_CLK                       74
+#define CFPB_SPLITTER_H_CLK                     75
+#define TSIF_H_CLK                              76
+#define TSIF_INACTIVITY_TIMERS_CLK              77
+#define TSIF_REF_SRC                            78
+#define TSIF_REF_CLK                            79
+#define CE1_H_CLK                               80
+#define CE1_CORE_CLK                            81
+#define CE1_SLEEP_CLK                           82
+#define CE2_H_CLK                               83
+#define CE2_CORE_CLK                            84
+#define SFPB_H_CLK_SRC                          85
+#define SFPB_H_CLK                              86
+#define SFAB_SFPB_M_H_CLK                       87
+#define SFAB_SFPB_S_H_CLK                       88
+#define RPM_PROC_CLK                            89
+#define RPM_BUS_H_CLK                           90
+#define RPM_SLEEP_CLK                           91
+#define RPM_TIMER_CLK                           92
+#define RPM_MSG_RAM_H_CLK                       93
+#define PMIC_ARB0_H_CLK                         94
+#define PMIC_ARB1_H_CLK                         95
+#define PMIC_SSBI2_SRC                          96
+#define PMIC_SSBI2_CLK                          97
+#define SDC1_H_CLK                              98
+#define SDC2_H_CLK                              99
+#define SDC3_H_CLK                              100
+#define SDC4_H_CLK                              101
+#define SDC1_SRC                                102
+#define SDC1_CLK                                103
+#define SDC2_SRC                                104
+#define SDC2_CLK                                105
+#define SDC3_SRC                                106
+#define SDC3_CLK                                107
+#define SDC4_SRC                                108
+#define SDC4_CLK                                109
+#define USB_HS1_H_CLK                           110
+#define USB_HS1_XCVR_SRC                        111
+#define USB_HS1_XCVR_CLK                        112
+#define USB_HSIC_H_CLK                          113
+#define USB_HSIC_XCVR_SRC                       114
+#define USB_HSIC_XCVR_CLK                       115
+#define USB_HSIC_SYSTEM_CLK_SRC                 116
+#define USB_HSIC_SYSTEM_CLK                     117
+#define CFPB0_C0_H_CLK                          118
+#define CFPB0_D0_H_CLK                          119
+#define CFPB0_C1_H_CLK                          120
+#define CFPB0_D1_H_CLK                          121
+#define USB_FS1_H_CLK                           122
+#define USB_FS1_XCVR_SRC                        123
+#define USB_FS1_XCVR_CLK                        124
+#define USB_FS1_SYSTEM_CLK                      125
+#define GSBI_COMMON_SIM_SRC                     126
+#define GSBI1_H_CLK                             127
+#define GSBI2_H_CLK                             128
+#define GSBI3_H_CLK                             129
+#define GSBI4_H_CLK                             130
+#define GSBI5_H_CLK                             131
+#define GSBI6_H_CLK                             132
+#define GSBI7_H_CLK                             133
+#define GSBI1_QUP_SRC                           134
+#define GSBI1_QUP_CLK                           135
+#define GSBI2_QUP_SRC                           136
+#define GSBI2_QUP_CLK                           137
+#define GSBI3_QUP_SRC                           138
+#define GSBI3_QUP_CLK                           139
+#define GSBI4_QUP_SRC                           140
+#define GSBI4_QUP_CLK                           141
+#define GSBI5_QUP_SRC                           142
+#define GSBI5_QUP_CLK                           143
+#define GSBI6_QUP_SRC                           144
+#define GSBI6_QUP_CLK                           145
+#define GSBI7_QUP_SRC                           146
+#define GSBI7_QUP_CLK                           147
+#define GSBI1_UART_SRC                          148
+#define GSBI1_UART_CLK                          149
+#define GSBI2_UART_SRC                          150
+#define GSBI2_UART_CLK                          151
+#define GSBI3_UART_SRC                          152
+#define GSBI3_UART_CLK                          153
+#define GSBI4_UART_SRC                          154
+#define GSBI4_UART_CLK                          155
+#define GSBI5_UART_SRC                          156
+#define GSBI5_UART_CLK                          157
+#define GSBI6_UART_SRC                          158
+#define GSBI6_UART_CLK                          159
+#define GSBI7_UART_SRC                          160
+#define GSBI7_UART_CLK                          161
+#define GSBI1_SIM_CLK                           162
+#define GSBI2_SIM_CLK                           163
+#define GSBI3_SIM_CLK                           164
+#define GSBI4_SIM_CLK                           165
+#define GSBI5_SIM_CLK                           166
+#define GSBI6_SIM_CLK                           167
+#define GSBI7_SIM_CLK                           168
+#define USB_HSIC_HSIC_CLK_SRC                   169
+#define USB_HSIC_HSIC_CLK                       170
+#define USB_HSIC_HSIO_CAL_CLK                   171
+#define SPDM_CFG_H_CLK                          172
+#define SPDM_MSTR_H_CLK                         173
+#define SPDM_FF_CLK_SRC                         174
+#define SPDM_FF_CLK                             175
+#define SEC_CTRL_CLK                            176
+#define SEC_CTRL_ACC_CLK_SRC                    177
+#define SEC_CTRL_ACC_CLK                        178
+#define TLMM_H_CLK                              179
+#define TLMM_CLK                                180
+#define SATA_H_CLK                              181
+#define SATA_CLK_SRC                            182
+#define SATA_RXOOB_CLK                          183
+#define SATA_PMALIVE_CLK                        184
+#define SATA_PHY_REF_CLK                        185
+#define SATA_A_CLK                              186
+#define SATA_PHY_CFG_CLK                        187
+#define TSSC_CLK_SRC                            188
+#define TSSC_CLK                                189
+#define PDM_SRC                                 190
+#define PDM_CLK                                 191
+#define GP0_SRC                                 192
+#define GP0_CLK                                 193
+#define GP1_SRC                                 194
+#define GP1_CLK                                 195
+#define GP2_SRC                                 196
+#define GP2_CLK                                 197
+#define MPM_CLK                                 198
+#define EBI1_CLK_SRC                            199
+#define EBI1_CH0_CLK                            200
+#define EBI1_CH1_CLK                            201
+#define EBI1_2X_CLK                             202
+#define EBI1_CH0_DQ_CLK                         203
+#define EBI1_CH1_DQ_CLK                         204
+#define EBI1_CH0_CA_CLK                         205
+#define EBI1_CH1_CA_CLK                         206
+#define EBI1_XO_CLK                             207
+#define SFAB_SMPSS_S_H_CLK                      208
+#define PRNG_SRC                                209
+#define PRNG_CLK                                210
+#define PXO_SRC                                 211
+#define SPDM_CY_PORT0_CLK                       212
+#define SPDM_CY_PORT1_CLK                       213
+#define SPDM_CY_PORT2_CLK                       214
+#define SPDM_CY_PORT3_CLK                       215
+#define SPDM_CY_PORT4_CLK                       216
+#define SPDM_CY_PORT5_CLK                       217
+#define SPDM_CY_PORT6_CLK                       218
+#define SPDM_CY_PORT7_CLK                       219
+#define PLL0                                    220
+#define PLL0_VOTE                               221
+#define PLL3                                    222
+#define PLL3_VOTE                               223
+#define PLL4                                    224
+#define PLL4_VOTE                               225
+#define PLL8                                    226
+#define PLL8_VOTE                               227
+#define PLL9                                    228
+#define PLL10                                   229
+#define PLL11                                   230
+#define PLL12                                   231
+#define PLL14                                   232
+#define PLL14_VOTE                              233
+#define PLL18                                   234
+#define CE5_SRC                                 235
+#define CE5_H_CLK                               236
+#define CE5_CORE_CLK                            237
+#define CE3_SLEEP_CLK                           238
+#define SFAB_AHB_S8_FCLK                        239
+#define SPDM_CY_PORT8_CLK                       246
+#define PCIE_ALT_REF_SRC                        247
+#define PCIE_ALT_REF_CLK                        248
+#define PCIE_1_A_CLK                            249
+#define PCIE_1_AUX_CLK                          250
+#define PCIE_1_H_CLK                            251
+#define PCIE_1_PHY_CLK                          252
+#define PCIE_1_ALT_REF_SRC                      253
+#define PCIE_1_ALT_REF_CLK                      254
+#define PCIE_2_A_CLK                            255
+#define PCIE_2_AUX_CLK                          256
+#define PCIE_2_H_CLK                            257
+#define PCIE_2_PHY_CLK                          258
+#define PCIE_2_ALT_REF_SRC                      259
+#define PCIE_2_ALT_REF_CLK                      260
+#define EBI2_CLK                                261
+#define USB30_SLEEP_CLK                         262
+#define USB30_UTMI_SRC                          263
+#define USB30_0_UTMI_CLK                        264
+#define USB30_1_UTMI_CLK                        265
+#define USB30_MASTER_SRC                        266
+#define USB30_0_MASTER_CLK                      267
+#define USB30_1_MASTER_CLK                      268
+#define GMAC_CORE1_CLK_SRC                      269
+#define GMAC_CORE2_CLK_SRC                      270
+#define GMAC_CORE3_CLK_SRC                      271
+#define GMAC_CORE4_CLK_SRC                      272
+#define GMAC_CORE1_CLK                          273
+#define GMAC_CORE2_CLK                          274
+#define GMAC_CORE3_CLK                          275
+#define GMAC_CORE4_CLK                          276
+#define UBI32_CORE1_CLK_SRC                     277
+#define UBI32_CORE2_CLK_SRC                     278
+#define UBI32_CORE1_CLK                         279
+#define UBI32_CORE2_CLK                         280
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8960.h b/include/dt-bindings/clock/qcom,gcc-msm8960.h
index f9f547146a15..7d20eedfee98 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8960.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h
@@ -308,5 +308,16 @@
 #define PLL13                                   292
 #define PLL14                                   293
 #define PLL14_VOTE                              294
+#define USB_HS3_H_CLK                           295
+#define USB_HS3_XCVR_SRC                        296
+#define USB_HS3_XCVR_CLK                        297
+#define USB_HS4_H_CLK                           298
+#define USB_HS4_XCVR_SRC                        299
+#define USB_HS4_XCVR_CLK                        300
+#define SATA_PHY_CFG_CLK                        301
+#define SATA_A_CLK                              302
+#define CE3_SRC                                 303
+#define CE3_CORE_CLK                            304
+#define CE3_H_CLK                               305
 
 #endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-apq8084.h b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
new file mode 100644
index 000000000000..a929f86d0ddd
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H
+#define _DT_BINDINGS_CLK_APQ_MMCC_8084_H
+
+#define MMSS_AHB_CLK_SRC                0
+#define MMSS_AXI_CLK_SRC                1
+#define MMPLL0                          2
+#define MMPLL0_VOTE                     3
+#define MMPLL1                          4
+#define MMPLL1_VOTE                     5
+#define MMPLL2                          6
+#define MMPLL3                          7
+#define MMPLL4                          8
+#define CSI0_CLK_SRC                    9
+#define CSI1_CLK_SRC                    10
+#define CSI2_CLK_SRC                    11
+#define CSI3_CLK_SRC                    12
+#define VCODEC0_CLK_SRC                 13
+#define VFE0_CLK_SRC                    14
+#define VFE1_CLK_SRC                    15
+#define MDP_CLK_SRC                     16
+#define PCLK0_CLK_SRC                   17
+#define PCLK1_CLK_SRC                   18
+#define OCMEMNOC_CLK_SRC                19
+#define GFX3D_CLK_SRC                   20
+#define JPEG0_CLK_SRC                   21
+#define JPEG1_CLK_SRC                   22
+#define JPEG2_CLK_SRC                   23
+#define EDPPIXEL_CLK_SRC                24
+#define EXTPCLK_CLK_SRC                 25
+#define VP_CLK_SRC                      26
+#define CCI_CLK_SRC                     27
+#define CAMSS_GP0_CLK_SRC               28
+#define CAMSS_GP1_CLK_SRC               29
+#define MCLK0_CLK_SRC                   30
+#define MCLK1_CLK_SRC                   31
+#define MCLK2_CLK_SRC                   32
+#define MCLK3_CLK_SRC                   33
+#define CSI0PHYTIMER_CLK_SRC            34
+#define CSI1PHYTIMER_CLK_SRC            35
+#define CSI2PHYTIMER_CLK_SRC            36
+#define CPP_CLK_SRC                     37
+#define BYTE0_CLK_SRC                   38
+#define BYTE1_CLK_SRC                   39
+#define EDPAUX_CLK_SRC                  40
+#define EDPLINK_CLK_SRC                 41
+#define ESC0_CLK_SRC                    42
+#define ESC1_CLK_SRC                    43
+#define HDMI_CLK_SRC                    44
+#define VSYNC_CLK_SRC                   45
+#define RBCPR_CLK_SRC                   46
+#define RBBMTIMER_CLK_SRC               47
+#define MAPLE_CLK_SRC                   48
+#define VDP_CLK_SRC                     49
+#define VPU_BUS_CLK_SRC                 50
+#define MMSS_CXO_CLK                    51
+#define MMSS_SLEEPCLK_CLK               52
+#define AVSYNC_AHB_CLK                  53
+#define AVSYNC_EDPPIXEL_CLK             54
+#define AVSYNC_EXTPCLK_CLK              55
+#define AVSYNC_PCLK0_CLK                56
+#define AVSYNC_PCLK1_CLK                57
+#define AVSYNC_VP_CLK                   58
+#define CAMSS_AHB_CLK                   59
+#define CAMSS_CCI_CCI_AHB_CLK           60
+#define CAMSS_CCI_CCI_CLK               61
+#define CAMSS_CSI0_AHB_CLK              62
+#define CAMSS_CSI0_CLK                  63
+#define CAMSS_CSI0PHY_CLK               64
+#define CAMSS_CSI0PIX_CLK               65
+#define CAMSS_CSI0RDI_CLK               66
+#define CAMSS_CSI1_AHB_CLK              67
+#define CAMSS_CSI1_CLK                  68
+#define CAMSS_CSI1PHY_CLK               69
+#define CAMSS_CSI1PIX_CLK               70
+#define CAMSS_CSI1RDI_CLK               71
+#define CAMSS_CSI2_AHB_CLK              72
+#define CAMSS_CSI2_CLK                  73
+#define CAMSS_CSI2PHY_CLK               74
+#define CAMSS_CSI2PIX_CLK               75
+#define CAMSS_CSI2RDI_CLK               76
+#define CAMSS_CSI3_AHB_CLK              77
+#define CAMSS_CSI3_CLK                  78
+#define CAMSS_CSI3PHY_CLK               79
+#define CAMSS_CSI3PIX_CLK               80
+#define CAMSS_CSI3RDI_CLK               81
+#define CAMSS_CSI_VFE0_CLK              82
+#define CAMSS_CSI_VFE1_CLK              83
+#define CAMSS_GP0_CLK                   84
+#define CAMSS_GP1_CLK                   85
+#define CAMSS_ISPIF_AHB_CLK             86
+#define CAMSS_JPEG_JPEG0_CLK            87
+#define CAMSS_JPEG_JPEG1_CLK            88
+#define CAMSS_JPEG_JPEG2_CLK            89
+#define CAMSS_JPEG_JPEG_AHB_CLK         90
+#define CAMSS_JPEG_JPEG_AXI_CLK         91
+#define CAMSS_MCLK0_CLK                 92
+#define CAMSS_MCLK1_CLK                 93
+#define CAMSS_MCLK2_CLK                 94
+#define CAMSS_MCLK3_CLK                 95
+#define CAMSS_MICRO_AHB_CLK             96
+#define CAMSS_PHY0_CSI0PHYTIMER_CLK     97
+#define CAMSS_PHY1_CSI1PHYTIMER_CLK     98
+#define CAMSS_PHY2_CSI2PHYTIMER_CLK     99
+#define CAMSS_TOP_AHB_CLK               100
+#define CAMSS_VFE_CPP_AHB_CLK           101
+#define CAMSS_VFE_CPP_CLK               102
+#define CAMSS_VFE_VFE0_CLK              103
+#define CAMSS_VFE_VFE1_CLK              104
+#define CAMSS_VFE_VFE_AHB_CLK           105
+#define CAMSS_VFE_VFE_AXI_CLK           106
+#define MDSS_AHB_CLK                    107
+#define MDSS_AXI_CLK                    108
+#define MDSS_BYTE0_CLK                  109
+#define MDSS_BYTE1_CLK                  110
+#define MDSS_EDPAUX_CLK                 111
+#define MDSS_EDPLINK_CLK                112
+#define MDSS_EDPPIXEL_CLK               113
+#define MDSS_ESC0_CLK                   114
+#define MDSS_ESC1_CLK                   115
+#define MDSS_EXTPCLK_CLK                116
+#define MDSS_HDMI_AHB_CLK               117
+#define MDSS_HDMI_CLK                   118
+#define MDSS_MDP_CLK                    119
+#define MDSS_MDP_LUT_CLK                120
+#define MDSS_PCLK0_CLK                  121
+#define MDSS_PCLK1_CLK                  122
+#define MDSS_VSYNC_CLK                  123
+#define MMSS_RBCPR_AHB_CLK              124
+#define MMSS_RBCPR_CLK                  125
+#define MMSS_SPDM_AHB_CLK               126
+#define MMSS_SPDM_AXI_CLK               127
+#define MMSS_SPDM_CSI0_CLK              128
+#define MMSS_SPDM_GFX3D_CLK             129
+#define MMSS_SPDM_JPEG0_CLK             130
+#define MMSS_SPDM_JPEG1_CLK             131
+#define MMSS_SPDM_JPEG2_CLK             132
+#define MMSS_SPDM_MDP_CLK               133
+#define MMSS_SPDM_PCLK0_CLK             134
+#define MMSS_SPDM_PCLK1_CLK             135
+#define MMSS_SPDM_VCODEC0_CLK           136
+#define MMSS_SPDM_VFE0_CLK              137
+#define MMSS_SPDM_VFE1_CLK              138
+#define MMSS_SPDM_RM_AXI_CLK            139
+#define MMSS_SPDM_RM_OCMEMNOC_CLK       140
+#define MMSS_MISC_AHB_CLK               141
+#define MMSS_MMSSNOC_AHB_CLK            142
+#define MMSS_MMSSNOC_BTO_AHB_CLK        143
+#define MMSS_MMSSNOC_AXI_CLK            144
+#define MMSS_S0_AXI_CLK                 145
+#define OCMEMCX_AHB_CLK                 146
+#define OCMEMCX_OCMEMNOC_CLK            147
+#define OXILI_OCMEMGX_CLK               148
+#define OXILI_GFX3D_CLK                 149
+#define OXILI_RBBMTIMER_CLK             150
+#define OXILICX_AHB_CLK                 151
+#define VENUS0_AHB_CLK                  152
+#define VENUS0_AXI_CLK                  153
+#define VENUS0_CORE0_VCODEC_CLK         154
+#define VENUS0_CORE1_VCODEC_CLK         155
+#define VENUS0_OCMEMNOC_CLK             156
+#define VENUS0_VCODEC0_CLK              157
+#define VPU_AHB_CLK                     158
+#define VPU_AXI_CLK                     159
+#define VPU_BUS_CLK                     160
+#define VPU_CXO_CLK                     161
+#define VPU_MAPLE_CLK                   162
+#define VPU_SLEEP_CLK                   163
+#define VPU_VDP_CLK                     164
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/include/dt-bindings/clock/qcom,mmcc-msm8960.h
index 5868ef14a777..85041b28f97f 100644
--- a/include/dt-bindings/clock/qcom,mmcc-msm8960.h
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8960.h
@@ -133,5 +133,13 @@
 #define CSIPHY0_TIMER_CLK                               116
 #define PLL1                                            117
 #define PLL2                                            118
+#define RGB_TV_CLK                                      119
+#define NPL_TV_CLK                                      120
+#define VCAP_AHB_CLK                                    121
+#define VCAP_AXI_CLK                                    122
+#define VCAP_SRC                                        123
+#define VCAP_CLK                                        124
+#define VCAP_NPL_CLK                                    125
+#define PLL15                                           126
 
 #endif
diff --git a/include/dt-bindings/reset/qcom,gcc-apq8084.h b/include/dt-bindings/reset/qcom,gcc-apq8084.h
new file mode 100644
index 000000000000..527caaf48e3d
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-apq8084.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_APQ_GCC_8084_H
+#define _DT_BINDINGS_RESET_APQ_GCC_8084_H
+
+#define GCC_SYSTEM_NOC_BCR              0
+#define GCC_CONFIG_NOC_BCR              1
+#define GCC_PERIPH_NOC_BCR              2
+#define GCC_IMEM_BCR                    3
+#define GCC_MMSS_BCR                    4
+#define GCC_QDSS_BCR                    5
+#define GCC_USB_30_BCR                  6
+#define GCC_USB3_PHY_BCR                7
+#define GCC_USB_HS_HSIC_BCR             8
+#define GCC_USB_HS_BCR                  9
+#define GCC_USB2A_PHY_BCR               10
+#define GCC_USB2B_PHY_BCR               11
+#define GCC_SDCC1_BCR                   12
+#define GCC_SDCC2_BCR                   13
+#define GCC_SDCC3_BCR                   14
+#define GCC_SDCC4_BCR                   15
+#define GCC_BLSP1_BCR                   16
+#define GCC_BLSP1_QUP1_BCR              17
+#define GCC_BLSP1_UART1_BCR             18
+#define GCC_BLSP1_QUP2_BCR              19
+#define GCC_BLSP1_UART2_BCR             20
+#define GCC_BLSP1_QUP3_BCR              21
+#define GCC_BLSP1_UART3_BCR             22
+#define GCC_BLSP1_QUP4_BCR              23
+#define GCC_BLSP1_UART4_BCR             24
+#define GCC_BLSP1_QUP5_BCR              25
+#define GCC_BLSP1_UART5_BCR             26
+#define GCC_BLSP1_QUP6_BCR              27
+#define GCC_BLSP1_UART6_BCR             28
+#define GCC_BLSP2_BCR                   29
+#define GCC_BLSP2_QUP1_BCR              30
+#define GCC_BLSP2_UART1_BCR             31
+#define GCC_BLSP2_QUP2_BCR              32
+#define GCC_BLSP2_UART2_BCR             33
+#define GCC_BLSP2_QUP3_BCR              34
+#define GCC_BLSP2_UART3_BCR             35
+#define GCC_BLSP2_QUP4_BCR              36
+#define GCC_BLSP2_UART4_BCR             37
+#define GCC_BLSP2_QUP5_BCR              38
+#define GCC_BLSP2_UART5_BCR             39
+#define GCC_BLSP2_QUP6_BCR              40
+#define GCC_BLSP2_UART6_BCR             41
+#define GCC_PDM_BCR                     42
+#define GCC_PRNG_BCR                    43
+#define GCC_BAM_DMA_BCR                 44
+#define GCC_TSIF_BCR                    45
+#define GCC_TCSR_BCR                    46
+#define GCC_BOOT_ROM_BCR                47
+#define GCC_MSG_RAM_BCR                 48
+#define GCC_TLMM_BCR                    49
+#define GCC_MPM_BCR                     50
+#define GCC_MPM_AHB_RESET               51
+#define GCC_MPM_NON_AHB_RESET           52
+#define GCC_SEC_CTRL_BCR                53
+#define GCC_SPMI_BCR                    54
+#define GCC_SPDM_BCR                    55
+#define GCC_CE1_BCR                     56
+#define GCC_CE2_BCR                     57
+#define GCC_BIMC_BCR                    58
+#define GCC_SNOC_BUS_TIMEOUT0_BCR       59
+#define GCC_SNOC_BUS_TIMEOUT2_BCR       60
+#define GCC_PNOC_BUS_TIMEOUT0_BCR       61
+#define GCC_PNOC_BUS_TIMEOUT1_BCR       62
+#define GCC_PNOC_BUS_TIMEOUT2_BCR       63
+#define GCC_PNOC_BUS_TIMEOUT3_BCR       64
+#define GCC_PNOC_BUS_TIMEOUT4_BCR       65
+#define GCC_CNOC_BUS_TIMEOUT0_BCR       66
+#define GCC_CNOC_BUS_TIMEOUT1_BCR       67
+#define GCC_CNOC_BUS_TIMEOUT2_BCR       68
+#define GCC_CNOC_BUS_TIMEOUT3_BCR       69
+#define GCC_CNOC_BUS_TIMEOUT4_BCR       70
+#define GCC_CNOC_BUS_TIMEOUT5_BCR       71
+#define GCC_CNOC_BUS_TIMEOUT6_BCR       72
+#define GCC_DEHR_BCR                    73
+#define GCC_RBCPR_BCR                   74
+#define GCC_MSS_RESTART                 75
+#define GCC_LPASS_RESTART               76
+#define GCC_WCSS_RESTART                77
+#define GCC_VENUS_RESTART               78
+#define GCC_COPSS_SMMU_BCR              79
+#define GCC_SPSS_BCR                    80
+#define GCC_PCIE_0_BCR                  81
+#define GCC_PCIE_0_PHY_BCR              82
+#define GCC_PCIE_1_BCR                  83
+#define GCC_PCIE_1_PHY_BCR              84
+#define GCC_USB_30_SEC_BCR              85
+#define GCC_USB3_SEC_PHY_BCR            86
+#define GCC_SATA_BCR                    87
+#define GCC_CE3_BCR                     88
+#define GCC_UFS_BCR                     89
+#define GCC_USB30_PHY_COM_BCR           90
+
+#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
new file mode 100644
index 000000000000..0ad5ef930b5d
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_IPQ_806X_H
+#define _DT_BINDINGS_RESET_IPQ_806X_H
+
+#define QDSS_STM_RESET                                  0
+#define AFAB_SMPSS_S_RESET                              1
+#define AFAB_SMPSS_M1_RESET                             2
+#define AFAB_SMPSS_M0_RESET                             3
+#define AFAB_EBI1_CH0_RESET                             4
+#define AFAB_EBI1_CH1_RESET                             5
+#define SFAB_ADM0_M0_RESET                              6
+#define SFAB_ADM0_M1_RESET                              7
+#define SFAB_ADM0_M2_RESET                              8
+#define ADM0_C2_RESET                                   9
+#define ADM0_C1_RESET                                   10
+#define ADM0_C0_RESET                                   11
+#define ADM0_PBUS_RESET                                 12
+#define ADM0_RESET                                      13
+#define QDSS_CLKS_SW_RESET                              14
+#define QDSS_POR_RESET                                  15
+#define QDSS_TSCTR_RESET                                16
+#define QDSS_HRESET_RESET                               17
+#define QDSS_AXI_RESET                                  18
+#define QDSS_DBG_RESET                                  19
+#define SFAB_PCIE_M_RESET                               20
+#define SFAB_PCIE_S_RESET                               21
+#define PCIE_EXT_RESET                                  22
+#define PCIE_PHY_RESET                                  23
+#define PCIE_PCI_RESET                                  24
+#define PCIE_POR_RESET                                  25
+#define PCIE_HCLK_RESET                                 26
+#define PCIE_ACLK_RESET                                 27
+#define SFAB_LPASS_RESET                                28
+#define SFAB_AFAB_M_RESET                               29
+#define AFAB_SFAB_M0_RESET                              30
+#define AFAB_SFAB_M1_RESET                              31
+#define SFAB_SATA_S_RESET                               32
+#define SFAB_DFAB_M_RESET                               33
+#define DFAB_SFAB_M_RESET                               34
+#define DFAB_SWAY0_RESET                                35
+#define DFAB_SWAY1_RESET                                36
+#define DFAB_ARB0_RESET                                 37
+#define DFAB_ARB1_RESET                                 38
+#define PPSS_PROC_RESET                                 39
+#define PPSS_RESET                                      40
+#define DMA_BAM_RESET                                   41
+#define SPS_TIC_H_RESET                                 42
+#define SFAB_CFPB_M_RESET                               43
+#define SFAB_CFPB_S_RESET                               44
+#define TSIF_H_RESET                                    45
+#define CE1_H_RESET                                     46
+#define CE1_CORE_RESET                                  47
+#define CE1_SLEEP_RESET                                 48
+#define CE2_H_RESET                                     49
+#define CE2_CORE_RESET                                  50
+#define SFAB_SFPB_M_RESET                               51
+#define SFAB_SFPB_S_RESET                               52
+#define RPM_PROC_RESET                                  53
+#define PMIC_SSBI2_RESET                                54
+#define SDC1_RESET                                      55
+#define SDC2_RESET                                      56
+#define SDC3_RESET                                      57
+#define SDC4_RESET                                      58
+#define USB_HS1_RESET                                   59
+#define USB_HSIC_RESET                                  60
+#define USB_FS1_XCVR_RESET                              61
+#define USB_FS1_RESET                                   62
+#define GSBI1_RESET                                     63
+#define GSBI2_RESET                                     64
+#define GSBI3_RESET                                     65
+#define GSBI4_RESET                                     66
+#define GSBI5_RESET                                     67
+#define GSBI6_RESET                                     68
+#define GSBI7_RESET                                     69
+#define SPDM_RESET                                      70
+#define SEC_CTRL_RESET                                  71
+#define TLMM_H_RESET                                    72
+#define SFAB_SATA_M_RESET                               73
+#define SATA_RESET                                      74
+#define TSSC_RESET                                      75
+#define PDM_RESET                                       76
+#define MPM_H_RESET                                     77
+#define MPM_RESET                                       78
+#define SFAB_SMPSS_S_RESET                              79
+#define PRNG_RESET                                      80
+#define SFAB_CE3_M_RESET                                81
+#define SFAB_CE3_S_RESET                                82
+#define CE3_SLEEP_RESET                                 83
+#define PCIE_1_M_RESET                                  84
+#define PCIE_1_S_RESET                                  85
+#define PCIE_1_EXT_RESET                                86
+#define PCIE_1_PHY_RESET                                87
+#define PCIE_1_PCI_RESET                                88
+#define PCIE_1_POR_RESET                                89
+#define PCIE_1_HCLK_RESET                               90
+#define PCIE_1_ACLK_RESET                               91
+#define PCIE_2_M_RESET                                  92
+#define PCIE_2_S_RESET                                  93
+#define PCIE_2_EXT_RESET                                94
+#define PCIE_2_PHY_RESET                                95
+#define PCIE_2_PCI_RESET                                96
+#define PCIE_2_POR_RESET                                97
+#define PCIE_2_HCLK_RESET                               98
+#define PCIE_2_ACLK_RESET                               99
+#define SFAB_USB30_S_RESET                              100
+#define SFAB_USB30_M_RESET                              101
+#define USB30_0_PORT2_HS_PHY_RESET                      102
+#define USB30_0_MASTER_RESET                            103
+#define USB30_0_SLEEP_RESET                             104
+#define USB30_0_UTMI_PHY_RESET                          105
+#define USB30_0_POWERON_RESET                           106
+#define USB30_0_PHY_RESET                               107
+#define USB30_1_MASTER_RESET                            108
+#define USB30_1_SLEEP_RESET                             109
+#define USB30_1_UTMI_PHY_RESET                          110
+#define USB30_1_POWERON_RESET                           111
+#define USB30_1_PHY_RESET                               112
+#define NSSFB0_RESET                                    113
+#define NSSFB1_RESET                                    114
+#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8960.h b/include/dt-bindings/reset/qcom,gcc-msm8960.h
index 07edd0e65eed..47c8686955da 100644
--- a/include/dt-bindings/reset/qcom,gcc-msm8960.h
+++ b/include/dt-bindings/reset/qcom,gcc-msm8960.h
@@ -114,5 +114,21 @@
 #define SFAB_SMPSS_S_RESET                              97
 #define PRNG_RESET                                      98
 #define RIVA_RESET                                      99
+#define USB_HS3_RESET                                   100
+#define USB_HS4_RESET                                   101
+#define CE3_RESET                                       102
+#define PCIE_EXT_PCI_RESET                              103
+#define PCIE_PHY_RESET                                  104
+#define PCIE_PCI_RESET                                  105
+#define PCIE_POR_RESET                                  106
+#define PCIE_HCLK_RESET                                 107
+#define PCIE_ACLK_RESET                                 108
+#define CE3_H_RESET                                     109
+#define SFAB_CE3_M_RESET                                110
+#define SFAB_CE3_S_RESET                                111
+#define SATA_RESET                                      112
+#define CE3_SLEEP_RESET                                 113
+#define GSS_SLP_RESET                                   114
+#define GSS_RESET                                       115
 
 #endif
diff --git a/include/dt-bindings/reset/qcom,mmcc-apq8084.h b/include/dt-bindings/reset/qcom,mmcc-apq8084.h
new file mode 100644
index 000000000000..c1671396531d
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,mmcc-apq8084.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_APQ_MMCC_8084_H
+#define _DT_BINDINGS_RESET_APQ_MMCC_8084_H
+
+#define MMSS_SPDM_RESET                 0
+#define MMSS_SPDM_RM_RESET              1
+#define VENUS0_RESET                    2
+#define VPU_RESET                       3
+#define MDSS_RESET                      4
+#define AVSYNC_RESET                    5
+#define CAMSS_PHY0_RESET                6
+#define CAMSS_PHY1_RESET                7
+#define CAMSS_PHY2_RESET                8
+#define CAMSS_CSI0_RESET                9
+#define CAMSS_CSI0PHY_RESET             10
+#define CAMSS_CSI0RDI_RESET             11
+#define CAMSS_CSI0PIX_RESET             12
+#define CAMSS_CSI1_RESET                13
+#define CAMSS_CSI1PHY_RESET             14
+#define CAMSS_CSI1RDI_RESET             15
+#define CAMSS_CSI1PIX_RESET             16
+#define CAMSS_CSI2_RESET                17
+#define CAMSS_CSI2PHY_RESET             18
+#define CAMSS_CSI2RDI_RESET             19
+#define CAMSS_CSI2PIX_RESET             20
+#define CAMSS_CSI3_RESET                21
+#define CAMSS_CSI3PHY_RESET             22
+#define CAMSS_CSI3RDI_RESET             23
+#define CAMSS_CSI3PIX_RESET             24
+#define CAMSS_ISPIF_RESET               25
+#define CAMSS_CCI_RESET                 26
+#define CAMSS_MCLK0_RESET               27
+#define CAMSS_MCLK1_RESET               28
+#define CAMSS_MCLK2_RESET               29
+#define CAMSS_MCLK3_RESET               30
+#define CAMSS_GP0_RESET                 31
+#define CAMSS_GP1_RESET                 32
+#define CAMSS_TOP_RESET                 33
+#define CAMSS_AHB_RESET                 34
+#define CAMSS_MICRO_RESET               35
+#define CAMSS_JPEG_RESET                36
+#define CAMSS_VFE_RESET                 37
+#define CAMSS_CSI_VFE0_RESET            38
+#define CAMSS_CSI_VFE1_RESET            39
+#define OXILI_RESET                     40
+#define OXILICX_RESET                   41
+#define OCMEMCX_RESET                   42
+#define MMSS_RBCRP_RESET                43
+#define MMSSNOCAHB_RESET                44
+#define MMSSNOCAXI_RESET                45
+
+#endif
diff --git a/include/dt-bindings/reset/qcom,mmcc-msm8960.h b/include/dt-bindings/reset/qcom,mmcc-msm8960.h
index ba36ec680118..11741113a841 100644
--- a/include/dt-bindings/reset/qcom,mmcc-msm8960.h
+++ b/include/dt-bindings/reset/qcom,mmcc-msm8960.h
@@ -89,5 +89,13 @@
 #define CSI2_RESET                                      72
 #define CSI_RDI1_RESET                                  73
 #define CSI_RDI2_RESET                                  74
+#define GFX3D_AXI_RESET                                 75
+#define VCAP_AXI_RESET                                  76
+#define SMMU_VCAP_AHB_RESET                             77
+#define VCAP_AHB_RESET                                  78
+#define CSI_RDI_RESET                                   79
+#define CSI_PIX_RESET                                   80
+#define VCAP_NPL_RESET                                  81
+#define VCAP_RESET                                      82
 
 #endif