Merge branch 'kvm-arm/timer' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into next/virt

From Marc Zyngier, this branch enables virtual GIC and timer for KVM/ARM.

* 'kvm-arm/timer' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms:
  ARM: KVM: arch_timers: Wire the init code and config option
  ARM: KVM: arch_timers: Add timer world switch
  ARM: KVM: arch_timers: Add guest timer core support
  ARM: KVM: Add VGIC configuration option
  ARM: KVM: VGIC initialisation code
  ARM: KVM: VGIC control interface world switch
  ARM: KVM: VGIC interrupt injection
  ARM: KVM: vgic: retire queued, disabled interrupts
  ARM: KVM: VGIC virtual CPU interface management
  ARM: KVM: VGIC distributor handling
  ARM: KVM: VGIC accept vcpu and dist base addresses from user space
  ARM: KVM: Initial VGIC infrastructure code
  ARM: KVM: Keep track of currently running vcpus
  KVM: ARM: Introduce KVM_ARM_SET_DEVICE_ADDR ioctl
  ARM: gic: add __ASSEMBLY__ guard to C definitions
  ARM: gic: define GICH offsets for VGIC support
  ARM: gic: add missing distributor defintions

1 files changed, 32 insertions, 1 deletions

diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index a67ca55e6f4e..3fd8e4290a1c 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -20,16 +20,45 @@
 
 #define GIC_DIST_CTRL                   0x000
 #define GIC_DIST_CTR                    0x004
+#define GIC_DIST_IGROUP                 0x080
 #define GIC_DIST_ENABLE_SET             0x100
 #define GIC_DIST_ENABLE_CLEAR           0x180
 #define GIC_DIST_PENDING_SET            0x200
 #define GIC_DIST_PENDING_CLEAR          0x280
-#define GIC_DIST_ACTIVE_BIT             0x300
+#define GIC_DIST_ACTIVE_SET             0x300
+#define GIC_DIST_ACTIVE_CLEAR           0x380
 #define GIC_DIST_PRI                    0x400
 #define GIC_DIST_TARGET                 0x800
 #define GIC_DIST_CONFIG                 0xc00
 #define GIC_DIST_SOFTINT                0xf00
 
+#define GICH_HCR                        0x0
+#define GICH_VTR                        0x4
+#define GICH_VMCR                       0x8
+#define GICH_MISR                       0x10
+#define GICH_EISR0                      0x20
+#define GICH_EISR1                      0x24
+#define GICH_ELRSR0                     0x30
+#define GICH_ELRSR1                     0x34
+#define GICH_APR                        0xf0
+#define GICH_LR0                        0x100
+
+#define GICH_HCR_EN                     (1 << 0)
+#define GICH_HCR_UIE                    (1 << 1)
+
+#define GICH_LR_VIRTUALID               (0x3ff << 0)
+#define GICH_LR_PHYSID_CPUID_SHIFT      (10)
+#define GICH_LR_PHYSID_CPUID            (7 << GICH_LR_PHYSID_CPUID_SHIFT)
+#define GICH_LR_STATE                   (3 << 28)
+#define GICH_LR_PENDING_BIT             (1 << 28)
+#define GICH_LR_ACTIVE_BIT              (1 << 29)
+#define GICH_LR_EOI                     (1 << 19)
+
+#define GICH_MISR_EOI                   (1 << 0)
+#define GICH_MISR_U                     (1 << 1)
+
+#ifndef __ASSEMBLY__
+
 struct device_node;
 
 extern struct irq_chip gic_arch_extn;
@@ -45,4 +74,6 @@ static inline void gic_init(unsigned int nr, int start,
         gic_init_bases(nr, start, dist, cpu, 0, NULL);
 }
 
+#endif /* __ASSEMBLY */
+
 #endif