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authorDavid S. Miller <davem@davemloft.net>2015-03-03 21:16:48 -0500
committerDavid S. Miller <davem@davemloft.net>2015-03-03 21:16:48 -0500
commit71a83a6db6138b9d41d8a0b6b91cb59f6dc4742c (patch)
treef74b6e4e48257ec6ce40b95645ecb8533b9cc1f8 /include/linux
parentb97526f3ff95f92b107f0fb52cbb8627e395429b (diff)
parenta6c5170d1edea97c538c81e377e56c7b5c5b7e63 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts: drivers/net/ethernet/rocker/rocker.c The rocker commit was two overlapping changes, one to rename the ->vport member to ->pport, and another making the bitmask expression use '1ULL' instead of plain '1'. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/bcm47xx_wdt.h1
-rw-r--r--include/linux/ceph/ceph_fs.h37
-rw-r--r--include/linux/ceph/libceph.h3
-rw-r--r--include/linux/ceph/messenger.h4
-rw-r--r--include/linux/ceph/mon_client.h9
-rw-r--r--include/linux/clk-private.h220
-rw-r--r--include/linux/clk-provider.h58
-rw-r--r--include/linux/clk.h45
-rw-r--r--include/linux/clk/sunxi.h22
-rw-r--r--include/linux/clk/tegra.h2
-rw-r--r--include/linux/clk/ti.h25
-rw-r--r--include/linux/compiler.h6
-rw-r--r--include/linux/dcache.h103
-rw-r--r--include/linux/dmaengine.h120
-rw-r--r--include/linux/fs.h3
-rw-r--r--include/linux/hid-sensor-hub.h5
-rw-r--r--include/linux/i2c.h4
-rw-r--r--include/linux/irqchip/mips-gic.h1
-rw-r--r--include/linux/kdb.h8
-rw-r--r--include/linux/lguest_launcher.h61
-rw-r--r--include/linux/mfd/axp20x.h43
-rw-r--r--include/linux/mfd/da9063/core.h1
-rw-r--r--include/linux/mfd/da9150/core.h68
-rw-r--r--include/linux/mfd/da9150/registers.h1155
-rw-r--r--include/linux/mfd/max77686-private.h1
-rw-r--r--include/linux/mfd/max77686.h28
-rw-r--r--include/linux/mfd/qcom_rpm.h13
-rw-r--r--include/linux/mfd/rt5033-private.h260
-rw-r--r--include/linux/mfd/rt5033.h62
-rw-r--r--include/linux/mlx4/qp.h2
-rw-r--r--include/linux/mtd/mtd.h1
-rw-r--r--include/linux/mtd/spi-nor.h7
-rw-r--r--include/linux/netdevice.h1
-rw-r--r--include/linux/nfs_fs.h1
-rw-r--r--include/linux/nfs_xdr.h19
-rw-r--r--include/linux/nvme.h9
-rw-r--r--include/linux/platform_data/bfin_rotary.h117
-rw-r--r--include/linux/platform_data/dma-dw.h6
-rw-r--r--include/linux/platform_data/dma-mmp_tdma.h7
-rw-r--r--include/linux/rhashtable.h22
-rw-r--r--include/linux/sched.h10
-rw-r--r--include/linux/sunrpc/metrics.h7
-rw-r--r--include/linux/thermal.h56
-rw-r--r--include/linux/vfio.h2
-rw-r--r--include/linux/virtio_mmio.h44
45 files changed, 2180 insertions, 499 deletions
diff --git a/include/linux/bcm47xx_wdt.h b/include/linux/bcm47xx_wdt.h
index b708786d4cbf..5582c211f594 100644
--- a/include/linux/bcm47xx_wdt.h
+++ b/include/linux/bcm47xx_wdt.h
@@ -16,6 +16,7 @@ struct bcm47xx_wdt {
16 16
17 struct watchdog_device wdd; 17 struct watchdog_device wdd;
18 struct notifier_block notifier; 18 struct notifier_block notifier;
19 struct notifier_block restart_handler;
19 20
20 struct timer_list soft_timer; 21 struct timer_list soft_timer;
21 atomic_t soft_ticks; 22 atomic_t soft_ticks;
diff --git a/include/linux/ceph/ceph_fs.h b/include/linux/ceph/ceph_fs.h
index c0dadaac26e3..31eb03d0c766 100644
--- a/include/linux/ceph/ceph_fs.h
+++ b/include/linux/ceph/ceph_fs.h
@@ -158,17 +158,6 @@ enum {
158}; 158};
159 159
160 160
161/* pool operations */
162enum {
163 POOL_OP_CREATE = 0x01,
164 POOL_OP_DELETE = 0x02,
165 POOL_OP_AUID_CHANGE = 0x03,
166 POOL_OP_CREATE_SNAP = 0x11,
167 POOL_OP_DELETE_SNAP = 0x12,
168 POOL_OP_CREATE_UNMANAGED_SNAP = 0x21,
169 POOL_OP_DELETE_UNMANAGED_SNAP = 0x22,
170};
171
172struct ceph_mon_request_header { 161struct ceph_mon_request_header {
173 __le64 have_version; 162 __le64 have_version;
174 __le16 session_mon; 163 __le16 session_mon;
@@ -191,31 +180,6 @@ struct ceph_mon_statfs_reply {
191 struct ceph_statfs st; 180 struct ceph_statfs st;
192} __attribute__ ((packed)); 181} __attribute__ ((packed));
193 182
194const char *ceph_pool_op_name(int op);
195
196struct ceph_mon_poolop {
197 struct ceph_mon_request_header monhdr;
198 struct ceph_fsid fsid;
199 __le32 pool;
200 __le32 op;
201 __le64 auid;
202 __le64 snapid;
203 __le32 name_len;
204} __attribute__ ((packed));
205
206struct ceph_mon_poolop_reply {
207 struct ceph_mon_request_header monhdr;
208 struct ceph_fsid fsid;
209 __le32 reply_code;
210 __le32 epoch;
211 char has_data;
212 char data[0];
213} __attribute__ ((packed));
214
215struct ceph_mon_unmanaged_snap {
216 __le64 snapid;
217} __attribute__ ((packed));
218
219struct ceph_osd_getmap { 183struct ceph_osd_getmap {
220 struct ceph_mon_request_header monhdr; 184 struct ceph_mon_request_header monhdr;
221 struct ceph_fsid fsid; 185 struct ceph_fsid fsid;
@@ -307,6 +271,7 @@ enum {
307 CEPH_SESSION_RECALL_STATE, 271 CEPH_SESSION_RECALL_STATE,
308 CEPH_SESSION_FLUSHMSG, 272 CEPH_SESSION_FLUSHMSG,
309 CEPH_SESSION_FLUSHMSG_ACK, 273 CEPH_SESSION_FLUSHMSG_ACK,
274 CEPH_SESSION_FORCE_RO,
310}; 275};
311 276
312extern const char *ceph_session_op_name(int op); 277extern const char *ceph_session_op_name(int op);
diff --git a/include/linux/ceph/libceph.h b/include/linux/ceph/libceph.h
index 8b11a79ca1cb..16fff9608848 100644
--- a/include/linux/ceph/libceph.h
+++ b/include/linux/ceph/libceph.h
@@ -30,8 +30,9 @@
30#define CEPH_OPT_MYIP (1<<2) /* specified my ip */ 30#define CEPH_OPT_MYIP (1<<2) /* specified my ip */
31#define CEPH_OPT_NOCRC (1<<3) /* no data crc on writes */ 31#define CEPH_OPT_NOCRC (1<<3) /* no data crc on writes */
32#define CEPH_OPT_NOMSGAUTH (1<<4) /* not require cephx message signature */ 32#define CEPH_OPT_NOMSGAUTH (1<<4) /* not require cephx message signature */
33#define CEPH_OPT_TCP_NODELAY (1<<5) /* TCP_NODELAY on TCP sockets */
33 34
34#define CEPH_OPT_DEFAULT (0) 35#define CEPH_OPT_DEFAULT (CEPH_OPT_TCP_NODELAY)
35 36
36#define ceph_set_opt(client, opt) \ 37#define ceph_set_opt(client, opt) \
37 (client)->options->flags |= CEPH_OPT_##opt; 38 (client)->options->flags |= CEPH_OPT_##opt;
diff --git a/include/linux/ceph/messenger.h b/include/linux/ceph/messenger.h
index d9d396c16503..e15499422fdc 100644
--- a/include/linux/ceph/messenger.h
+++ b/include/linux/ceph/messenger.h
@@ -57,6 +57,7 @@ struct ceph_messenger {
57 57
58 atomic_t stopping; 58 atomic_t stopping;
59 bool nocrc; 59 bool nocrc;
60 bool tcp_nodelay;
60 61
61 /* 62 /*
62 * the global_seq counts connections i (attempt to) initiate 63 * the global_seq counts connections i (attempt to) initiate
@@ -264,7 +265,8 @@ extern void ceph_messenger_init(struct ceph_messenger *msgr,
264 struct ceph_entity_addr *myaddr, 265 struct ceph_entity_addr *myaddr,
265 u64 supported_features, 266 u64 supported_features,
266 u64 required_features, 267 u64 required_features,
267 bool nocrc); 268 bool nocrc,
269 bool tcp_nodelay);
268 270
269extern void ceph_con_init(struct ceph_connection *con, void *private, 271extern void ceph_con_init(struct ceph_connection *con, void *private,
270 const struct ceph_connection_operations *ops, 272 const struct ceph_connection_operations *ops,
diff --git a/include/linux/ceph/mon_client.h b/include/linux/ceph/mon_client.h
index deb47e45ac7c..81810dc21f06 100644
--- a/include/linux/ceph/mon_client.h
+++ b/include/linux/ceph/mon_client.h
@@ -40,7 +40,7 @@ struct ceph_mon_request {
40}; 40};
41 41
42/* 42/*
43 * ceph_mon_generic_request is being used for the statfs, poolop and 43 * ceph_mon_generic_request is being used for the statfs and
44 * mon_get_version requests which are being done a bit differently 44 * mon_get_version requests which are being done a bit differently
45 * because we need to get data back to the caller 45 * because we need to get data back to the caller
46 */ 46 */
@@ -50,7 +50,6 @@ struct ceph_mon_generic_request {
50 struct rb_node node; 50 struct rb_node node;
51 int result; 51 int result;
52 void *buf; 52 void *buf;
53 int buf_len;
54 struct completion completion; 53 struct completion completion;
55 struct ceph_msg *request; /* original request */ 54 struct ceph_msg *request; /* original request */
56 struct ceph_msg *reply; /* and reply */ 55 struct ceph_msg *reply; /* and reply */
@@ -117,10 +116,4 @@ extern int ceph_monc_open_session(struct ceph_mon_client *monc);
117 116
118extern int ceph_monc_validate_auth(struct ceph_mon_client *monc); 117extern int ceph_monc_validate_auth(struct ceph_mon_client *monc);
119 118
120extern int ceph_monc_create_snapid(struct ceph_mon_client *monc,
121 u32 pool, u64 *snapid);
122
123extern int ceph_monc_delete_snapid(struct ceph_mon_client *monc,
124 u32 pool, u64 snapid);
125
126#endif 119#endif
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
deleted file mode 100644
index 0ca5f6046920..000000000000
--- a/include/linux/clk-private.h
+++ /dev/null
@@ -1,220 +0,0 @@
1/*
2 * linux/include/linux/clk-private.h
3 *
4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef __LINUX_CLK_PRIVATE_H
12#define __LINUX_CLK_PRIVATE_H
13
14#include <linux/clk-provider.h>
15#include <linux/kref.h>
16#include <linux/list.h>
17
18/*
19 * WARNING: Do not include clk-private.h from any file that implements struct
20 * clk_ops. Doing so is a layering violation!
21 *
22 * This header exists only to allow for statically initialized clock data. Any
23 * static clock data must be defined in a separate file from the logic that
24 * implements the clock operations for that same data.
25 */
26
27#ifdef CONFIG_COMMON_CLK
28
29struct module;
30
31struct clk {
32 const char *name;
33 const struct clk_ops *ops;
34 struct clk_hw *hw;
35 struct module *owner;
36 struct clk *parent;
37 const char **parent_names;
38 struct clk **parents;
39 u8 num_parents;
40 u8 new_parent_index;
41 unsigned long rate;
42 unsigned long new_rate;
43 struct clk *new_parent;
44 struct clk *new_child;
45 unsigned long flags;
46 unsigned int enable_count;
47 unsigned int prepare_count;
48 unsigned long accuracy;
49 int phase;
50 struct hlist_head children;
51 struct hlist_node child_node;
52 struct hlist_node debug_node;
53 unsigned int notifier_count;
54#ifdef CONFIG_DEBUG_FS
55 struct dentry *dentry;
56#endif
57 struct kref ref;
58};
59
60/*
61 * DOC: Basic clock implementations common to many platforms
62 *
63 * Each basic clock hardware type is comprised of a structure describing the
64 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
65 * unique flags for that hardware type, a registration function and an
66 * alternative macro for static initialization
67 */
68
69#define DEFINE_CLK(_name, _ops, _flags, _parent_names, \
70 _parents) \
71 static struct clk _name = { \
72 .name = #_name, \
73 .ops = &_ops, \
74 .hw = &_name##_hw.hw, \
75 .parent_names = _parent_names, \
76 .num_parents = ARRAY_SIZE(_parent_names), \
77 .parents = _parents, \
78 .flags = _flags | CLK_IS_BASIC, \
79 }
80
81#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \
82 _fixed_rate_flags) \
83 static struct clk _name; \
84 static const char *_name##_parent_names[] = {}; \
85 static struct clk_fixed_rate _name##_hw = { \
86 .hw = { \
87 .clk = &_name, \
88 }, \
89 .fixed_rate = _rate, \
90 .flags = _fixed_rate_flags, \
91 }; \
92 DEFINE_CLK(_name, clk_fixed_rate_ops, _flags, \
93 _name##_parent_names, NULL);
94
95#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, \
96 _flags, _reg, _bit_idx, \
97 _gate_flags, _lock) \
98 static struct clk _name; \
99 static const char *_name##_parent_names[] = { \
100 _parent_name, \
101 }; \
102 static struct clk *_name##_parents[] = { \
103 _parent_ptr, \
104 }; \
105 static struct clk_gate _name##_hw = { \
106 .hw = { \
107 .clk = &_name, \
108 }, \
109 .reg = _reg, \
110 .bit_idx = _bit_idx, \
111 .flags = _gate_flags, \
112 .lock = _lock, \
113 }; \
114 DEFINE_CLK(_name, clk_gate_ops, _flags, \
115 _name##_parent_names, _name##_parents);
116
117#define _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
118 _flags, _reg, _shift, _width, \
119 _divider_flags, _table, _lock) \
120 static struct clk _name; \
121 static const char *_name##_parent_names[] = { \
122 _parent_name, \
123 }; \
124 static struct clk *_name##_parents[] = { \
125 _parent_ptr, \
126 }; \
127 static struct clk_divider _name##_hw = { \
128 .hw = { \
129 .clk = &_name, \
130 }, \
131 .reg = _reg, \
132 .shift = _shift, \
133 .width = _width, \
134 .flags = _divider_flags, \
135 .table = _table, \
136 .lock = _lock, \
137 }; \
138 DEFINE_CLK(_name, clk_divider_ops, _flags, \
139 _name##_parent_names, _name##_parents);
140
141#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
142 _flags, _reg, _shift, _width, \
143 _divider_flags, _lock) \
144 _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
145 _flags, _reg, _shift, _width, \
146 _divider_flags, NULL, _lock)
147
148#define DEFINE_CLK_DIVIDER_TABLE(_name, _parent_name, \
149 _parent_ptr, _flags, _reg, \
150 _shift, _width, _divider_flags, \
151 _table, _lock) \
152 _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
153 _flags, _reg, _shift, _width, \
154 _divider_flags, _table, _lock) \
155
156#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \
157 _reg, _shift, _width, \
158 _mux_flags, _lock) \
159 static struct clk _name; \
160 static struct clk_mux _name##_hw = { \
161 .hw = { \
162 .clk = &_name, \
163 }, \
164 .reg = _reg, \
165 .shift = _shift, \
166 .mask = BIT(_width) - 1, \
167 .flags = _mux_flags, \
168 .lock = _lock, \
169 }; \
170 DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names, \
171 _parents);
172
173#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name, \
174 _parent_ptr, _flags, \
175 _mult, _div) \
176 static struct clk _name; \
177 static const char *_name##_parent_names[] = { \
178 _parent_name, \
179 }; \
180 static struct clk *_name##_parents[] = { \
181 _parent_ptr, \
182 }; \
183 static struct clk_fixed_factor _name##_hw = { \
184 .hw = { \
185 .clk = &_name, \
186 }, \
187 .mult = _mult, \
188 .div = _div, \
189 }; \
190 DEFINE_CLK(_name, clk_fixed_factor_ops, _flags, \
191 _name##_parent_names, _name##_parents);
192
193/**
194 * __clk_init - initialize the data structures in a struct clk
195 * @dev: device initializing this clk, placeholder for now
196 * @clk: clk being initialized
197 *
198 * Initializes the lists in struct clk, queries the hardware for the
199 * parent and rate and sets them both.
200 *
201 * Any struct clk passed into __clk_init must have the following members
202 * populated:
203 * .name
204 * .ops
205 * .hw
206 * .parent_names
207 * .num_parents
208 * .flags
209 *
210 * It is not necessary to call clk_register if __clk_init is used directly with
211 * statically initialized clock data.
212 *
213 * Returns 0 on success, otherwise an error code.
214 */
215int __clk_init(struct device *dev, struct clk *clk);
216
217struct clk *__clk_register(struct device *dev, struct clk_hw *hw);
218
219#endif /* CONFIG_COMMON_CLK */
220#endif /* CLK_PRIVATE_H */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index d936409520f8..5591ea71a8d1 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -33,6 +33,7 @@
33#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 33#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
34 34
35struct clk_hw; 35struct clk_hw;
36struct clk_core;
36struct dentry; 37struct dentry;
37 38
38/** 39/**
@@ -174,9 +175,12 @@ struct clk_ops {
174 unsigned long parent_rate); 175 unsigned long parent_rate);
175 long (*round_rate)(struct clk_hw *hw, unsigned long rate, 176 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
176 unsigned long *parent_rate); 177 unsigned long *parent_rate);
177 long (*determine_rate)(struct clk_hw *hw, unsigned long rate, 178 long (*determine_rate)(struct clk_hw *hw,
178 unsigned long *best_parent_rate, 179 unsigned long rate,
179 struct clk_hw **best_parent_hw); 180 unsigned long min_rate,
181 unsigned long max_rate,
182 unsigned long *best_parent_rate,
183 struct clk_hw **best_parent_hw);
180 int (*set_parent)(struct clk_hw *hw, u8 index); 184 int (*set_parent)(struct clk_hw *hw, u8 index);
181 u8 (*get_parent)(struct clk_hw *hw); 185 u8 (*get_parent)(struct clk_hw *hw);
182 int (*set_rate)(struct clk_hw *hw, unsigned long rate, 186 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
@@ -216,13 +220,17 @@ struct clk_init_data {
216 * clk_foo and then referenced by the struct clk instance that uses struct 220 * clk_foo and then referenced by the struct clk instance that uses struct
217 * clk_foo's clk_ops 221 * clk_foo's clk_ops
218 * 222 *
219 * @clk: pointer to the struct clk instance that points back to this struct 223 * @core: pointer to the struct clk_core instance that points back to this
220 * clk_hw instance 224 * struct clk_hw instance
225 *
226 * @clk: pointer to the per-user struct clk instance that can be used to call
227 * into the clk API
221 * 228 *
222 * @init: pointer to struct clk_init_data that contains the init data shared 229 * @init: pointer to struct clk_init_data that contains the init data shared
223 * with the common clock framework. 230 * with the common clock framework.
224 */ 231 */
225struct clk_hw { 232struct clk_hw {
233 struct clk_core *core;
226 struct clk *clk; 234 struct clk *clk;
227 const struct clk_init_data *init; 235 const struct clk_init_data *init;
228}; 236};
@@ -294,6 +302,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
294 const char *parent_name, unsigned long flags, 302 const char *parent_name, unsigned long flags,
295 void __iomem *reg, u8 bit_idx, 303 void __iomem *reg, u8 bit_idx,
296 u8 clk_gate_flags, spinlock_t *lock); 304 u8 clk_gate_flags, spinlock_t *lock);
305void clk_unregister_gate(struct clk *clk);
297 306
298struct clk_div_table { 307struct clk_div_table {
299 unsigned int val; 308 unsigned int val;
@@ -352,6 +361,17 @@ struct clk_divider {
352#define CLK_DIVIDER_READ_ONLY BIT(5) 361#define CLK_DIVIDER_READ_ONLY BIT(5)
353 362
354extern const struct clk_ops clk_divider_ops; 363extern const struct clk_ops clk_divider_ops;
364
365unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
366 unsigned int val, const struct clk_div_table *table,
367 unsigned long flags);
368long divider_round_rate(struct clk_hw *hw, unsigned long rate,
369 unsigned long *prate, const struct clk_div_table *table,
370 u8 width, unsigned long flags);
371int divider_get_val(unsigned long rate, unsigned long parent_rate,
372 const struct clk_div_table *table, u8 width,
373 unsigned long flags);
374
355struct clk *clk_register_divider(struct device *dev, const char *name, 375struct clk *clk_register_divider(struct device *dev, const char *name,
356 const char *parent_name, unsigned long flags, 376 const char *parent_name, unsigned long flags,
357 void __iomem *reg, u8 shift, u8 width, 377 void __iomem *reg, u8 shift, u8 width,
@@ -361,6 +381,7 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
361 void __iomem *reg, u8 shift, u8 width, 381 void __iomem *reg, u8 shift, u8 width,
362 u8 clk_divider_flags, const struct clk_div_table *table, 382 u8 clk_divider_flags, const struct clk_div_table *table,
363 spinlock_t *lock); 383 spinlock_t *lock);
384void clk_unregister_divider(struct clk *clk);
364 385
365/** 386/**
366 * struct clk_mux - multiplexer clock 387 * struct clk_mux - multiplexer clock
@@ -382,6 +403,8 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
382 * register, and mask of mux bits are in higher 16-bit of this register. 403 * register, and mask of mux bits are in higher 16-bit of this register.
383 * While setting the mux bits, higher 16-bit should also be updated to 404 * While setting the mux bits, higher 16-bit should also be updated to
384 * indicate changing mux bits. 405 * indicate changing mux bits.
406 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
407 * frequency.
385 */ 408 */
386struct clk_mux { 409struct clk_mux {
387 struct clk_hw hw; 410 struct clk_hw hw;
@@ -396,7 +419,8 @@ struct clk_mux {
396#define CLK_MUX_INDEX_ONE BIT(0) 419#define CLK_MUX_INDEX_ONE BIT(0)
397#define CLK_MUX_INDEX_BIT BIT(1) 420#define CLK_MUX_INDEX_BIT BIT(1)
398#define CLK_MUX_HIWORD_MASK BIT(2) 421#define CLK_MUX_HIWORD_MASK BIT(2)
399#define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */ 422#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
423#define CLK_MUX_ROUND_CLOSEST BIT(4)
400 424
401extern const struct clk_ops clk_mux_ops; 425extern const struct clk_ops clk_mux_ops;
402extern const struct clk_ops clk_mux_ro_ops; 426extern const struct clk_ops clk_mux_ro_ops;
@@ -411,6 +435,8 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name,
411 void __iomem *reg, u8 shift, u32 mask, 435 void __iomem *reg, u8 shift, u32 mask,
412 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 436 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
413 437
438void clk_unregister_mux(struct clk *clk);
439
414void of_fixed_factor_clk_setup(struct device_node *node); 440void of_fixed_factor_clk_setup(struct device_node *node);
415 441
416/** 442/**
@@ -550,15 +576,29 @@ bool __clk_is_prepared(struct clk *clk);
550bool __clk_is_enabled(struct clk *clk); 576bool __clk_is_enabled(struct clk *clk);
551struct clk *__clk_lookup(const char *name); 577struct clk *__clk_lookup(const char *name);
552long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, 578long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
579 unsigned long min_rate,
580 unsigned long max_rate,
553 unsigned long *best_parent_rate, 581 unsigned long *best_parent_rate,
554 struct clk_hw **best_parent_p); 582 struct clk_hw **best_parent_p);
583unsigned long __clk_determine_rate(struct clk_hw *core,
584 unsigned long rate,
585 unsigned long min_rate,
586 unsigned long max_rate);
587long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate,
588 unsigned long min_rate,
589 unsigned long max_rate,
590 unsigned long *best_parent_rate,
591 struct clk_hw **best_parent_p);
592
593static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
594{
595 dst->clk = src->clk;
596 dst->core = src->core;
597}
555 598
556/* 599/*
557 * FIXME clock api without lock protection 600 * FIXME clock api without lock protection
558 */ 601 */
559int __clk_prepare(struct clk *clk);
560void __clk_unprepare(struct clk *clk);
561void __clk_reparent(struct clk *clk, struct clk *new_parent);
562unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); 602unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
563 603
564struct of_device_id; 604struct of_device_id;
diff --git a/include/linux/clk.h b/include/linux/clk.h
index c7f258a81761..8381bbfbc308 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -302,6 +302,46 @@ long clk_round_rate(struct clk *clk, unsigned long rate);
302int clk_set_rate(struct clk *clk, unsigned long rate); 302int clk_set_rate(struct clk *clk, unsigned long rate);
303 303
304/** 304/**
305 * clk_has_parent - check if a clock is a possible parent for another
306 * @clk: clock source
307 * @parent: parent clock source
308 *
309 * This function can be used in drivers that need to check that a clock can be
310 * the parent of another without actually changing the parent.
311 *
312 * Returns true if @parent is a possible parent for @clk, false otherwise.
313 */
314bool clk_has_parent(struct clk *clk, struct clk *parent);
315
316/**
317 * clk_set_rate_range - set a rate range for a clock source
318 * @clk: clock source
319 * @min: desired minimum clock rate in Hz, inclusive
320 * @max: desired maximum clock rate in Hz, inclusive
321 *
322 * Returns success (0) or negative errno.
323 */
324int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max);
325
326/**
327 * clk_set_min_rate - set a minimum clock rate for a clock source
328 * @clk: clock source
329 * @rate: desired minimum clock rate in Hz, inclusive
330 *
331 * Returns success (0) or negative errno.
332 */
333int clk_set_min_rate(struct clk *clk, unsigned long rate);
334
335/**
336 * clk_set_max_rate - set a maximum clock rate for a clock source
337 * @clk: clock source
338 * @rate: desired maximum clock rate in Hz, inclusive
339 *
340 * Returns success (0) or negative errno.
341 */
342int clk_set_max_rate(struct clk *clk, unsigned long rate);
343
344/**
305 * clk_set_parent - set the parent clock source for this clock 345 * clk_set_parent - set the parent clock source for this clock
306 * @clk: clock source 346 * @clk: clock source
307 * @parent: parent clock source 347 * @parent: parent clock source
@@ -374,6 +414,11 @@ static inline long clk_round_rate(struct clk *clk, unsigned long rate)
374 return 0; 414 return 0;
375} 415}
376 416
417static inline bool clk_has_parent(struct clk *clk, struct clk *parent)
418{
419 return true;
420}
421
377static inline int clk_set_parent(struct clk *clk, struct clk *parent) 422static inline int clk_set_parent(struct clk *clk, struct clk *parent)
378{ 423{
379 return 0; 424 return 0;
diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
deleted file mode 100644
index aed28c4451d9..000000000000
--- a/include/linux/clk/sunxi.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright 2013 - Hans de Goede <hdegoede@redhat.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __LINUX_CLK_SUNXI_H_
16#define __LINUX_CLK_SUNXI_H_
17
18#include <linux/clk.h>
19
20void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output);
21
22#endif
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 3ca9fca827a2..19c4208f4752 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -120,6 +120,4 @@ static inline void tegra_cpu_clock_resume(void)
120} 120}
121#endif 121#endif
122 122
123void tegra_clocks_apply_init_table(void);
124
125#endif /* __LINUX_CLK_TEGRA_H_ */ 123#endif /* __LINUX_CLK_TEGRA_H_ */
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 55ef529a0dbf..67844003493d 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -15,6 +15,7 @@
15#ifndef __LINUX_CLK_TI_H__ 15#ifndef __LINUX_CLK_TI_H__
16#define __LINUX_CLK_TI_H__ 16#define __LINUX_CLK_TI_H__
17 17
18#include <linux/clk-provider.h>
18#include <linux/clkdev.h> 19#include <linux/clkdev.h>
19 20
20/** 21/**
@@ -217,6 +218,13 @@ struct ti_dt_clk {
217/* Maximum number of clock memmaps */ 218/* Maximum number of clock memmaps */
218#define CLK_MAX_MEMMAPS 4 219#define CLK_MAX_MEMMAPS 4
219 220
221/* Static memmap indices */
222enum {
223 TI_CLKM_CM = 0,
224 TI_CLKM_PRM,
225 TI_CLKM_SCRM,
226};
227
220typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *); 228typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
221 229
222/** 230/**
@@ -263,6 +271,8 @@ int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
263 u8 index); 271 u8 index);
264long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, 272long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
265 unsigned long rate, 273 unsigned long rate,
274 unsigned long min_rate,
275 unsigned long max_rate,
266 unsigned long *best_parent_rate, 276 unsigned long *best_parent_rate,
267 struct clk_hw **best_parent_clk); 277 struct clk_hw **best_parent_clk);
268unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 278unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
@@ -272,6 +282,8 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
272 unsigned long *parent_rate); 282 unsigned long *parent_rate);
273long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, 283long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
274 unsigned long rate, 284 unsigned long rate,
285 unsigned long min_rate,
286 unsigned long max_rate,
275 unsigned long *best_parent_rate, 287 unsigned long *best_parent_rate,
276 struct clk_hw **best_parent_clk); 288 struct clk_hw **best_parent_clk);
277u8 omap2_init_dpll_parent(struct clk_hw *hw); 289u8 omap2_init_dpll_parent(struct clk_hw *hw);
@@ -348,4 +360,17 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
348extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; 360extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
349extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; 361extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
350 362
363#ifdef CONFIG_ATAGS
364int omap3430_clk_legacy_init(void);
365int omap3430es1_clk_legacy_init(void);
366int omap36xx_clk_legacy_init(void);
367int am35xx_clk_legacy_init(void);
368#else
369static inline int omap3430_clk_legacy_init(void) { return -ENXIO; }
370static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; }
371static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; }
372static inline int am35xx_clk_legacy_init(void) { return -ENXIO; }
373#endif
374
375
351#endif 376#endif
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index d1ec10a940ff..1b45e4a0519b 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -202,7 +202,7 @@ static __always_inline void data_access_exceeds_word_size(void)
202{ 202{
203} 203}
204 204
205static __always_inline void __read_once_size(volatile void *p, void *res, int size) 205static __always_inline void __read_once_size(const volatile void *p, void *res, int size)
206{ 206{
207 switch (size) { 207 switch (size) {
208 case 1: *(__u8 *)res = *(volatile __u8 *)p; break; 208 case 1: *(__u8 *)res = *(volatile __u8 *)p; break;
@@ -259,10 +259,10 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s
259 */ 259 */
260 260
261#define READ_ONCE(x) \ 261#define READ_ONCE(x) \
262 ({ typeof(x) __val; __read_once_size(&x, &__val, sizeof(__val)); __val; }) 262 ({ union { typeof(x) __val; char __c[1]; } __u; __read_once_size(&(x), __u.__c, sizeof(x)); __u.__val; })
263 263
264#define WRITE_ONCE(x, val) \ 264#define WRITE_ONCE(x, val) \
265 ({ typeof(x) __val; __val = val; __write_once_size(&x, &__val, sizeof(__val)); __val; }) 265 ({ typeof(x) __val = (val); __write_once_size(&(x), &__val, sizeof(__val)); __val; })
266 266
267#endif /* __KERNEL__ */ 267#endif /* __KERNEL__ */
268 268
diff --git a/include/linux/dcache.h b/include/linux/dcache.h
index 92c08cf7670e..d8358799c594 100644
--- a/include/linux/dcache.h
+++ b/include/linux/dcache.h
@@ -215,13 +215,16 @@ struct dentry_operations {
215#define DCACHE_LRU_LIST 0x00080000 215#define DCACHE_LRU_LIST 0x00080000
216 216
217#define DCACHE_ENTRY_TYPE 0x00700000 217#define DCACHE_ENTRY_TYPE 0x00700000
218#define DCACHE_MISS_TYPE 0x00000000 /* Negative dentry */ 218#define DCACHE_MISS_TYPE 0x00000000 /* Negative dentry (maybe fallthru to nowhere) */
219#define DCACHE_DIRECTORY_TYPE 0x00100000 /* Normal directory */ 219#define DCACHE_WHITEOUT_TYPE 0x00100000 /* Whiteout dentry (stop pathwalk) */
220#define DCACHE_AUTODIR_TYPE 0x00200000 /* Lookupless directory (presumed automount) */ 220#define DCACHE_DIRECTORY_TYPE 0x00200000 /* Normal directory */
221#define DCACHE_SYMLINK_TYPE 0x00300000 /* Symlink */ 221#define DCACHE_AUTODIR_TYPE 0x00300000 /* Lookupless directory (presumed automount) */
222#define DCACHE_FILE_TYPE 0x00400000 /* Other file type */ 222#define DCACHE_REGULAR_TYPE 0x00400000 /* Regular file type (or fallthru to such) */
223#define DCACHE_SPECIAL_TYPE 0x00500000 /* Other file type (or fallthru to such) */
224#define DCACHE_SYMLINK_TYPE 0x00600000 /* Symlink (or fallthru to such) */
223 225
224#define DCACHE_MAY_FREE 0x00800000 226#define DCACHE_MAY_FREE 0x00800000
227#define DCACHE_FALLTHRU 0x01000000 /* Fall through to lower layer */
225 228
226extern seqlock_t rename_lock; 229extern seqlock_t rename_lock;
227 230
@@ -423,6 +426,16 @@ static inline unsigned __d_entry_type(const struct dentry *dentry)
423 return dentry->d_flags & DCACHE_ENTRY_TYPE; 426 return dentry->d_flags & DCACHE_ENTRY_TYPE;
424} 427}
425 428
429static inline bool d_is_miss(const struct dentry *dentry)
430{
431 return __d_entry_type(dentry) == DCACHE_MISS_TYPE;
432}
433
434static inline bool d_is_whiteout(const struct dentry *dentry)
435{
436 return __d_entry_type(dentry) == DCACHE_WHITEOUT_TYPE;
437}
438
426static inline bool d_can_lookup(const struct dentry *dentry) 439static inline bool d_can_lookup(const struct dentry *dentry)
427{ 440{
428 return __d_entry_type(dentry) == DCACHE_DIRECTORY_TYPE; 441 return __d_entry_type(dentry) == DCACHE_DIRECTORY_TYPE;
@@ -443,14 +456,25 @@ static inline bool d_is_symlink(const struct dentry *dentry)
443 return __d_entry_type(dentry) == DCACHE_SYMLINK_TYPE; 456 return __d_entry_type(dentry) == DCACHE_SYMLINK_TYPE;
444} 457}
445 458
459static inline bool d_is_reg(const struct dentry *dentry)
460{
461 return __d_entry_type(dentry) == DCACHE_REGULAR_TYPE;
462}
463
464static inline bool d_is_special(const struct dentry *dentry)
465{
466 return __d_entry_type(dentry) == DCACHE_SPECIAL_TYPE;
467}
468
446static inline bool d_is_file(const struct dentry *dentry) 469static inline bool d_is_file(const struct dentry *dentry)
447{ 470{
448 return __d_entry_type(dentry) == DCACHE_FILE_TYPE; 471 return d_is_reg(dentry) || d_is_special(dentry);
449} 472}
450 473
451static inline bool d_is_negative(const struct dentry *dentry) 474static inline bool d_is_negative(const struct dentry *dentry)
452{ 475{
453 return __d_entry_type(dentry) == DCACHE_MISS_TYPE; 476 // TODO: check d_is_whiteout(dentry) also.
477 return d_is_miss(dentry);
454} 478}
455 479
456static inline bool d_is_positive(const struct dentry *dentry) 480static inline bool d_is_positive(const struct dentry *dentry)
@@ -458,10 +482,75 @@ static inline bool d_is_positive(const struct dentry *dentry)
458 return !d_is_negative(dentry); 482 return !d_is_negative(dentry);
459} 483}
460 484
485extern void d_set_fallthru(struct dentry *dentry);
486
487static inline bool d_is_fallthru(const struct dentry *dentry)
488{
489 return dentry->d_flags & DCACHE_FALLTHRU;
490}
491
492
461extern int sysctl_vfs_cache_pressure; 493extern int sysctl_vfs_cache_pressure;
462 494
463static inline unsigned long vfs_pressure_ratio(unsigned long val) 495static inline unsigned long vfs_pressure_ratio(unsigned long val)
464{ 496{
465 return mult_frac(val, sysctl_vfs_cache_pressure, 100); 497 return mult_frac(val, sysctl_vfs_cache_pressure, 100);
466} 498}
499
500/**
501 * d_inode - Get the actual inode of this dentry
502 * @dentry: The dentry to query
503 *
504 * This is the helper normal filesystems should use to get at their own inodes
505 * in their own dentries and ignore the layering superimposed upon them.
506 */
507static inline struct inode *d_inode(const struct dentry *dentry)
508{
509 return dentry->d_inode;
510}
511
512/**
513 * d_inode_rcu - Get the actual inode of this dentry with ACCESS_ONCE()
514 * @dentry: The dentry to query
515 *
516 * This is the helper normal filesystems should use to get at their own inodes
517 * in their own dentries and ignore the layering superimposed upon them.
518 */
519static inline struct inode *d_inode_rcu(const struct dentry *dentry)
520{
521 return ACCESS_ONCE(dentry->d_inode);
522}
523
524/**
525 * d_backing_inode - Get upper or lower inode we should be using
526 * @upper: The upper layer
527 *
528 * This is the helper that should be used to get at the inode that will be used
529 * if this dentry were to be opened as a file. The inode may be on the upper
530 * dentry or it may be on a lower dentry pinned by the upper.
531 *
532 * Normal filesystems should not use this to access their own inodes.
533 */
534static inline struct inode *d_backing_inode(const struct dentry *upper)
535{
536 struct inode *inode = upper->d_inode;
537
538 return inode;
539}
540
541/**
542 * d_backing_dentry - Get upper or lower dentry we should be using
543 * @upper: The upper layer
544 *
545 * This is the helper that should be used to get the dentry of the inode that
546 * will be used if this dentry were opened as a file. It may be the upper
547 * dentry or it may be a lower dentry pinned by the upper.
548 *
549 * Normal filesystems should not use this to access their own dentries.
550 */
551static inline struct dentry *d_backing_dentry(struct dentry *upper)
552{
553 return upper;
554}
555
467#endif /* __LINUX_DCACHE_H */ 556#endif /* __LINUX_DCACHE_H */
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 40cd75e21ea2..b6997a0cb528 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -189,25 +189,6 @@ enum dma_ctrl_flags {
189}; 189};
190 190
191/** 191/**
192 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
193 * on a running channel.
194 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
195 * @DMA_PAUSE: pause ongoing transfers
196 * @DMA_RESUME: resume paused transfer
197 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
198 * that need to runtime reconfigure the slave channels (as opposed to passing
199 * configuration data in statically from the platform). An additional
200 * argument of struct dma_slave_config must be passed in with this
201 * command.
202 */
203enum dma_ctrl_cmd {
204 DMA_TERMINATE_ALL,
205 DMA_PAUSE,
206 DMA_RESUME,
207 DMA_SLAVE_CONFIG,
208};
209
210/**
211 * enum sum_check_bits - bit position of pq_check_flags 192 * enum sum_check_bits - bit position of pq_check_flags
212 */ 193 */
213enum sum_check_bits { 194enum sum_check_bits {
@@ -298,6 +279,9 @@ enum dma_slave_buswidth {
298 DMA_SLAVE_BUSWIDTH_3_BYTES = 3, 279 DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
299 DMA_SLAVE_BUSWIDTH_4_BYTES = 4, 280 DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
300 DMA_SLAVE_BUSWIDTH_8_BYTES = 8, 281 DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
282 DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
283 DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
284 DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
301}; 285};
302 286
303/** 287/**
@@ -336,9 +320,8 @@ enum dma_slave_buswidth {
336 * This struct is passed in as configuration data to a DMA engine 320 * This struct is passed in as configuration data to a DMA engine
337 * in order to set up a certain channel for DMA transport at runtime. 321 * in order to set up a certain channel for DMA transport at runtime.
338 * The DMA device/engine has to provide support for an additional 322 * The DMA device/engine has to provide support for an additional
339 * command in the channel config interface, DMA_SLAVE_CONFIG 323 * callback in the dma_device structure, device_config and this struct
340 * and this struct will then be passed in as an argument to the 324 * will then be passed in as an argument to the function.
341 * DMA engine device_control() function.
342 * 325 *
343 * The rationale for adding configuration information to this struct is as 326 * The rationale for adding configuration information to this struct is as
344 * follows: if it is likely that more than one DMA slave controllers in 327 * follows: if it is likely that more than one DMA slave controllers in
@@ -387,7 +370,7 @@ enum dma_residue_granularity {
387/* struct dma_slave_caps - expose capabilities of a slave channel only 370/* struct dma_slave_caps - expose capabilities of a slave channel only
388 * 371 *
389 * @src_addr_widths: bit mask of src addr widths the channel supports 372 * @src_addr_widths: bit mask of src addr widths the channel supports
390 * @dstn_addr_widths: bit mask of dstn addr widths the channel supports 373 * @dst_addr_widths: bit mask of dstn addr widths the channel supports
391 * @directions: bit mask of slave direction the channel supported 374 * @directions: bit mask of slave direction the channel supported
392 * since the enum dma_transfer_direction is not defined as bits for each 375 * since the enum dma_transfer_direction is not defined as bits for each
393 * type of direction, the dma controller should fill (1 << <TYPE>) and same 376 * type of direction, the dma controller should fill (1 << <TYPE>) and same
@@ -398,7 +381,7 @@ enum dma_residue_granularity {
398 */ 381 */
399struct dma_slave_caps { 382struct dma_slave_caps {
400 u32 src_addr_widths; 383 u32 src_addr_widths;
401 u32 dstn_addr_widths; 384 u32 dst_addr_widths;
402 u32 directions; 385 u32 directions;
403 bool cmd_pause; 386 bool cmd_pause;
404 bool cmd_terminate; 387 bool cmd_terminate;
@@ -594,6 +577,14 @@ struct dma_tx_state {
594 * @fill_align: alignment shift for memset operations 577 * @fill_align: alignment shift for memset operations
595 * @dev_id: unique device ID 578 * @dev_id: unique device ID
596 * @dev: struct device reference for dma mapping api 579 * @dev: struct device reference for dma mapping api
580 * @src_addr_widths: bit mask of src addr widths the device supports
581 * @dst_addr_widths: bit mask of dst addr widths the device supports
582 * @directions: bit mask of slave direction the device supports since
583 * the enum dma_transfer_direction is not defined as bits for
584 * each type of direction, the dma controller should fill (1 <<
585 * <TYPE>) and same should be checked by controller as well
586 * @residue_granularity: granularity of the transfer residue reported
587 * by tx_status
597 * @device_alloc_chan_resources: allocate resources and return the 588 * @device_alloc_chan_resources: allocate resources and return the
598 * number of allocated descriptors 589 * number of allocated descriptors
599 * @device_free_chan_resources: release DMA channel's resources 590 * @device_free_chan_resources: release DMA channel's resources
@@ -608,14 +599,19 @@ struct dma_tx_state {
608 * The function takes a buffer of size buf_len. The callback function will 599 * The function takes a buffer of size buf_len. The callback function will
609 * be called after period_len bytes have been transferred. 600 * be called after period_len bytes have been transferred.
610 * @device_prep_interleaved_dma: Transfer expression in a generic way. 601 * @device_prep_interleaved_dma: Transfer expression in a generic way.
611 * @device_control: manipulate all pending operations on a channel, returns 602 * @device_config: Pushes a new configuration to a channel, return 0 or an error
612 * zero or error code 603 * code
604 * @device_pause: Pauses any transfer happening on a channel. Returns
605 * 0 or an error code
606 * @device_resume: Resumes any transfer on a channel previously
607 * paused. Returns 0 or an error code
608 * @device_terminate_all: Aborts all transfers on a channel. Returns 0
609 * or an error code
613 * @device_tx_status: poll for transaction completion, the optional 610 * @device_tx_status: poll for transaction completion, the optional
614 * txstate parameter can be supplied with a pointer to get a 611 * txstate parameter can be supplied with a pointer to get a
615 * struct with auxiliary transfer status information, otherwise the call 612 * struct with auxiliary transfer status information, otherwise the call
616 * will just return a simple status code 613 * will just return a simple status code
617 * @device_issue_pending: push pending transactions to hardware 614 * @device_issue_pending: push pending transactions to hardware
618 * @device_slave_caps: return the slave channel capabilities
619 */ 615 */
620struct dma_device { 616struct dma_device {
621 617
@@ -635,14 +631,19 @@ struct dma_device {
635 int dev_id; 631 int dev_id;
636 struct device *dev; 632 struct device *dev;
637 633
634 u32 src_addr_widths;
635 u32 dst_addr_widths;
636 u32 directions;
637 enum dma_residue_granularity residue_granularity;
638
638 int (*device_alloc_chan_resources)(struct dma_chan *chan); 639 int (*device_alloc_chan_resources)(struct dma_chan *chan);
639 void (*device_free_chan_resources)(struct dma_chan *chan); 640 void (*device_free_chan_resources)(struct dma_chan *chan);
640 641
641 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( 642 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
642 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 643 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
643 size_t len, unsigned long flags); 644 size_t len, unsigned long flags);
644 struct dma_async_tx_descriptor *(*device_prep_dma_xor)( 645 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
645 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, 646 struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
646 unsigned int src_cnt, size_t len, unsigned long flags); 647 unsigned int src_cnt, size_t len, unsigned long flags);
647 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( 648 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
648 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, 649 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
@@ -674,31 +675,26 @@ struct dma_device {
674 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( 675 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
675 struct dma_chan *chan, struct dma_interleaved_template *xt, 676 struct dma_chan *chan, struct dma_interleaved_template *xt,
676 unsigned long flags); 677 unsigned long flags);
677 int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 678
678 unsigned long arg); 679 int (*device_config)(struct dma_chan *chan,
680 struct dma_slave_config *config);
681 int (*device_pause)(struct dma_chan *chan);
682 int (*device_resume)(struct dma_chan *chan);
683 int (*device_terminate_all)(struct dma_chan *chan);
679 684
680 enum dma_status (*device_tx_status)(struct dma_chan *chan, 685 enum dma_status (*device_tx_status)(struct dma_chan *chan,
681 dma_cookie_t cookie, 686 dma_cookie_t cookie,
682 struct dma_tx_state *txstate); 687 struct dma_tx_state *txstate);
683 void (*device_issue_pending)(struct dma_chan *chan); 688 void (*device_issue_pending)(struct dma_chan *chan);
684 int (*device_slave_caps)(struct dma_chan *chan, struct dma_slave_caps *caps);
685}; 689};
686 690
687static inline int dmaengine_device_control(struct dma_chan *chan,
688 enum dma_ctrl_cmd cmd,
689 unsigned long arg)
690{
691 if (chan->device->device_control)
692 return chan->device->device_control(chan, cmd, arg);
693
694 return -ENOSYS;
695}
696
697static inline int dmaengine_slave_config(struct dma_chan *chan, 691static inline int dmaengine_slave_config(struct dma_chan *chan,
698 struct dma_slave_config *config) 692 struct dma_slave_config *config)
699{ 693{
700 return dmaengine_device_control(chan, DMA_SLAVE_CONFIG, 694 if (chan->device->device_config)
701 (unsigned long)config); 695 return chan->device->device_config(chan, config);
696
697 return -ENOSYS;
702} 698}
703 699
704static inline bool is_slave_direction(enum dma_transfer_direction direction) 700static inline bool is_slave_direction(enum dma_transfer_direction direction)
@@ -765,34 +761,28 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg(
765 src_sg, src_nents, flags); 761 src_sg, src_nents, flags);
766} 762}
767 763
768static inline int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
769{
770 if (!chan || !caps)
771 return -EINVAL;
772
773 /* check if the channel supports slave transactions */
774 if (!test_bit(DMA_SLAVE, chan->device->cap_mask.bits))
775 return -ENXIO;
776
777 if (chan->device->device_slave_caps)
778 return chan->device->device_slave_caps(chan, caps);
779
780 return -ENXIO;
781}
782
783static inline int dmaengine_terminate_all(struct dma_chan *chan) 764static inline int dmaengine_terminate_all(struct dma_chan *chan)
784{ 765{
785 return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0); 766 if (chan->device->device_terminate_all)
767 return chan->device->device_terminate_all(chan);
768
769 return -ENOSYS;
786} 770}
787 771
788static inline int dmaengine_pause(struct dma_chan *chan) 772static inline int dmaengine_pause(struct dma_chan *chan)
789{ 773{
790 return dmaengine_device_control(chan, DMA_PAUSE, 0); 774 if (chan->device->device_pause)
775 return chan->device->device_pause(chan);
776
777 return -ENOSYS;
791} 778}
792 779
793static inline int dmaengine_resume(struct dma_chan *chan) 780static inline int dmaengine_resume(struct dma_chan *chan)
794{ 781{
795 return dmaengine_device_control(chan, DMA_RESUME, 0); 782 if (chan->device->device_resume)
783 return chan->device->device_resume(chan);
784
785 return -ENOSYS;
796} 786}
797 787
798static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, 788static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
@@ -1059,6 +1049,7 @@ struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
1059 const char *name); 1049 const char *name);
1060struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); 1050struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
1061void dma_release_channel(struct dma_chan *chan); 1051void dma_release_channel(struct dma_chan *chan);
1052int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
1062#else 1053#else
1063static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) 1054static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
1064{ 1055{
@@ -1093,6 +1084,11 @@ static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
1093static inline void dma_release_channel(struct dma_chan *chan) 1084static inline void dma_release_channel(struct dma_chan *chan)
1094{ 1085{
1095} 1086}
1087static inline int dma_get_slave_caps(struct dma_chan *chan,
1088 struct dma_slave_caps *caps)
1089{
1090 return -ENXIO;
1091}
1096#endif 1092#endif
1097 1093
1098/* --- DMA device --- */ 1094/* --- DMA device --- */
diff --git a/include/linux/fs.h b/include/linux/fs.h
index 447932aed1e1..b4d71b5e1ff2 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -968,9 +968,6 @@ struct file_lock_context {
968 struct list_head flc_flock; 968 struct list_head flc_flock;
969 struct list_head flc_posix; 969 struct list_head flc_posix;
970 struct list_head flc_lease; 970 struct list_head flc_lease;
971 int flc_flock_cnt;
972 int flc_posix_cnt;
973 int flc_lease_cnt;
974}; 971};
975 972
976/* The following constant reflects the upper bound of the file/locking space */ 973/* The following constant reflects the upper bound of the file/locking space */
diff --git a/include/linux/hid-sensor-hub.h b/include/linux/hid-sensor-hub.h
index 51f7ccadf923..4173a8fdad9e 100644
--- a/include/linux/hid-sensor-hub.h
+++ b/include/linux/hid-sensor-hub.h
@@ -33,6 +33,8 @@
33 * @units: Measurment unit for this attribute. 33 * @units: Measurment unit for this attribute.
34 * @unit_expo: Exponent used in the data. 34 * @unit_expo: Exponent used in the data.
35 * @size: Size in bytes for data size. 35 * @size: Size in bytes for data size.
36 * @logical_minimum: Logical minimum value for this attribute.
37 * @logical_maximum: Logical maximum value for this attribute.
36 */ 38 */
37struct hid_sensor_hub_attribute_info { 39struct hid_sensor_hub_attribute_info {
38 u32 usage_id; 40 u32 usage_id;
@@ -146,6 +148,7 @@ int sensor_hub_input_get_attribute_info(struct hid_sensor_hub_device *hsdev,
146 148
147/** 149/**
148* sensor_hub_input_attr_get_raw_value() - Synchronous read request 150* sensor_hub_input_attr_get_raw_value() - Synchronous read request
151* @hsdev: Hub device instance.
149* @usage_id: Attribute usage id of parent physical device as per spec 152* @usage_id: Attribute usage id of parent physical device as per spec
150* @attr_usage_id: Attribute usage id as per spec 153* @attr_usage_id: Attribute usage id as per spec
151* @report_id: Report id to look for 154* @report_id: Report id to look for
@@ -160,6 +163,7 @@ int sensor_hub_input_attr_get_raw_value(struct hid_sensor_hub_device *hsdev,
160 u32 attr_usage_id, u32 report_id); 163 u32 attr_usage_id, u32 report_id);
161/** 164/**
162* sensor_hub_set_feature() - Feature set request 165* sensor_hub_set_feature() - Feature set request
166* @hsdev: Hub device instance.
163* @report_id: Report id to look for 167* @report_id: Report id to look for
164* @field_index: Field index inside a report 168* @field_index: Field index inside a report
165* @value: Value to set 169* @value: Value to set
@@ -172,6 +176,7 @@ int sensor_hub_set_feature(struct hid_sensor_hub_device *hsdev, u32 report_id,
172 176
173/** 177/**
174* sensor_hub_get_feature() - Feature get request 178* sensor_hub_get_feature() - Feature get request
179* @hsdev: Hub device instance.
175* @report_id: Report id to look for 180* @report_id: Report id to look for
176* @field_index: Field index inside a report 181* @field_index: Field index inside a report
177* @value: Place holder for return value 182* @value: Place holder for return value
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 7c7695940ddd..f17da50402a4 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -130,8 +130,6 @@ extern s32 i2c_smbus_write_i2c_block_data(const struct i2c_client *client,
130 * @probe: Callback for device binding 130 * @probe: Callback for device binding
131 * @remove: Callback for device unbinding 131 * @remove: Callback for device unbinding
132 * @shutdown: Callback for device shutdown 132 * @shutdown: Callback for device shutdown
133 * @suspend: Callback for device suspend
134 * @resume: Callback for device resume
135 * @alert: Alert callback, for example for the SMBus alert protocol 133 * @alert: Alert callback, for example for the SMBus alert protocol
136 * @command: Callback for bus-wide signaling (optional) 134 * @command: Callback for bus-wide signaling (optional)
137 * @driver: Device driver model driver 135 * @driver: Device driver model driver
@@ -174,8 +172,6 @@ struct i2c_driver {
174 172
175 /* driver model interfaces that don't relate to enumeration */ 173 /* driver model interfaces that don't relate to enumeration */
176 void (*shutdown)(struct i2c_client *); 174 void (*shutdown)(struct i2c_client *);
177 int (*suspend)(struct i2c_client *, pm_message_t mesg);
178 int (*resume)(struct i2c_client *);
179 175
180 /* Alert callback, for example for the SMBus alert protocol. 176 /* Alert callback, for example for the SMBus alert protocol.
181 * The format and meaning of the data value depends on the protocol. 177 * The format and meaning of the data value depends on the protocol.
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h
index 420f77b34d02..e6a6aac451db 100644
--- a/include/linux/irqchip/mips-gic.h
+++ b/include/linux/irqchip/mips-gic.h
@@ -243,7 +243,6 @@ extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
243extern void gic_send_ipi(unsigned int intr); 243extern void gic_send_ipi(unsigned int intr);
244extern unsigned int plat_ipi_call_int_xlate(unsigned int); 244extern unsigned int plat_ipi_call_int_xlate(unsigned int);
245extern unsigned int plat_ipi_resched_int_xlate(unsigned int); 245extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
246extern unsigned int gic_get_timer_pending(void);
247extern int gic_get_c0_compare_int(void); 246extern int gic_get_c0_compare_int(void);
248extern int gic_get_c0_perfcount_int(void); 247extern int gic_get_c0_perfcount_int(void);
249#endif /* __LINUX_IRQCHIP_MIPS_GIC_H */ 248#endif /* __LINUX_IRQCHIP_MIPS_GIC_H */
diff --git a/include/linux/kdb.h b/include/linux/kdb.h
index 75ae2e2631fc..a19bcf9e762e 100644
--- a/include/linux/kdb.h
+++ b/include/linux/kdb.h
@@ -156,8 +156,14 @@ typedef enum {
156 KDB_REASON_SYSTEM_NMI, /* In NMI due to SYSTEM cmd; regs valid */ 156 KDB_REASON_SYSTEM_NMI, /* In NMI due to SYSTEM cmd; regs valid */
157} kdb_reason_t; 157} kdb_reason_t;
158 158
159enum kdb_msgsrc {
160 KDB_MSGSRC_INTERNAL, /* direct call to kdb_printf() */
161 KDB_MSGSRC_PRINTK, /* trapped from printk() */
162};
163
159extern int kdb_trap_printk; 164extern int kdb_trap_printk;
160extern __printf(1, 0) int vkdb_printf(const char *fmt, va_list args); 165extern __printf(2, 0) int vkdb_printf(enum kdb_msgsrc src, const char *fmt,
166 va_list args);
161extern __printf(1, 2) int kdb_printf(const char *, ...); 167extern __printf(1, 2) int kdb_printf(const char *, ...);
162typedef __printf(1, 2) int (*kdb_printf_t)(const char *, ...); 168typedef __printf(1, 2) int (*kdb_printf_t)(const char *, ...);
163 169
diff --git a/include/linux/lguest_launcher.h b/include/linux/lguest_launcher.h
index 495203ff221c..acd5b12565cc 100644
--- a/include/linux/lguest_launcher.h
+++ b/include/linux/lguest_launcher.h
@@ -8,52 +8,13 @@
8 * 8 *
9 * The Guest needs devices to do anything useful. Since we don't let it touch 9 * The Guest needs devices to do anything useful. Since we don't let it touch
10 * real devices (think of the damage it could do!) we provide virtual devices. 10 * real devices (think of the damage it could do!) we provide virtual devices.
11 * We could emulate a PCI bus with various devices on it, but that is a fairly 11 * We emulate a PCI bus with virtio devices on it; we used to have our own
12 * complex burden for the Host and suboptimal for the Guest, so we have our own 12 * lguest bus which was far simpler, but this tests the virtio 1.0 standard.
13 * simple lguest bus and we use "virtio" drivers. These drivers need a set of
14 * routines from us which will actually do the virtual I/O, but they handle all
15 * the net/block/console stuff themselves. This means that if we want to add
16 * a new device, we simply need to write a new virtio driver and create support
17 * for it in the Launcher: this code won't need to change.
18 * 13 *
19 * Virtio devices are also used by kvm, so we can simply reuse their optimized 14 * Virtio devices are also used by kvm, so we can simply reuse their optimized
20 * device drivers. And one day when everyone uses virtio, my plan will be 15 * device drivers. And one day when everyone uses virtio, my plan will be
21 * complete. Bwahahahah! 16 * complete. Bwahahahah!
22 *
23 * Devices are described by a simplified ID, a status byte, and some "config"
24 * bytes which describe this device's configuration. This is placed by the
25 * Launcher just above the top of physical memory:
26 */
27struct lguest_device_desc {
28 /* The device type: console, network, disk etc. Type 0 terminates. */
29 __u8 type;
30 /* The number of virtqueues (first in config array) */
31 __u8 num_vq;
32 /*
33 * The number of bytes of feature bits. Multiply by 2: one for host
34 * features and one for Guest acknowledgements.
35 */
36 __u8 feature_len;
37 /* The number of bytes of the config array after virtqueues. */
38 __u8 config_len;
39 /* A status byte, written by the Guest. */
40 __u8 status;
41 __u8 config[0];
42};
43
44/*D:135
45 * This is how we expect the device configuration field for a virtqueue
46 * to be laid out in config space.
47 */ 17 */
48struct lguest_vqconfig {
49 /* The number of entries in the virtio_ring */
50 __u16 num;
51 /* The interrupt we get when something happens. */
52 __u16 irq;
53 /* The page number of the virtio ring for this device. */
54 __u32 pfn;
55};
56/*:*/
57 18
58/* Write command first word is a request. */ 19/* Write command first word is a request. */
59enum lguest_req 20enum lguest_req
@@ -62,12 +23,22 @@ enum lguest_req
62 LHREQ_GETDMA, /* No longer used */ 23 LHREQ_GETDMA, /* No longer used */
63 LHREQ_IRQ, /* + irq */ 24 LHREQ_IRQ, /* + irq */
64 LHREQ_BREAK, /* No longer used */ 25 LHREQ_BREAK, /* No longer used */
65 LHREQ_EVENTFD, /* + address, fd. */ 26 LHREQ_EVENTFD, /* No longer used. */
27 LHREQ_GETREG, /* + offset within struct pt_regs (then read value). */
28 LHREQ_SETREG, /* + offset within struct pt_regs, value. */
29 LHREQ_TRAP, /* + trap number to deliver to guest. */
66}; 30};
67 31
68/* 32/*
69 * The alignment to use between consumer and producer parts of vring. 33 * This is what read() of the lguest fd populates. trap ==
70 * x86 pagesize for historical reasons. 34 * LGUEST_TRAP_ENTRY for an LHCALL_NOTIFY (addr is the
35 * argument), 14 for a page fault in the MMIO region (addr is
36 * the trap address, insn is the instruction), or 13 for a GPF
37 * (insn is the instruction).
71 */ 38 */
72#define LGUEST_VRING_ALIGN 4096 39struct lguest_pending {
40 __u8 trap;
41 __u8 insn[7];
42 __u32 addr;
43};
73#endif /* _LINUX_LGUEST_LAUNCHER */ 44#endif /* _LINUX_LGUEST_LAUNCHER */
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h
index 81589d176ae8..dfabd6db7ddf 100644
--- a/include/linux/mfd/axp20x.h
+++ b/include/linux/mfd/axp20x.h
@@ -124,10 +124,27 @@ enum {
124#define AXP288_PMIC_ADC_H 0x56 124#define AXP288_PMIC_ADC_H 0x56
125#define AXP288_PMIC_ADC_L 0x57 125#define AXP288_PMIC_ADC_L 0x57
126#define AXP288_ADC_TS_PIN_CTRL 0x84 126#define AXP288_ADC_TS_PIN_CTRL 0x84
127
128#define AXP288_PMIC_ADC_EN 0x84 127#define AXP288_PMIC_ADC_EN 0x84
129#define AXP288_FG_TUNE5 0xed
130 128
129/* Fuel Gauge */
130#define AXP288_FG_RDC1_REG 0xba
131#define AXP288_FG_RDC0_REG 0xbb
132#define AXP288_FG_OCVH_REG 0xbc
133#define AXP288_FG_OCVL_REG 0xbd
134#define AXP288_FG_OCV_CURVE_REG 0xc0
135#define AXP288_FG_DES_CAP1_REG 0xe0
136#define AXP288_FG_DES_CAP0_REG 0xe1
137#define AXP288_FG_CC_MTR1_REG 0xe2
138#define AXP288_FG_CC_MTR0_REG 0xe3
139#define AXP288_FG_OCV_CAP_REG 0xe4
140#define AXP288_FG_CC_CAP_REG 0xe5
141#define AXP288_FG_LOW_CAP_REG 0xe6
142#define AXP288_FG_TUNE0 0xe8
143#define AXP288_FG_TUNE1 0xe9
144#define AXP288_FG_TUNE2 0xea
145#define AXP288_FG_TUNE3 0xeb
146#define AXP288_FG_TUNE4 0xec
147#define AXP288_FG_TUNE5 0xed
131 148
132/* Regulators IDs */ 149/* Regulators IDs */
133enum { 150enum {
@@ -236,4 +253,26 @@ struct axp20x_dev {
236 const struct regmap_irq_chip *regmap_irq_chip; 253 const struct regmap_irq_chip *regmap_irq_chip;
237}; 254};
238 255
256#define BATTID_LEN 64
257#define OCV_CURVE_SIZE 32
258#define MAX_THERM_CURVE_SIZE 25
259#define PD_DEF_MIN_TEMP 0
260#define PD_DEF_MAX_TEMP 55
261
262struct axp20x_fg_pdata {
263 char battid[BATTID_LEN + 1];
264 int design_cap;
265 int min_volt;
266 int max_volt;
267 int max_temp;
268 int min_temp;
269 int cap1;
270 int cap0;
271 int rdc1;
272 int rdc0;
273 int ocv_curve[OCV_CURVE_SIZE];
274 int tcsz;
275 int thermistor_curve[MAX_THERM_CURVE_SIZE][2];
276};
277
239#endif /* __LINUX_MFD_AXP20X_H */ 278#endif /* __LINUX_MFD_AXP20X_H */
diff --git a/include/linux/mfd/da9063/core.h b/include/linux/mfd/da9063/core.h
index b92a3262f8f6..79f4d822ba13 100644
--- a/include/linux/mfd/da9063/core.h
+++ b/include/linux/mfd/da9063/core.h
@@ -36,6 +36,7 @@ enum da9063_models {
36enum da9063_variant_codes { 36enum da9063_variant_codes {
37 PMIC_DA9063_AD = 0x3, 37 PMIC_DA9063_AD = 0x3,
38 PMIC_DA9063_BB = 0x5, 38 PMIC_DA9063_BB = 0x5,
39 PMIC_DA9063_CA = 0x6,
39}; 40};
40 41
41/* Interrupts */ 42/* Interrupts */
diff --git a/include/linux/mfd/da9150/core.h b/include/linux/mfd/da9150/core.h
new file mode 100644
index 000000000000..76e668933a77
--- /dev/null
+++ b/include/linux/mfd/da9150/core.h
@@ -0,0 +1,68 @@
1/*
2 * DA9150 MFD Driver - Core Data
3 *
4 * Copyright (c) 2014 Dialog Semiconductor
5 *
6 * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifndef __DA9150_CORE_H
15#define __DA9150_CORE_H
16
17#include <linux/device.h>
18#include <linux/interrupt.h>
19#include <linux/regmap.h>
20
21/* I2C address paging */
22#define DA9150_REG_PAGE_SHIFT 8
23#define DA9150_REG_PAGE_MASK 0xFF
24
25/* IRQs */
26#define DA9150_NUM_IRQ_REGS 4
27#define DA9150_IRQ_VBUS 0
28#define DA9150_IRQ_CHG 1
29#define DA9150_IRQ_TCLASS 2
30#define DA9150_IRQ_TJUNC 3
31#define DA9150_IRQ_VFAULT 4
32#define DA9150_IRQ_CONF 5
33#define DA9150_IRQ_DAT 6
34#define DA9150_IRQ_DTYPE 7
35#define DA9150_IRQ_ID 8
36#define DA9150_IRQ_ADP 9
37#define DA9150_IRQ_SESS_END 10
38#define DA9150_IRQ_SESS_VLD 11
39#define DA9150_IRQ_FG 12
40#define DA9150_IRQ_GP 13
41#define DA9150_IRQ_TBAT 14
42#define DA9150_IRQ_GPIOA 15
43#define DA9150_IRQ_GPIOB 16
44#define DA9150_IRQ_GPIOC 17
45#define DA9150_IRQ_GPIOD 18
46#define DA9150_IRQ_GPADC 19
47#define DA9150_IRQ_WKUP 20
48
49struct da9150_pdata {
50 int irq_base;
51};
52
53struct da9150 {
54 struct device *dev;
55 struct regmap *regmap;
56 struct regmap_irq_chip_data *regmap_irq_data;
57 int irq;
58 int irq_base;
59};
60
61/* Device I/O */
62u8 da9150_reg_read(struct da9150 *da9150, u16 reg);
63void da9150_reg_write(struct da9150 *da9150, u16 reg, u8 val);
64void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val);
65
66void da9150_bulk_read(struct da9150 *da9150, u16 reg, int count, u8 *buf);
67void da9150_bulk_write(struct da9150 *da9150, u16 reg, int count, const u8 *buf);
68#endif /* __DA9150_CORE_H */
diff --git a/include/linux/mfd/da9150/registers.h b/include/linux/mfd/da9150/registers.h
new file mode 100644
index 000000000000..27ca6ee4d840
--- /dev/null
+++ b/include/linux/mfd/da9150/registers.h
@@ -0,0 +1,1155 @@
1/*
2 * DA9150 MFD Driver - Registers
3 *
4 * Copyright (c) 2014 Dialog Semiconductor
5 *
6 * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifndef __DA9150_REGISTERS_H
15#define __DA9150_REGISTERS_H
16
17#include <linux/bitops.h>
18
19/* Registers */
20#define DA9150_PAGE_CON 0x000
21#define DA9150_STATUS_A 0x068
22#define DA9150_STATUS_B 0x069
23#define DA9150_STATUS_C 0x06A
24#define DA9150_STATUS_D 0x06B
25#define DA9150_STATUS_E 0x06C
26#define DA9150_STATUS_F 0x06D
27#define DA9150_STATUS_G 0x06E
28#define DA9150_STATUS_H 0x06F
29#define DA9150_STATUS_I 0x070
30#define DA9150_STATUS_J 0x071
31#define DA9150_STATUS_K 0x072
32#define DA9150_STATUS_L 0x073
33#define DA9150_STATUS_N 0x074
34#define DA9150_FAULT_LOG_A 0x076
35#define DA9150_FAULT_LOG_B 0x077
36#define DA9150_EVENT_E 0x078
37#define DA9150_EVENT_F 0x079
38#define DA9150_EVENT_G 0x07A
39#define DA9150_EVENT_H 0x07B
40#define DA9150_IRQ_MASK_E 0x07C
41#define DA9150_IRQ_MASK_F 0x07D
42#define DA9150_IRQ_MASK_G 0x07E
43#define DA9150_IRQ_MASK_H 0x07F
44#define DA9150_PAGE_CON_1 0x080
45#define DA9150_CONFIG_A 0x0E0
46#define DA9150_CONFIG_B 0x0E1
47#define DA9150_CONFIG_C 0x0E2
48#define DA9150_CONFIG_D 0x0E3
49#define DA9150_CONFIG_E 0x0E4
50#define DA9150_CONTROL_A 0x0E5
51#define DA9150_CONTROL_B 0x0E6
52#define DA9150_CONTROL_C 0x0E7
53#define DA9150_GPIO_A_B 0x0E8
54#define DA9150_GPIO_C_D 0x0E9
55#define DA9150_GPIO_MODE_CONT 0x0EA
56#define DA9150_GPIO_CTRL_B 0x0EB
57#define DA9150_GPIO_CTRL_A 0x0EC
58#define DA9150_GPIO_CTRL_C 0x0ED
59#define DA9150_GPIO_CFG_A 0x0EE
60#define DA9150_GPIO_CFG_B 0x0EF
61#define DA9150_GPIO_CFG_C 0x0F0
62#define DA9150_GPADC_MAN 0x0F2
63#define DA9150_GPADC_RES_A 0x0F4
64#define DA9150_GPADC_RES_B 0x0F5
65#define DA9150_PAGE_CON_2 0x100
66#define DA9150_OTP_CONT_SHARED 0x101
67#define DA9150_INTERFACE_SHARED 0x105
68#define DA9150_CONFIG_A_SHARED 0x106
69#define DA9150_CONFIG_D_SHARED 0x109
70#define DA9150_ADETVB_CFG_C 0x150
71#define DA9150_ADETD_STAT 0x151
72#define DA9150_ADET_CMPSTAT 0x152
73#define DA9150_ADET_CTRL_A 0x153
74#define DA9150_ADETVB_CFG_B 0x154
75#define DA9150_ADETVB_CFG_A 0x155
76#define DA9150_ADETAC_CFG_A 0x156
77#define DA9150_ADDETAC_CFG_B 0x157
78#define DA9150_ADETAC_CFG_C 0x158
79#define DA9150_ADETAC_CFG_D 0x159
80#define DA9150_ADETVB_CFG_D 0x15A
81#define DA9150_ADETID_CFG_A 0x15B
82#define DA9150_ADET_RID_PT_CHG_H 0x15C
83#define DA9150_ADET_RID_PT_CHG_L 0x15D
84#define DA9150_PPR_TCTR_B 0x160
85#define DA9150_PPR_BKCTRL_A 0x163
86#define DA9150_PPR_BKCFG_A 0x164
87#define DA9150_PPR_BKCFG_B 0x165
88#define DA9150_PPR_CHGCTRL_A 0x166
89#define DA9150_PPR_CHGCTRL_B 0x167
90#define DA9150_PPR_CHGCTRL_C 0x168
91#define DA9150_PPR_TCTR_A 0x169
92#define DA9150_PPR_CHGCTRL_D 0x16A
93#define DA9150_PPR_CHGCTRL_E 0x16B
94#define DA9150_PPR_CHGCTRL_F 0x16C
95#define DA9150_PPR_CHGCTRL_G 0x16D
96#define DA9150_PPR_CHGCTRL_H 0x16E
97#define DA9150_PPR_CHGCTRL_I 0x16F
98#define DA9150_PPR_CHGCTRL_J 0x170
99#define DA9150_PPR_CHGCTRL_K 0x171
100#define DA9150_PPR_CHGCTRL_L 0x172
101#define DA9150_PPR_CHGCTRL_M 0x173
102#define DA9150_PPR_THYST_A 0x174
103#define DA9150_PPR_THYST_B 0x175
104#define DA9150_PPR_THYST_C 0x176
105#define DA9150_PPR_THYST_D 0x177
106#define DA9150_PPR_THYST_E 0x178
107#define DA9150_PPR_THYST_F 0x179
108#define DA9150_PPR_THYST_G 0x17A
109#define DA9150_PAGE_CON_3 0x180
110#define DA9150_PAGE_CON_4 0x200
111#define DA9150_PAGE_CON_5 0x280
112#define DA9150_PAGE_CON_6 0x300
113#define DA9150_COREBTLD_STAT_A 0x302
114#define DA9150_COREBTLD_CTRL_A 0x303
115#define DA9150_CORE_CONFIG_A 0x304
116#define DA9150_CORE_CONFIG_C 0x305
117#define DA9150_CORE_CONFIG_B 0x306
118#define DA9150_CORE_CFG_DATA_A 0x307
119#define DA9150_CORE_CFG_DATA_B 0x308
120#define DA9150_CORE_CMD_A 0x309
121#define DA9150_CORE_DATA_A 0x30A
122#define DA9150_CORE_DATA_B 0x30B
123#define DA9150_CORE_DATA_C 0x30C
124#define DA9150_CORE_DATA_D 0x30D
125#define DA9150_CORE2WIRE_STAT_A 0x310
126#define DA9150_CORE2WIRE_CTRL_A 0x311
127#define DA9150_FW_CTRL_A 0x312
128#define DA9150_FW_CTRL_C 0x313
129#define DA9150_FW_CTRL_D 0x314
130#define DA9150_FG_CTRL_A 0x315
131#define DA9150_FG_CTRL_B 0x316
132#define DA9150_FW_CTRL_E 0x317
133#define DA9150_FW_CTRL_B 0x318
134#define DA9150_GPADC_CMAN 0x320
135#define DA9150_GPADC_CRES_A 0x322
136#define DA9150_GPADC_CRES_B 0x323
137#define DA9150_CC_CFG_A 0x328
138#define DA9150_CC_CFG_B 0x329
139#define DA9150_CC_ICHG_RES_A 0x32A
140#define DA9150_CC_ICHG_RES_B 0x32B
141#define DA9150_CC_IAVG_RES_A 0x32C
142#define DA9150_CC_IAVG_RES_B 0x32D
143#define DA9150_TAUX_CTRL_A 0x330
144#define DA9150_TAUX_RELOAD_H 0x332
145#define DA9150_TAUX_RELOAD_L 0x333
146#define DA9150_TAUX_VALUE_H 0x334
147#define DA9150_TAUX_VALUE_L 0x335
148#define DA9150_AUX_DATA_0 0x338
149#define DA9150_AUX_DATA_1 0x339
150#define DA9150_AUX_DATA_2 0x33A
151#define DA9150_AUX_DATA_3 0x33B
152#define DA9150_BIF_CTRL 0x340
153#define DA9150_TBAT_CTRL_A 0x342
154#define DA9150_TBAT_CTRL_B 0x343
155#define DA9150_TBAT_RES_A 0x344
156#define DA9150_TBAT_RES_B 0x345
157
158/* DA9150_PAGE_CON = 0x000 */
159#define DA9150_PAGE_SHIFT 0
160#define DA9150_PAGE_MASK (0x3f << 0)
161#define DA9150_I2C_PAGE_SHIFT 1
162#define DA9150_I2C_PAGE_MASK (0x1f << 1)
163#define DA9150_WRITE_MODE_SHIFT 6
164#define DA9150_WRITE_MODE_MASK BIT(6)
165#define DA9150_REVERT_SHIFT 7
166#define DA9150_REVERT_MASK BIT(7)
167
168/* DA9150_STATUS_A = 0x068 */
169#define DA9150_WKUP_STAT_SHIFT 2
170#define DA9150_WKUP_STAT_MASK (0x0f << 2)
171#define DA9150_SLEEP_STAT_SHIFT 6
172#define DA9150_SLEEP_STAT_MASK (0x03 << 6)
173
174/* DA9150_STATUS_B = 0x069 */
175#define DA9150_VFAULT_STAT_SHIFT 0
176#define DA9150_VFAULT_STAT_MASK BIT(0)
177#define DA9150_TFAULT_STAT_SHIFT 1
178#define DA9150_TFAULT_STAT_MASK BIT(1)
179
180/* DA9150_STATUS_C = 0x06A */
181#define DA9150_VDD33_STAT_SHIFT 0
182#define DA9150_VDD33_STAT_MASK BIT(0)
183#define DA9150_VDD33_SLEEP_SHIFT 1
184#define DA9150_VDD33_SLEEP_MASK BIT(1)
185#define DA9150_LFOSC_STAT_SHIFT 7
186#define DA9150_LFOSC_STAT_MASK BIT(7)
187
188/* DA9150_STATUS_D = 0x06B */
189#define DA9150_GPIOA_STAT_SHIFT 0
190#define DA9150_GPIOA_STAT_MASK BIT(0)
191#define DA9150_GPIOB_STAT_SHIFT 1
192#define DA9150_GPIOB_STAT_MASK BIT(1)
193#define DA9150_GPIOC_STAT_SHIFT 2
194#define DA9150_GPIOC_STAT_MASK BIT(2)
195#define DA9150_GPIOD_STAT_SHIFT 3
196#define DA9150_GPIOD_STAT_MASK BIT(3)
197
198/* DA9150_STATUS_E = 0x06C */
199#define DA9150_DTYPE_SHIFT 0
200#define DA9150_DTYPE_MASK (0x1f << 0)
201#define DA9150_DTYPE_DT_NIL (0x00 << 0)
202#define DA9150_DTYPE_DT_USB_OTG BIT(0)
203#define DA9150_DTYPE_DT_USB_STD (0x02 << 0)
204#define DA9150_DTYPE_DT_USB_CHG (0x03 << 0)
205#define DA9150_DTYPE_DT_ACA_CHG (0x04 << 0)
206#define DA9150_DTYPE_DT_ACA_OTG (0x05 << 0)
207#define DA9150_DTYPE_DT_ACA_DOC (0x06 << 0)
208#define DA9150_DTYPE_DT_DED_CHG (0x07 << 0)
209#define DA9150_DTYPE_DT_CR5_CHG (0x08 << 0)
210#define DA9150_DTYPE_DT_CR4_CHG (0x0c << 0)
211#define DA9150_DTYPE_DT_PT_CHG (0x11 << 0)
212#define DA9150_DTYPE_DT_NN_ACC (0x16 << 0)
213#define DA9150_DTYPE_DT_NN_CHG (0x17 << 0)
214
215/* DA9150_STATUS_F = 0x06D */
216#define DA9150_SESS_VLD_SHIFT 0
217#define DA9150_SESS_VLD_MASK BIT(0)
218#define DA9150_ID_ERR_SHIFT 1
219#define DA9150_ID_ERR_MASK BIT(1)
220#define DA9150_PT_CHG_SHIFT 2
221#define DA9150_PT_CHG_MASK BIT(2)
222
223/* DA9150_STATUS_G = 0x06E */
224#define DA9150_RID_SHIFT 0
225#define DA9150_RID_MASK (0xff << 0)
226
227/* DA9150_STATUS_H = 0x06F */
228#define DA9150_VBUS_STAT_SHIFT 0
229#define DA9150_VBUS_STAT_MASK (0x07 << 0)
230#define DA9150_VBUS_STAT_OFF (0x00 << 0)
231#define DA9150_VBUS_STAT_WAIT BIT(0)
232#define DA9150_VBUS_STAT_CHG (0x02 << 0)
233#define DA9150_VBUS_TRED_SHIFT 3
234#define DA9150_VBUS_TRED_MASK BIT(3)
235#define DA9150_VBUS_DROP_STAT_SHIFT 4
236#define DA9150_VBUS_DROP_STAT_MASK (0x0f << 4)
237
238/* DA9150_STATUS_I = 0x070 */
239#define DA9150_VBUS_ISET_STAT_SHIFT 0
240#define DA9150_VBUS_ISET_STAT_MASK (0x1f << 0)
241#define DA9150_VBUS_OT_SHIFT 7
242#define DA9150_VBUS_OT_MASK BIT(7)
243
244/* DA9150_STATUS_J = 0x071 */
245#define DA9150_CHG_STAT_SHIFT 0
246#define DA9150_CHG_STAT_MASK (0x0f << 0)
247#define DA9150_CHG_STAT_OFF (0x00 << 0)
248#define DA9150_CHG_STAT_SUSP BIT(0)
249#define DA9150_CHG_STAT_ACT (0x02 << 0)
250#define DA9150_CHG_STAT_PRE (0x03 << 0)
251#define DA9150_CHG_STAT_CC (0x04 << 0)
252#define DA9150_CHG_STAT_CV (0x05 << 0)
253#define DA9150_CHG_STAT_FULL (0x06 << 0)
254#define DA9150_CHG_STAT_TEMP (0x07 << 0)
255#define DA9150_CHG_STAT_TIME (0x08 << 0)
256#define DA9150_CHG_STAT_BAT (0x09 << 0)
257#define DA9150_CHG_TEMP_SHIFT 4
258#define DA9150_CHG_TEMP_MASK (0x07 << 4)
259#define DA9150_CHG_TEMP_UNDER (0x06 << 4)
260#define DA9150_CHG_TEMP_OVER (0x07 << 4)
261#define DA9150_CHG_IEND_STAT_SHIFT 7
262#define DA9150_CHG_IEND_STAT_MASK BIT(7)
263
264/* DA9150_STATUS_K = 0x072 */
265#define DA9150_CHG_IAV_H_SHIFT 0
266#define DA9150_CHG_IAV_H_MASK (0xff << 0)
267
268/* DA9150_STATUS_L = 0x073 */
269#define DA9150_CHG_IAV_L_SHIFT 5
270#define DA9150_CHG_IAV_L_MASK (0x07 << 5)
271
272/* DA9150_STATUS_N = 0x074 */
273#define DA9150_CHG_TIME_SHIFT 1
274#define DA9150_CHG_TIME_MASK BIT(1)
275#define DA9150_CHG_TRED_SHIFT 2
276#define DA9150_CHG_TRED_MASK BIT(2)
277#define DA9150_CHG_TJUNC_CLASS_SHIFT 3
278#define DA9150_CHG_TJUNC_CLASS_MASK (0x07 << 3)
279#define DA9150_CHG_TJUNC_CLASS_6 (0x06 << 3)
280#define DA9150_EBS_STAT_SHIFT 6
281#define DA9150_EBS_STAT_MASK BIT(6)
282#define DA9150_CHG_BAT_REMOVED_SHIFT 7
283#define DA9150_CHG_BAT_REMOVED_MASK BIT(7)
284
285/* DA9150_FAULT_LOG_A = 0x076 */
286#define DA9150_TEMP_FAULT_SHIFT 0
287#define DA9150_TEMP_FAULT_MASK BIT(0)
288#define DA9150_VSYS_FAULT_SHIFT 1
289#define DA9150_VSYS_FAULT_MASK BIT(1)
290#define DA9150_START_FAULT_SHIFT 2
291#define DA9150_START_FAULT_MASK BIT(2)
292#define DA9150_EXT_FAULT_SHIFT 3
293#define DA9150_EXT_FAULT_MASK BIT(3)
294#define DA9150_POR_FAULT_SHIFT 4
295#define DA9150_POR_FAULT_MASK BIT(4)
296
297/* DA9150_FAULT_LOG_B = 0x077 */
298#define DA9150_VBUS_FAULT_SHIFT 0
299#define DA9150_VBUS_FAULT_MASK BIT(0)
300#define DA9150_OTG_FAULT_SHIFT 1
301#define DA9150_OTG_FAULT_MASK BIT(1)
302
303/* DA9150_EVENT_E = 0x078 */
304#define DA9150_E_VBUS_SHIFT 0
305#define DA9150_E_VBUS_MASK BIT(0)
306#define DA9150_E_CHG_SHIFT 1
307#define DA9150_E_CHG_MASK BIT(1)
308#define DA9150_E_TCLASS_SHIFT 2
309#define DA9150_E_TCLASS_MASK BIT(2)
310#define DA9150_E_TJUNC_SHIFT 3
311#define DA9150_E_TJUNC_MASK BIT(3)
312#define DA9150_E_VFAULT_SHIFT 4
313#define DA9150_E_VFAULT_MASK BIT(4)
314#define DA9150_EVENTS_H_SHIFT 5
315#define DA9150_EVENTS_H_MASK BIT(5)
316#define DA9150_EVENTS_G_SHIFT 6
317#define DA9150_EVENTS_G_MASK BIT(6)
318#define DA9150_EVENTS_F_SHIFT 7
319#define DA9150_EVENTS_F_MASK BIT(7)
320
321/* DA9150_EVENT_F = 0x079 */
322#define DA9150_E_CONF_SHIFT 0
323#define DA9150_E_CONF_MASK BIT(0)
324#define DA9150_E_DAT_SHIFT 1
325#define DA9150_E_DAT_MASK BIT(1)
326#define DA9150_E_DTYPE_SHIFT 3
327#define DA9150_E_DTYPE_MASK BIT(3)
328#define DA9150_E_ID_SHIFT 4
329#define DA9150_E_ID_MASK BIT(4)
330#define DA9150_E_ADP_SHIFT 5
331#define DA9150_E_ADP_MASK BIT(5)
332#define DA9150_E_SESS_END_SHIFT 6
333#define DA9150_E_SESS_END_MASK BIT(6)
334#define DA9150_E_SESS_VLD_SHIFT 7
335#define DA9150_E_SESS_VLD_MASK BIT(7)
336
337/* DA9150_EVENT_G = 0x07A */
338#define DA9150_E_FG_SHIFT 0
339#define DA9150_E_FG_MASK BIT(0)
340#define DA9150_E_GP_SHIFT 1
341#define DA9150_E_GP_MASK BIT(1)
342#define DA9150_E_TBAT_SHIFT 2
343#define DA9150_E_TBAT_MASK BIT(2)
344#define DA9150_E_GPIOA_SHIFT 3
345#define DA9150_E_GPIOA_MASK BIT(3)
346#define DA9150_E_GPIOB_SHIFT 4
347#define DA9150_E_GPIOB_MASK BIT(4)
348#define DA9150_E_GPIOC_SHIFT 5
349#define DA9150_E_GPIOC_MASK BIT(5)
350#define DA9150_E_GPIOD_SHIFT 6
351#define DA9150_E_GPIOD_MASK BIT(6)
352#define DA9150_E_GPADC_SHIFT 7
353#define DA9150_E_GPADC_MASK BIT(7)
354
355/* DA9150_EVENT_H = 0x07B */
356#define DA9150_E_WKUP_SHIFT 0
357#define DA9150_E_WKUP_MASK BIT(0)
358
359/* DA9150_IRQ_MASK_E = 0x07C */
360#define DA9150_M_VBUS_SHIFT 0
361#define DA9150_M_VBUS_MASK BIT(0)
362#define DA9150_M_CHG_SHIFT 1
363#define DA9150_M_CHG_MASK BIT(1)
364#define DA9150_M_TJUNC_SHIFT 3
365#define DA9150_M_TJUNC_MASK BIT(3)
366#define DA9150_M_VFAULT_SHIFT 4
367#define DA9150_M_VFAULT_MASK BIT(4)
368
369/* DA9150_IRQ_MASK_F = 0x07D */
370#define DA9150_M_CONF_SHIFT 0
371#define DA9150_M_CONF_MASK BIT(0)
372#define DA9150_M_DAT_SHIFT 1
373#define DA9150_M_DAT_MASK BIT(1)
374#define DA9150_M_DTYPE_SHIFT 3
375#define DA9150_M_DTYPE_MASK BIT(3)
376#define DA9150_M_ID_SHIFT 4
377#define DA9150_M_ID_MASK BIT(4)
378#define DA9150_M_ADP_SHIFT 5
379#define DA9150_M_ADP_MASK BIT(5)
380#define DA9150_M_SESS_END_SHIFT 6
381#define DA9150_M_SESS_END_MASK BIT(6)
382#define DA9150_M_SESS_VLD_SHIFT 7
383#define DA9150_M_SESS_VLD_MASK BIT(7)
384
385/* DA9150_IRQ_MASK_G = 0x07E */
386#define DA9150_M_FG_SHIFT 0
387#define DA9150_M_FG_MASK BIT(0)
388#define DA9150_M_GP_SHIFT 1
389#define DA9150_M_GP_MASK BIT(1)
390#define DA9150_M_TBAT_SHIFT 2
391#define DA9150_M_TBAT_MASK BIT(2)
392#define DA9150_M_GPIOA_SHIFT 3
393#define DA9150_M_GPIOA_MASK BIT(3)
394#define DA9150_M_GPIOB_SHIFT 4
395#define DA9150_M_GPIOB_MASK BIT(4)
396#define DA9150_M_GPIOC_SHIFT 5
397#define DA9150_M_GPIOC_MASK BIT(5)
398#define DA9150_M_GPIOD_SHIFT 6
399#define DA9150_M_GPIOD_MASK BIT(6)
400#define DA9150_M_GPADC_SHIFT 7
401#define DA9150_M_GPADC_MASK BIT(7)
402
403/* DA9150_IRQ_MASK_H = 0x07F */
404#define DA9150_M_WKUP_SHIFT 0
405#define DA9150_M_WKUP_MASK BIT(0)
406
407/* DA9150_PAGE_CON_1 = 0x080 */
408#define DA9150_PAGE_SHIFT 0
409#define DA9150_PAGE_MASK (0x3f << 0)
410#define DA9150_WRITE_MODE_SHIFT 6
411#define DA9150_WRITE_MODE_MASK BIT(6)
412#define DA9150_REVERT_SHIFT 7
413#define DA9150_REVERT_MASK BIT(7)
414
415/* DA9150_CONFIG_A = 0x0E0 */
416#define DA9150_RESET_DUR_SHIFT 0
417#define DA9150_RESET_DUR_MASK (0x03 << 0)
418#define DA9150_RESET_EXT_SHIFT 2
419#define DA9150_RESET_EXT_MASK (0x03 << 2)
420#define DA9150_START_MAX_SHIFT 4
421#define DA9150_START_MAX_MASK (0x03 << 4)
422#define DA9150_PS_WAIT_EN_SHIFT 6
423#define DA9150_PS_WAIT_EN_MASK BIT(6)
424#define DA9150_PS_DISABLE_DIRECT_SHIFT 7
425#define DA9150_PS_DISABLE_DIRECT_MASK BIT(7)
426
427/* DA9150_CONFIG_B = 0x0E1 */
428#define DA9150_VFAULT_ADJ_SHIFT 0
429#define DA9150_VFAULT_ADJ_MASK (0x0f << 0)
430#define DA9150_VFAULT_HYST_SHIFT 4
431#define DA9150_VFAULT_HYST_MASK (0x07 << 4)
432#define DA9150_VFAULT_EN_SHIFT 7
433#define DA9150_VFAULT_EN_MASK BIT(7)
434
435/* DA9150_CONFIG_C = 0x0E2 */
436#define DA9150_VSYS_MIN_SHIFT 3
437#define DA9150_VSYS_MIN_MASK (0x1f << 3)
438
439/* DA9150_CONFIG_D = 0x0E3 */
440#define DA9150_LFOSC_EXT_SHIFT 0
441#define DA9150_LFOSC_EXT_MASK BIT(0)
442#define DA9150_VDD33_DWN_SHIFT 1
443#define DA9150_VDD33_DWN_MASK BIT(1)
444#define DA9150_WKUP_PM_EN_SHIFT 2
445#define DA9150_WKUP_PM_EN_MASK BIT(2)
446#define DA9150_WKUP_CE_SEL_SHIFT 3
447#define DA9150_WKUP_CE_SEL_MASK (0x03 << 3)
448#define DA9150_WKUP_CLK32K_EN_SHIFT 5
449#define DA9150_WKUP_CLK32K_EN_MASK BIT(5)
450#define DA9150_DISABLE_DEL_SHIFT 7
451#define DA9150_DISABLE_DEL_MASK BIT(7)
452
453/* DA9150_CONFIG_E = 0x0E4 */
454#define DA9150_PM_SPKSUP_DIS_SHIFT 0
455#define DA9150_PM_SPKSUP_DIS_MASK BIT(0)
456#define DA9150_PM_MERGE_SHIFT 1
457#define DA9150_PM_MERGE_MASK BIT(1)
458#define DA9150_PM_SR_OFF_SHIFT 2
459#define DA9150_PM_SR_OFF_MASK BIT(2)
460#define DA9150_PM_TIMEOUT_EN_SHIFT 3
461#define DA9150_PM_TIMEOUT_EN_MASK BIT(3)
462#define DA9150_PM_DLY_SEL_SHIFT 4
463#define DA9150_PM_DLY_SEL_MASK (0x07 << 4)
464#define DA9150_PM_OUT_DLY_SEL_SHIFT 7
465#define DA9150_PM_OUT_DLY_SEL_MASK BIT(7)
466
467/* DA9150_CONTROL_A = 0x0E5 */
468#define DA9150_VDD33_SL_SHIFT 0
469#define DA9150_VDD33_SL_MASK BIT(0)
470#define DA9150_VDD33_LPM_SHIFT 1
471#define DA9150_VDD33_LPM_MASK (0x03 << 1)
472#define DA9150_VDD33_EN_SHIFT 3
473#define DA9150_VDD33_EN_MASK BIT(3)
474#define DA9150_GPI_LPM_SHIFT 6
475#define DA9150_GPI_LPM_MASK BIT(6)
476#define DA9150_PM_IF_LPM_SHIFT 7
477#define DA9150_PM_IF_LPM_MASK BIT(7)
478
479/* DA9150_CONTROL_B = 0x0E6 */
480#define DA9150_LPM_SHIFT 0
481#define DA9150_LPM_MASK BIT(0)
482#define DA9150_RESET_SHIFT 1
483#define DA9150_RESET_MASK BIT(1)
484#define DA9150_RESET_USRCONF_EN_SHIFT 2
485#define DA9150_RESET_USRCONF_EN_MASK BIT(2)
486
487/* DA9150_CONTROL_C = 0x0E7 */
488#define DA9150_DISABLE_SHIFT 0
489#define DA9150_DISABLE_MASK BIT(0)
490
491/* DA9150_GPIO_A_B = 0x0E8 */
492#define DA9150_GPIOA_PIN_SHIFT 0
493#define DA9150_GPIOA_PIN_MASK (0x07 << 0)
494#define DA9150_GPIOA_PIN_GPI (0x00 << 0)
495#define DA9150_GPIOA_PIN_GPO_OD BIT(0)
496#define DA9150_GPIOA_TYPE_SHIFT 3
497#define DA9150_GPIOA_TYPE_MASK BIT(3)
498#define DA9150_GPIOB_PIN_SHIFT 4
499#define DA9150_GPIOB_PIN_MASK (0x07 << 4)
500#define DA9150_GPIOB_PIN_GPI (0x00 << 4)
501#define DA9150_GPIOB_PIN_GPO_OD BIT(4)
502#define DA9150_GPIOB_TYPE_SHIFT 7
503#define DA9150_GPIOB_TYPE_MASK BIT(7)
504
505/* DA9150_GPIO_C_D = 0x0E9 */
506#define DA9150_GPIOC_PIN_SHIFT 0
507#define DA9150_GPIOC_PIN_MASK (0x07 << 0)
508#define DA9150_GPIOC_PIN_GPI (0x00 << 0)
509#define DA9150_GPIOC_PIN_GPO_OD BIT(0)
510#define DA9150_GPIOC_TYPE_SHIFT 3
511#define DA9150_GPIOC_TYPE_MASK BIT(3)
512#define DA9150_GPIOD_PIN_SHIFT 4
513#define DA9150_GPIOD_PIN_MASK (0x07 << 4)
514#define DA9150_GPIOD_PIN_GPI (0x00 << 4)
515#define DA9150_GPIOD_PIN_GPO_OD BIT(4)
516#define DA9150_GPIOD_TYPE_SHIFT 7
517#define DA9150_GPIOD_TYPE_MASK BIT(7)
518
519/* DA9150_GPIO_MODE_CONT = 0x0EA */
520#define DA9150_GPIOA_MODE_SHIFT 0
521#define DA9150_GPIOA_MODE_MASK BIT(0)
522#define DA9150_GPIOB_MODE_SHIFT 1
523#define DA9150_GPIOB_MODE_MASK BIT(1)
524#define DA9150_GPIOC_MODE_SHIFT 2
525#define DA9150_GPIOC_MODE_MASK BIT(2)
526#define DA9150_GPIOD_MODE_SHIFT 3
527#define DA9150_GPIOD_MODE_MASK BIT(3)
528#define DA9150_GPIOA_CONT_SHIFT 4
529#define DA9150_GPIOA_CONT_MASK BIT(4)
530#define DA9150_GPIOB_CONT_SHIFT 5
531#define DA9150_GPIOB_CONT_MASK BIT(5)
532#define DA9150_GPIOC_CONT_SHIFT 6
533#define DA9150_GPIOC_CONT_MASK BIT(6)
534#define DA9150_GPIOD_CONT_SHIFT 7
535#define DA9150_GPIOD_CONT_MASK BIT(7)
536
537/* DA9150_GPIO_CTRL_B = 0x0EB */
538#define DA9150_WAKE_PIN_SHIFT 0
539#define DA9150_WAKE_PIN_MASK (0x03 << 0)
540#define DA9150_WAKE_MODE_SHIFT 2
541#define DA9150_WAKE_MODE_MASK BIT(2)
542#define DA9150_WAKE_CONT_SHIFT 3
543#define DA9150_WAKE_CONT_MASK BIT(3)
544#define DA9150_WAKE_DLY_SHIFT 4
545#define DA9150_WAKE_DLY_MASK BIT(4)
546
547/* DA9150_GPIO_CTRL_A = 0x0EC */
548#define DA9150_GPIOA_ANAEN_SHIFT 0
549#define DA9150_GPIOA_ANAEN_MASK BIT(0)
550#define DA9150_GPIOB_ANAEN_SHIFT 1
551#define DA9150_GPIOB_ANAEN_MASK BIT(1)
552#define DA9150_GPIOC_ANAEN_SHIFT 2
553#define DA9150_GPIOC_ANAEN_MASK BIT(2)
554#define DA9150_GPIOD_ANAEN_SHIFT 3
555#define DA9150_GPIOD_ANAEN_MASK BIT(3)
556#define DA9150_GPIO_ANAEN 0x01
557#define DA9150_GPIO_ANAEN_MASK 0x0F
558#define DA9150_CHGLED_PIN_SHIFT 5
559#define DA9150_CHGLED_PIN_MASK (0x07 << 5)
560
561/* DA9150_GPIO_CTRL_C = 0x0ED */
562#define DA9150_CHGBL_DUR_SHIFT 0
563#define DA9150_CHGBL_DUR_MASK (0x03 << 0)
564#define DA9150_CHGBL_DBL_SHIFT 2
565#define DA9150_CHGBL_DBL_MASK BIT(2)
566#define DA9150_CHGBL_FRQ_SHIFT 3
567#define DA9150_CHGBL_FRQ_MASK (0x03 << 3)
568#define DA9150_CHGBL_FLKR_SHIFT 5
569#define DA9150_CHGBL_FLKR_MASK BIT(5)
570
571/* DA9150_GPIO_CFG_A = 0x0EE */
572#define DA9150_CE_LPM_DEB_SHIFT 0
573#define DA9150_CE_LPM_DEB_MASK (0x07 << 0)
574
575/* DA9150_GPIO_CFG_B = 0x0EF */
576#define DA9150_GPIOA_PUPD_SHIFT 0
577#define DA9150_GPIOA_PUPD_MASK BIT(0)
578#define DA9150_GPIOB_PUPD_SHIFT 1
579#define DA9150_GPIOB_PUPD_MASK BIT(1)
580#define DA9150_GPIOC_PUPD_SHIFT 2
581#define DA9150_GPIOC_PUPD_MASK BIT(2)
582#define DA9150_GPIOD_PUPD_SHIFT 3
583#define DA9150_GPIOD_PUPD_MASK BIT(3)
584#define DA9150_GPIO_PUPD_MASK (0xF << 0)
585#define DA9150_GPI_DEB_SHIFT 4
586#define DA9150_GPI_DEB_MASK (0x07 << 4)
587#define DA9150_LPM_EN_SHIFT 7
588#define DA9150_LPM_EN_MASK BIT(7)
589
590/* DA9150_GPIO_CFG_C = 0x0F0 */
591#define DA9150_GPI_V_SHIFT 0
592#define DA9150_GPI_V_MASK BIT(0)
593#define DA9150_VDDIO_INT_SHIFT 1
594#define DA9150_VDDIO_INT_MASK BIT(1)
595#define DA9150_FAULT_PIN_SHIFT 3
596#define DA9150_FAULT_PIN_MASK (0x07 << 3)
597#define DA9150_FAULT_TYPE_SHIFT 6
598#define DA9150_FAULT_TYPE_MASK BIT(6)
599#define DA9150_NIRQ_PUPD_SHIFT 7
600#define DA9150_NIRQ_PUPD_MASK BIT(7)
601
602/* DA9150_GPADC_MAN = 0x0F2 */
603#define DA9150_GPADC_EN_SHIFT 0
604#define DA9150_GPADC_EN_MASK BIT(0)
605#define DA9150_GPADC_MUX_SHIFT 1
606#define DA9150_GPADC_MUX_MASK (0x1f << 1)
607
608/* DA9150_GPADC_RES_A = 0x0F4 */
609#define DA9150_GPADC_RES_H_SHIFT 0
610#define DA9150_GPADC_RES_H_MASK (0xff << 0)
611
612/* DA9150_GPADC_RES_B = 0x0F5 */
613#define DA9150_GPADC_RUN_SHIFT 0
614#define DA9150_GPADC_RUN_MASK BIT(0)
615#define DA9150_GPADC_RES_L_SHIFT 6
616#define DA9150_GPADC_RES_L_MASK (0x03 << 6)
617#define DA9150_GPADC_RES_L_BITS 2
618
619/* DA9150_PAGE_CON_2 = 0x100 */
620#define DA9150_PAGE_SHIFT 0
621#define DA9150_PAGE_MASK (0x3f << 0)
622#define DA9150_WRITE_MODE_SHIFT 6
623#define DA9150_WRITE_MODE_MASK BIT(6)
624#define DA9150_REVERT_SHIFT 7
625#define DA9150_REVERT_MASK BIT(7)
626
627/* DA9150_OTP_CONT_SHARED = 0x101 */
628#define DA9150_PC_DONE_SHIFT 3
629#define DA9150_PC_DONE_MASK BIT(3)
630
631/* DA9150_INTERFACE_SHARED = 0x105 */
632#define DA9150_IF_BASE_ADDR_SHIFT 4
633#define DA9150_IF_BASE_ADDR_MASK (0x0f << 4)
634
635/* DA9150_CONFIG_A_SHARED = 0x106 */
636#define DA9150_NIRQ_VDD_SHIFT 1
637#define DA9150_NIRQ_VDD_MASK BIT(1)
638#define DA9150_NIRQ_PIN_SHIFT 2
639#define DA9150_NIRQ_PIN_MASK BIT(2)
640#define DA9150_NIRQ_TYPE_SHIFT 3
641#define DA9150_NIRQ_TYPE_MASK BIT(3)
642#define DA9150_PM_IF_V_SHIFT 4
643#define DA9150_PM_IF_V_MASK BIT(4)
644#define DA9150_PM_IF_FMP_SHIFT 5
645#define DA9150_PM_IF_FMP_MASK BIT(5)
646#define DA9150_PM_IF_HSM_SHIFT 6
647#define DA9150_PM_IF_HSM_MASK BIT(6)
648
649/* DA9150_CONFIG_D_SHARED = 0x109 */
650#define DA9150_NIRQ_MODE_SHIFT 1
651#define DA9150_NIRQ_MODE_MASK BIT(1)
652
653/* DA9150_ADETVB_CFG_C = 0x150 */
654#define DA9150_TADP_RISE_SHIFT 0
655#define DA9150_TADP_RISE_MASK (0xff << 0)
656
657/* DA9150_ADETD_STAT = 0x151 */
658#define DA9150_DCD_STAT_SHIFT 0
659#define DA9150_DCD_STAT_MASK BIT(0)
660#define DA9150_PCD_STAT_SHIFT 1
661#define DA9150_PCD_STAT_MASK (0x03 << 1)
662#define DA9150_SCD_STAT_SHIFT 3
663#define DA9150_SCD_STAT_MASK (0x03 << 3)
664#define DA9150_DP_STAT_SHIFT 5
665#define DA9150_DP_STAT_MASK BIT(5)
666#define DA9150_DM_STAT_SHIFT 6
667#define DA9150_DM_STAT_MASK BIT(6)
668
669/* DA9150_ADET_CMPSTAT = 0x152 */
670#define DA9150_DP_COMP_SHIFT 1
671#define DA9150_DP_COMP_MASK BIT(1)
672#define DA9150_DM_COMP_SHIFT 2
673#define DA9150_DM_COMP_MASK BIT(2)
674#define DA9150_ADP_SNS_COMP_SHIFT 3
675#define DA9150_ADP_SNS_COMP_MASK BIT(3)
676#define DA9150_ADP_PRB_COMP_SHIFT 4
677#define DA9150_ADP_PRB_COMP_MASK BIT(4)
678#define DA9150_ID_COMP_SHIFT 5
679#define DA9150_ID_COMP_MASK BIT(5)
680
681/* DA9150_ADET_CTRL_A = 0x153 */
682#define DA9150_AID_DAT_SHIFT 0
683#define DA9150_AID_DAT_MASK BIT(0)
684#define DA9150_AID_ID_SHIFT 1
685#define DA9150_AID_ID_MASK BIT(1)
686#define DA9150_AID_TRIG_SHIFT 2
687#define DA9150_AID_TRIG_MASK BIT(2)
688
689/* DA9150_ADETVB_CFG_B = 0x154 */
690#define DA9150_VB_MODE_SHIFT 0
691#define DA9150_VB_MODE_MASK (0x03 << 0)
692#define DA9150_VB_MODE_VB_SESS BIT(0)
693
694#define DA9150_TADP_PRB_SHIFT 2
695#define DA9150_TADP_PRB_MASK BIT(2)
696#define DA9150_DAT_RPD_EXT_SHIFT 5
697#define DA9150_DAT_RPD_EXT_MASK BIT(5)
698#define DA9150_CONF_RPD_SHIFT 6
699#define DA9150_CONF_RPD_MASK BIT(6)
700#define DA9150_CONF_SRP_SHIFT 7
701#define DA9150_CONF_SRP_MASK BIT(7)
702
703/* DA9150_ADETVB_CFG_A = 0x155 */
704#define DA9150_AID_MODE_SHIFT 0
705#define DA9150_AID_MODE_MASK (0x03 << 0)
706#define DA9150_AID_EXT_POL_SHIFT 2
707#define DA9150_AID_EXT_POL_MASK BIT(2)
708
709/* DA9150_ADETAC_CFG_A = 0x156 */
710#define DA9150_ISET_CDP_SHIFT 0
711#define DA9150_ISET_CDP_MASK (0x1f << 0)
712#define DA9150_CONF_DBP_SHIFT 5
713#define DA9150_CONF_DBP_MASK BIT(5)
714
715/* DA9150_ADDETAC_CFG_B = 0x157 */
716#define DA9150_ISET_DCHG_SHIFT 0
717#define DA9150_ISET_DCHG_MASK (0x1f << 0)
718#define DA9150_CONF_GPIOA_SHIFT 5
719#define DA9150_CONF_GPIOA_MASK BIT(5)
720#define DA9150_CONF_GPIOB_SHIFT 6
721#define DA9150_CONF_GPIOB_MASK BIT(6)
722#define DA9150_AID_VB_SHIFT 7
723#define DA9150_AID_VB_MASK BIT(7)
724
725/* DA9150_ADETAC_CFG_C = 0x158 */
726#define DA9150_ISET_DEF_SHIFT 0
727#define DA9150_ISET_DEF_MASK (0x1f << 0)
728#define DA9150_CONF_MODE_SHIFT 5
729#define DA9150_CONF_MODE_MASK (0x03 << 5)
730#define DA9150_AID_CR_DIS_SHIFT 7
731#define DA9150_AID_CR_DIS_MASK BIT(7)
732
733/* DA9150_ADETAC_CFG_D = 0x159 */
734#define DA9150_ISET_UNIT_SHIFT 0
735#define DA9150_ISET_UNIT_MASK (0x1f << 0)
736#define DA9150_AID_UNCLAMP_SHIFT 5
737#define DA9150_AID_UNCLAMP_MASK BIT(5)
738
739/* DA9150_ADETVB_CFG_D = 0x15A */
740#define DA9150_ID_MODE_SHIFT 0
741#define DA9150_ID_MODE_MASK (0x03 << 0)
742#define DA9150_DAT_MODE_SHIFT 2
743#define DA9150_DAT_MODE_MASK (0x0f << 2)
744#define DA9150_DAT_SWP_SHIFT 6
745#define DA9150_DAT_SWP_MASK BIT(6)
746#define DA9150_DAT_CLAMP_EXT_SHIFT 7
747#define DA9150_DAT_CLAMP_EXT_MASK BIT(7)
748
749/* DA9150_ADETID_CFG_A = 0x15B */
750#define DA9150_TID_POLL_SHIFT 0
751#define DA9150_TID_POLL_MASK (0x07 << 0)
752#define DA9150_RID_CONV_SHIFT 3
753#define DA9150_RID_CONV_MASK BIT(3)
754
755/* DA9150_ADET_RID_PT_CHG_H = 0x15C */
756#define DA9150_RID_PT_CHG_H_SHIFT 0
757#define DA9150_RID_PT_CHG_H_MASK (0xff << 0)
758
759/* DA9150_ADET_RID_PT_CHG_L = 0x15D */
760#define DA9150_RID_PT_CHG_L_SHIFT 6
761#define DA9150_RID_PT_CHG_L_MASK (0x03 << 6)
762
763/* DA9150_PPR_TCTR_B = 0x160 */
764#define DA9150_CHG_TCTR_VAL_SHIFT 0
765#define DA9150_CHG_TCTR_VAL_MASK (0xff << 0)
766
767/* DA9150_PPR_BKCTRL_A = 0x163 */
768#define DA9150_VBUS_MODE_SHIFT 0
769#define DA9150_VBUS_MODE_MASK (0x03 << 0)
770#define DA9150_VBUS_MODE_CHG BIT(0)
771#define DA9150_VBUS_MODE_OTG (0x02 << 0)
772#define DA9150_VBUS_LPM_SHIFT 2
773#define DA9150_VBUS_LPM_MASK (0x03 << 2)
774#define DA9150_VBUS_SUSP_SHIFT 4
775#define DA9150_VBUS_SUSP_MASK BIT(4)
776#define DA9150_VBUS_PWM_SHIFT 5
777#define DA9150_VBUS_PWM_MASK BIT(5)
778#define DA9150_VBUS_ISO_SHIFT 6
779#define DA9150_VBUS_ISO_MASK BIT(6)
780#define DA9150_VBUS_LDO_SHIFT 7
781#define DA9150_VBUS_LDO_MASK BIT(7)
782
783/* DA9150_PPR_BKCFG_A = 0x164 */
784#define DA9150_VBUS_ISET_SHIFT 0
785#define DA9150_VBUS_ISET_MASK (0x1f << 0)
786#define DA9150_VBUS_IMAX_SHIFT 5
787#define DA9150_VBUS_IMAX_MASK BIT(5)
788#define DA9150_VBUS_IOTG_SHIFT 6
789#define DA9150_VBUS_IOTG_MASK (0x03 << 6)
790
791/* DA9150_PPR_BKCFG_B = 0x165 */
792#define DA9150_VBUS_DROP_SHIFT 0
793#define DA9150_VBUS_DROP_MASK (0x0f << 0)
794#define DA9150_VBUS_FAULT_DIS_SHIFT 6
795#define DA9150_VBUS_FAULT_DIS_MASK BIT(6)
796#define DA9150_OTG_FAULT_DIS_SHIFT 7
797#define DA9150_OTG_FAULT_DIS_MASK BIT(7)
798
799/* DA9150_PPR_CHGCTRL_A = 0x166 */
800#define DA9150_CHG_EN_SHIFT 0
801#define DA9150_CHG_EN_MASK BIT(0)
802
803/* DA9150_PPR_CHGCTRL_B = 0x167 */
804#define DA9150_CHG_VBAT_SHIFT 0
805#define DA9150_CHG_VBAT_MASK (0x1f << 0)
806#define DA9150_CHG_VDROP_SHIFT 6
807#define DA9150_CHG_VDROP_MASK (0x03 << 6)
808
809/* DA9150_PPR_CHGCTRL_C = 0x168 */
810#define DA9150_CHG_VFAULT_SHIFT 0
811#define DA9150_CHG_VFAULT_MASK (0x0f << 0)
812#define DA9150_CHG_IPRE_SHIFT 4
813#define DA9150_CHG_IPRE_MASK (0x03 << 4)
814
815/* DA9150_PPR_TCTR_A = 0x169 */
816#define DA9150_CHG_TCTR_SHIFT 0
817#define DA9150_CHG_TCTR_MASK (0x07 << 0)
818#define DA9150_CHG_TCTR_MODE_SHIFT 4
819#define DA9150_CHG_TCTR_MODE_MASK BIT(4)
820
821/* DA9150_PPR_CHGCTRL_D = 0x16A */
822#define DA9150_CHG_IBAT_SHIFT 0
823#define DA9150_CHG_IBAT_MASK (0xff << 0)
824
825/* DA9150_PPR_CHGCTRL_E = 0x16B */
826#define DA9150_CHG_IEND_SHIFT 0
827#define DA9150_CHG_IEND_MASK (0xff << 0)
828
829/* DA9150_PPR_CHGCTRL_F = 0x16C */
830#define DA9150_CHG_VCOLD_SHIFT 0
831#define DA9150_CHG_VCOLD_MASK (0x1f << 0)
832#define DA9150_TBAT_TQA_EN_SHIFT 6
833#define DA9150_TBAT_TQA_EN_MASK BIT(6)
834#define DA9150_TBAT_TDP_EN_SHIFT 7
835#define DA9150_TBAT_TDP_EN_MASK BIT(7)
836
837/* DA9150_PPR_CHGCTRL_G = 0x16D */
838#define DA9150_CHG_VWARM_SHIFT 0
839#define DA9150_CHG_VWARM_MASK (0x1f << 0)
840
841/* DA9150_PPR_CHGCTRL_H = 0x16E */
842#define DA9150_CHG_VHOT_SHIFT 0
843#define DA9150_CHG_VHOT_MASK (0x1f << 0)
844
845/* DA9150_PPR_CHGCTRL_I = 0x16F */
846#define DA9150_CHG_ICOLD_SHIFT 0
847#define DA9150_CHG_ICOLD_MASK (0xff << 0)
848
849/* DA9150_PPR_CHGCTRL_J = 0x170 */
850#define DA9150_CHG_IWARM_SHIFT 0
851#define DA9150_CHG_IWARM_MASK (0xff << 0)
852
853/* DA9150_PPR_CHGCTRL_K = 0x171 */
854#define DA9150_CHG_IHOT_SHIFT 0
855#define DA9150_CHG_IHOT_MASK (0xff << 0)
856
857/* DA9150_PPR_CHGCTRL_L = 0x172 */
858#define DA9150_CHG_IBAT_TRED_SHIFT 0
859#define DA9150_CHG_IBAT_TRED_MASK (0xff << 0)
860
861/* DA9150_PPR_CHGCTRL_M = 0x173 */
862#define DA9150_CHG_VFLOAT_SHIFT 0
863#define DA9150_CHG_VFLOAT_MASK (0x0f << 0)
864#define DA9150_CHG_LPM_SHIFT 5
865#define DA9150_CHG_LPM_MASK BIT(5)
866#define DA9150_CHG_NBLO_SHIFT 6
867#define DA9150_CHG_NBLO_MASK BIT(6)
868#define DA9150_EBS_EN_SHIFT 7
869#define DA9150_EBS_EN_MASK BIT(7)
870
871/* DA9150_PPR_THYST_A = 0x174 */
872#define DA9150_TBAT_T1_SHIFT 0
873#define DA9150_TBAT_T1_MASK (0xff << 0)
874
875/* DA9150_PPR_THYST_B = 0x175 */
876#define DA9150_TBAT_T2_SHIFT 0
877#define DA9150_TBAT_T2_MASK (0xff << 0)
878
879/* DA9150_PPR_THYST_C = 0x176 */
880#define DA9150_TBAT_T3_SHIFT 0
881#define DA9150_TBAT_T3_MASK (0xff << 0)
882
883/* DA9150_PPR_THYST_D = 0x177 */
884#define DA9150_TBAT_T4_SHIFT 0
885#define DA9150_TBAT_T4_MASK (0xff << 0)
886
887/* DA9150_PPR_THYST_E = 0x178 */
888#define DA9150_TBAT_T5_SHIFT 0
889#define DA9150_TBAT_T5_MASK (0xff << 0)
890
891/* DA9150_PPR_THYST_F = 0x179 */
892#define DA9150_TBAT_H1_SHIFT 0
893#define DA9150_TBAT_H1_MASK (0xff << 0)
894
895/* DA9150_PPR_THYST_G = 0x17A */
896#define DA9150_TBAT_H5_SHIFT 0
897#define DA9150_TBAT_H5_MASK (0xff << 0)
898
899/* DA9150_PAGE_CON_3 = 0x180 */
900#define DA9150_PAGE_SHIFT 0
901#define DA9150_PAGE_MASK (0x3f << 0)
902#define DA9150_WRITE_MODE_SHIFT 6
903#define DA9150_WRITE_MODE_MASK BIT(6)
904#define DA9150_REVERT_SHIFT 7
905#define DA9150_REVERT_MASK BIT(7)
906
907/* DA9150_PAGE_CON_4 = 0x200 */
908#define DA9150_PAGE_SHIFT 0
909#define DA9150_PAGE_MASK (0x3f << 0)
910#define DA9150_WRITE_MODE_SHIFT 6
911#define DA9150_WRITE_MODE_MASK BIT(6)
912#define DA9150_REVERT_SHIFT 7
913#define DA9150_REVERT_MASK BIT(7)
914
915/* DA9150_PAGE_CON_5 = 0x280 */
916#define DA9150_PAGE_SHIFT 0
917#define DA9150_PAGE_MASK (0x3f << 0)
918#define DA9150_WRITE_MODE_SHIFT 6
919#define DA9150_WRITE_MODE_MASK BIT(6)
920#define DA9150_REVERT_SHIFT 7
921#define DA9150_REVERT_MASK BIT(7)
922
923/* DA9150_PAGE_CON_6 = 0x300 */
924#define DA9150_PAGE_SHIFT 0
925#define DA9150_PAGE_MASK (0x3f << 0)
926#define DA9150_WRITE_MODE_SHIFT 6
927#define DA9150_WRITE_MODE_MASK BIT(6)
928#define DA9150_REVERT_SHIFT 7
929#define DA9150_REVERT_MASK BIT(7)
930
931/* DA9150_COREBTLD_STAT_A = 0x302 */
932#define DA9150_BOOTLD_STAT_SHIFT 0
933#define DA9150_BOOTLD_STAT_MASK (0x03 << 0)
934#define DA9150_CORE_LOCKUP_SHIFT 2
935#define DA9150_CORE_LOCKUP_MASK BIT(2)
936
937/* DA9150_COREBTLD_CTRL_A = 0x303 */
938#define DA9150_CORE_RESET_SHIFT 0
939#define DA9150_CORE_RESET_MASK BIT(0)
940#define DA9150_CORE_STOP_SHIFT 1
941#define DA9150_CORE_STOP_MASK BIT(1)
942
943/* DA9150_CORE_CONFIG_A = 0x304 */
944#define DA9150_CORE_MEMMUX_SHIFT 0
945#define DA9150_CORE_MEMMUX_MASK (0x03 << 0)
946#define DA9150_WDT_AUTO_START_SHIFT 2
947#define DA9150_WDT_AUTO_START_MASK BIT(2)
948#define DA9150_WDT_AUTO_LOCK_SHIFT 3
949#define DA9150_WDT_AUTO_LOCK_MASK BIT(3)
950#define DA9150_WDT_HLT_NO_CLK_SHIFT 4
951#define DA9150_WDT_HLT_NO_CLK_MASK BIT(4)
952
953/* DA9150_CORE_CONFIG_C = 0x305 */
954#define DA9150_CORE_SW_SIZE_SHIFT 0
955#define DA9150_CORE_SW_SIZE_MASK (0xff << 0)
956
957/* DA9150_CORE_CONFIG_B = 0x306 */
958#define DA9150_BOOTLD_EN_SHIFT 0
959#define DA9150_BOOTLD_EN_MASK BIT(0)
960#define DA9150_CORE_EN_SHIFT 2
961#define DA9150_CORE_EN_MASK BIT(2)
962#define DA9150_CORE_SW_SRC_SHIFT 3
963#define DA9150_CORE_SW_SRC_MASK (0x07 << 3)
964#define DA9150_DEEP_SLEEP_EN_SHIFT 7
965#define DA9150_DEEP_SLEEP_EN_MASK BIT(7)
966
967/* DA9150_CORE_CFG_DATA_A = 0x307 */
968#define DA9150_CORE_CFG_DT_A_SHIFT 0
969#define DA9150_CORE_CFG_DT_A_MASK (0xff << 0)
970
971/* DA9150_CORE_CFG_DATA_B = 0x308 */
972#define DA9150_CORE_CFG_DT_B_SHIFT 0
973#define DA9150_CORE_CFG_DT_B_MASK (0xff << 0)
974
975/* DA9150_CORE_CMD_A = 0x309 */
976#define DA9150_CORE_CMD_SHIFT 0
977#define DA9150_CORE_CMD_MASK (0xff << 0)
978
979/* DA9150_CORE_DATA_A = 0x30A */
980#define DA9150_CORE_DATA_0_SHIFT 0
981#define DA9150_CORE_DATA_0_MASK (0xff << 0)
982
983/* DA9150_CORE_DATA_B = 0x30B */
984#define DA9150_CORE_DATA_1_SHIFT 0
985#define DA9150_CORE_DATA_1_MASK (0xff << 0)
986
987/* DA9150_CORE_DATA_C = 0x30C */
988#define DA9150_CORE_DATA_2_SHIFT 0
989#define DA9150_CORE_DATA_2_MASK (0xff << 0)
990
991/* DA9150_CORE_DATA_D = 0x30D */
992#define DA9150_CORE_DATA_3_SHIFT 0
993#define DA9150_CORE_DATA_3_MASK (0xff << 0)
994
995/* DA9150_CORE2WIRE_STAT_A = 0x310 */
996#define DA9150_FW_FWDL_ERR_SHIFT 7
997#define DA9150_FW_FWDL_ERR_MASK BIT(7)
998
999/* DA9150_CORE2WIRE_CTRL_A = 0x311 */
1000#define DA9150_FW_FWDL_EN_SHIFT 0
1001#define DA9150_FW_FWDL_EN_MASK BIT(0)
1002#define DA9150_FG_QIF_EN_SHIFT 1
1003#define DA9150_FG_QIF_EN_MASK BIT(1)
1004#define DA9150_CORE_BASE_ADDR_SHIFT 4
1005#define DA9150_CORE_BASE_ADDR_MASK (0x0f << 4)
1006
1007/* DA9150_FW_CTRL_A = 0x312 */
1008#define DA9150_FW_SEAL_SHIFT 0
1009#define DA9150_FW_SEAL_MASK (0xff << 0)
1010
1011/* DA9150_FW_CTRL_C = 0x313 */
1012#define DA9150_FW_FWDL_CRC_SHIFT 0
1013#define DA9150_FW_FWDL_CRC_MASK (0xff << 0)
1014
1015/* DA9150_FW_CTRL_D = 0x314 */
1016#define DA9150_FW_FWDL_BASE_SHIFT 0
1017#define DA9150_FW_FWDL_BASE_MASK (0x0f << 0)
1018
1019/* DA9150_FG_CTRL_A = 0x315 */
1020#define DA9150_FG_QIF_CODE_SHIFT 0
1021#define DA9150_FG_QIF_CODE_MASK (0xff << 0)
1022
1023/* DA9150_FG_CTRL_B = 0x316 */
1024#define DA9150_FG_QIF_VALUE_SHIFT 0
1025#define DA9150_FG_QIF_VALUE_MASK (0xff << 0)
1026
1027/* DA9150_FW_CTRL_E = 0x317 */
1028#define DA9150_FW_FWDL_SEG_SHIFT 0
1029#define DA9150_FW_FWDL_SEG_MASK (0xff << 0)
1030
1031/* DA9150_FW_CTRL_B = 0x318 */
1032#define DA9150_FW_FWDL_VALUE_SHIFT 0
1033#define DA9150_FW_FWDL_VALUE_MASK (0xff << 0)
1034
1035/* DA9150_GPADC_CMAN = 0x320 */
1036#define DA9150_GPADC_CEN_SHIFT 0
1037#define DA9150_GPADC_CEN_MASK BIT(0)
1038#define DA9150_GPADC_CMUX_SHIFT 1
1039#define DA9150_GPADC_CMUX_MASK (0x1f << 1)
1040
1041/* DA9150_GPADC_CRES_A = 0x322 */
1042#define DA9150_GPADC_CRES_H_SHIFT 0
1043#define DA9150_GPADC_CRES_H_MASK (0xff << 0)
1044
1045/* DA9150_GPADC_CRES_B = 0x323 */
1046#define DA9150_GPADC_CRUN_SHIFT 0
1047#define DA9150_GPADC_CRUN_MASK BIT(0)
1048#define DA9150_GPADC_CRES_L_SHIFT 6
1049#define DA9150_GPADC_CRES_L_MASK (0x03 << 6)
1050
1051/* DA9150_CC_CFG_A = 0x328 */
1052#define DA9150_CC_EN_SHIFT 0
1053#define DA9150_CC_EN_MASK BIT(0)
1054#define DA9150_CC_TIMEBASE_SHIFT 1
1055#define DA9150_CC_TIMEBASE_MASK (0x03 << 1)
1056#define DA9150_CC_CFG_SHIFT 5
1057#define DA9150_CC_CFG_MASK (0x03 << 5)
1058#define DA9150_CC_ENDLESS_MODE_SHIFT 7
1059#define DA9150_CC_ENDLESS_MODE_MASK BIT(7)
1060
1061/* DA9150_CC_CFG_B = 0x329 */
1062#define DA9150_CC_OPT_SHIFT 0
1063#define DA9150_CC_OPT_MASK (0x03 << 0)
1064#define DA9150_CC_PREAMP_SHIFT 2
1065#define DA9150_CC_PREAMP_MASK (0x03 << 2)
1066
1067/* DA9150_CC_ICHG_RES_A = 0x32A */
1068#define DA9150_CC_ICHG_RES_H_SHIFT 0
1069#define DA9150_CC_ICHG_RES_H_MASK (0xff << 0)
1070
1071/* DA9150_CC_ICHG_RES_B = 0x32B */
1072#define DA9150_CC_ICHG_RES_L_SHIFT 3
1073#define DA9150_CC_ICHG_RES_L_MASK (0x1f << 3)
1074
1075/* DA9150_CC_IAVG_RES_A = 0x32C */
1076#define DA9150_CC_IAVG_RES_H_SHIFT 0
1077#define DA9150_CC_IAVG_RES_H_MASK (0xff << 0)
1078
1079/* DA9150_CC_IAVG_RES_B = 0x32D */
1080#define DA9150_CC_IAVG_RES_L_SHIFT 0
1081#define DA9150_CC_IAVG_RES_L_MASK (0xff << 0)
1082
1083/* DA9150_TAUX_CTRL_A = 0x330 */
1084#define DA9150_TAUX_EN_SHIFT 0
1085#define DA9150_TAUX_EN_MASK BIT(0)
1086#define DA9150_TAUX_MOD_SHIFT 1
1087#define DA9150_TAUX_MOD_MASK BIT(1)
1088#define DA9150_TAUX_UPDATE_SHIFT 2
1089#define DA9150_TAUX_UPDATE_MASK BIT(2)
1090
1091/* DA9150_TAUX_RELOAD_H = 0x332 */
1092#define DA9150_TAUX_RLD_H_SHIFT 0
1093#define DA9150_TAUX_RLD_H_MASK (0xff << 0)
1094
1095/* DA9150_TAUX_RELOAD_L = 0x333 */
1096#define DA9150_TAUX_RLD_L_SHIFT 3
1097#define DA9150_TAUX_RLD_L_MASK (0x1f << 3)
1098
1099/* DA9150_TAUX_VALUE_H = 0x334 */
1100#define DA9150_TAUX_VAL_H_SHIFT 0
1101#define DA9150_TAUX_VAL_H_MASK (0xff << 0)
1102
1103/* DA9150_TAUX_VALUE_L = 0x335 */
1104#define DA9150_TAUX_VAL_L_SHIFT 3
1105#define DA9150_TAUX_VAL_L_MASK (0x1f << 3)
1106
1107/* DA9150_AUX_DATA_0 = 0x338 */
1108#define DA9150_AUX_DAT_0_SHIFT 0
1109#define DA9150_AUX_DAT_0_MASK (0xff << 0)
1110
1111/* DA9150_AUX_DATA_1 = 0x339 */
1112#define DA9150_AUX_DAT_1_SHIFT 0
1113#define DA9150_AUX_DAT_1_MASK (0xff << 0)
1114
1115/* DA9150_AUX_DATA_2 = 0x33A */
1116#define DA9150_AUX_DAT_2_SHIFT 0
1117#define DA9150_AUX_DAT_2_MASK (0xff << 0)
1118
1119/* DA9150_AUX_DATA_3 = 0x33B */
1120#define DA9150_AUX_DAT_3_SHIFT 0
1121#define DA9150_AUX_DAT_3_MASK (0xff << 0)
1122
1123/* DA9150_BIF_CTRL = 0x340 */
1124#define DA9150_BIF_ISRC_EN_SHIFT 0
1125#define DA9150_BIF_ISRC_EN_MASK BIT(0)
1126
1127/* DA9150_TBAT_CTRL_A = 0x342 */
1128#define DA9150_TBAT_EN_SHIFT 0
1129#define DA9150_TBAT_EN_MASK BIT(0)
1130#define DA9150_TBAT_SW1_SHIFT 1
1131#define DA9150_TBAT_SW1_MASK BIT(1)
1132#define DA9150_TBAT_SW2_SHIFT 2
1133#define DA9150_TBAT_SW2_MASK BIT(2)
1134
1135/* DA9150_TBAT_CTRL_B = 0x343 */
1136#define DA9150_TBAT_SW_FRC_SHIFT 0
1137#define DA9150_TBAT_SW_FRC_MASK BIT(0)
1138#define DA9150_TBAT_STAT_SW1_SHIFT 1
1139#define DA9150_TBAT_STAT_SW1_MASK BIT(1)
1140#define DA9150_TBAT_STAT_SW2_SHIFT 2
1141#define DA9150_TBAT_STAT_SW2_MASK BIT(2)
1142#define DA9150_TBAT_HIGH_CURR_SHIFT 3
1143#define DA9150_TBAT_HIGH_CURR_MASK BIT(3)
1144
1145/* DA9150_TBAT_RES_A = 0x344 */
1146#define DA9150_TBAT_RES_H_SHIFT 0
1147#define DA9150_TBAT_RES_H_MASK (0xff << 0)
1148
1149/* DA9150_TBAT_RES_B = 0x345 */
1150#define DA9150_TBAT_RES_DIS_SHIFT 0
1151#define DA9150_TBAT_RES_DIS_MASK BIT(0)
1152#define DA9150_TBAT_RES_L_SHIFT 6
1153#define DA9150_TBAT_RES_L_MASK (0x03 << 6)
1154
1155#endif /* __DA9150_REGISTERS_H */
diff --git a/include/linux/mfd/max77686-private.h b/include/linux/mfd/max77686-private.h
index 960b92ad450d..f5043490d67c 100644
--- a/include/linux/mfd/max77686-private.h
+++ b/include/linux/mfd/max77686-private.h
@@ -447,7 +447,6 @@ struct max77686_dev {
447 struct regmap_irq_chip_data *rtc_irq_data; 447 struct regmap_irq_chip_data *rtc_irq_data;
448 448
449 int irq; 449 int irq;
450 bool wakeup;
451 struct mutex irqlock; 450 struct mutex irqlock;
452 int irq_masks_cur[MAX77686_IRQ_GROUP_NR]; 451 int irq_masks_cur[MAX77686_IRQ_GROUP_NR];
453 int irq_masks_cache[MAX77686_IRQ_GROUP_NR]; 452 int irq_masks_cache[MAX77686_IRQ_GROUP_NR];
diff --git a/include/linux/mfd/max77686.h b/include/linux/mfd/max77686.h
index 553f7d09258a..bb995ab9a575 100644
--- a/include/linux/mfd/max77686.h
+++ b/include/linux/mfd/max77686.h
@@ -119,12 +119,6 @@ enum max77802_regulators {
119 MAX77802_REG_MAX, 119 MAX77802_REG_MAX,
120}; 120};
121 121
122struct max77686_regulator_data {
123 int id;
124 struct regulator_init_data *initdata;
125 struct device_node *of_node;
126};
127
128enum max77686_opmode { 122enum max77686_opmode {
129 MAX77686_OPMODE_NORMAL, 123 MAX77686_OPMODE_NORMAL,
130 MAX77686_OPMODE_LP, 124 MAX77686_OPMODE_LP,
@@ -136,26 +130,4 @@ struct max77686_opmode_data {
136 int mode; 130 int mode;
137}; 131};
138 132
139struct max77686_platform_data {
140 int ono;
141 int wakeup;
142
143 /* ---- PMIC ---- */
144 struct max77686_regulator_data *regulators;
145 int num_regulators;
146
147 struct max77686_opmode_data *opmode_data;
148
149 /*
150 * GPIO-DVS feature is not enabled with the current version of
151 * MAX77686 driver. Buck2/3/4_voltages[0] is used as the default
152 * voltage at probe. DVS/SELB gpios are set as OUTPUT-LOW.
153 */
154 int buck234_gpio_dvs[3]; /* GPIO of [0]DVS1, [1]DVS2, [2]DVS3 */
155 int buck234_gpio_selb[3]; /* [0]SELB2, [1]SELB3, [2]SELB4 */
156 unsigned int buck2_voltage[8]; /* buckx_voltage in uV */
157 unsigned int buck3_voltage[8];
158 unsigned int buck4_voltage[8];
159};
160
161#endif /* __LINUX_MFD_MAX77686_H */ 133#endif /* __LINUX_MFD_MAX77686_H */
diff --git a/include/linux/mfd/qcom_rpm.h b/include/linux/mfd/qcom_rpm.h
new file mode 100644
index 000000000000..742ebf1b76ca
--- /dev/null
+++ b/include/linux/mfd/qcom_rpm.h
@@ -0,0 +1,13 @@
1#ifndef __QCOM_RPM_H__
2#define __QCOM_RPM_H__
3
4#include <linux/types.h>
5
6struct qcom_rpm;
7
8#define QCOM_RPM_ACTIVE_STATE 0
9#define QCOM_RPM_SLEEP_STATE 1
10
11int qcom_rpm_write(struct qcom_rpm *rpm, int state, int resource, u32 *buf, size_t count);
12
13#endif
diff --git a/include/linux/mfd/rt5033-private.h b/include/linux/mfd/rt5033-private.h
new file mode 100644
index 000000000000..1b63fc2f42d1
--- /dev/null
+++ b/include/linux/mfd/rt5033-private.h
@@ -0,0 +1,260 @@
1/*
2 * MFD core driver for Richtek RT5033
3 *
4 * Copyright (C) 2014 Samsung Electronics, Co., Ltd.
5 * Author: Beomho Seo <beomho.seo@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published bythe Free Software Foundation.
10 */
11
12#ifndef __RT5033_PRIVATE_H__
13#define __RT5033_PRIVATE_H__
14
15enum rt5033_reg {
16 RT5033_REG_CHG_STAT = 0x00,
17 RT5033_REG_CHG_CTRL1 = 0x01,
18 RT5033_REG_CHG_CTRL2 = 0x02,
19 RT5033_REG_DEVICE_ID = 0x03,
20 RT5033_REG_CHG_CTRL3 = 0x04,
21 RT5033_REG_CHG_CTRL4 = 0x05,
22 RT5033_REG_CHG_CTRL5 = 0x06,
23 RT5033_REG_RT_CTRL0 = 0x07,
24 RT5033_REG_CHG_RESET = 0x08,
25 /* Reserved 0x09~0x18 */
26 RT5033_REG_RT_CTRL1 = 0x19,
27 /* Reserved 0x1A~0x20 */
28 RT5033_REG_FLED_FUNCTION1 = 0x21,
29 RT5033_REG_FLED_FUNCTION2 = 0x22,
30 RT5033_REG_FLED_STROBE_CTRL1 = 0x23,
31 RT5033_REG_FLED_STROBE_CTRL2 = 0x24,
32 RT5033_REG_FLED_CTRL1 = 0x25,
33 RT5033_REG_FLED_CTRL2 = 0x26,
34 RT5033_REG_FLED_CTRL3 = 0x27,
35 RT5033_REG_FLED_CTRL4 = 0x28,
36 RT5033_REG_FLED_CTRL5 = 0x29,
37 /* Reserved 0x2A~0x40 */
38 RT5033_REG_CTRL = 0x41,
39 RT5033_REG_BUCK_CTRL = 0x42,
40 RT5033_REG_LDO_CTRL = 0x43,
41 /* Reserved 0x44~0x46 */
42 RT5033_REG_MANUAL_RESET_CTRL = 0x47,
43 /* Reserved 0x48~0x5F */
44 RT5033_REG_CHG_IRQ1 = 0x60,
45 RT5033_REG_CHG_IRQ2 = 0x61,
46 RT5033_REG_CHG_IRQ3 = 0x62,
47 RT5033_REG_CHG_IRQ1_CTRL = 0x63,
48 RT5033_REG_CHG_IRQ2_CTRL = 0x64,
49 RT5033_REG_CHG_IRQ3_CTRL = 0x65,
50 RT5033_REG_LED_IRQ_STAT = 0x66,
51 RT5033_REG_LED_IRQ_CTRL = 0x67,
52 RT5033_REG_PMIC_IRQ_STAT = 0x68,
53 RT5033_REG_PMIC_IRQ_CTRL = 0x69,
54 RT5033_REG_SHDN_CTRL = 0x6A,
55 RT5033_REG_OFF_EVENT = 0x6B,
56
57 RT5033_REG_END,
58};
59
60/* RT5033 Charger state register */
61#define RT5033_CHG_STAT_MASK 0x20
62#define RT5033_CHG_STAT_DISCHARGING 0x00
63#define RT5033_CHG_STAT_FULL 0x10
64#define RT5033_CHG_STAT_CHARGING 0x20
65#define RT5033_CHG_STAT_NOT_CHARGING 0x30
66#define RT5033_CHG_STAT_TYPE_MASK 0x60
67#define RT5033_CHG_STAT_TYPE_PRE 0x20
68#define RT5033_CHG_STAT_TYPE_FAST 0x60
69
70/* RT5033 CHGCTRL1 register */
71#define RT5033_CHGCTRL1_IAICR_MASK 0xe0
72#define RT5033_CHGCTRL1_MODE_MASK 0x01
73
74/* RT5033 CHGCTRL2 register */
75#define RT5033_CHGCTRL2_CV_MASK 0xfc
76
77/* RT5033 CHGCTRL3 register */
78#define RT5033_CHGCTRL3_CFO_EN_MASK 0x40
79#define RT5033_CHGCTRL3_TIMER_MASK 0x38
80#define RT5033_CHGCTRL3_TIMER_EN_MASK 0x01
81
82/* RT5033 CHGCTRL4 register */
83#define RT5033_CHGCTRL4_EOC_MASK 0x07
84#define RT5033_CHGCTRL4_IPREC_MASK 0x18
85
86/* RT5033 CHGCTRL5 register */
87#define RT5033_CHGCTRL5_VPREC_MASK 0x0f
88#define RT5033_CHGCTRL5_ICHG_MASK 0xf0
89#define RT5033_CHGCTRL5_ICHG_SHIFT 0x04
90#define RT5033_CHG_MAX_CURRENT 0x0d
91
92/* RT5033 RT CTRL1 register */
93#define RT5033_RT_CTRL1_UUG_MASK 0x02
94#define RT5033_RT_HZ_MASK 0x01
95
96/* RT5033 control register */
97#define RT5033_CTRL_FCCM_BUCK_MASK 0x00
98#define RT5033_CTRL_BUCKOMS_MASK 0x01
99#define RT5033_CTRL_LDOOMS_MASK 0x02
100#define RT5033_CTRL_SLDOOMS_MASK 0x03
101#define RT5033_CTRL_EN_BUCK_MASK 0x04
102#define RT5033_CTRL_EN_LDO_MASK 0x05
103#define RT5033_CTRL_EN_SAFE_LDO_MASK 0x06
104#define RT5033_CTRL_LDO_SLEEP_MASK 0x07
105
106/* RT5033 BUCK control register */
107#define RT5033_BUCK_CTRL_MASK 0x1f
108
109/* RT5033 LDO control register */
110#define RT5033_LDO_CTRL_MASK 0x1f
111
112/* RT5033 charger property - model, manufacturer */
113
114#define RT5033_CHARGER_MODEL "RT5033WSC Charger"
115#define RT5033_MANUFACTURER "Richtek Technology Corporation"
116
117/*
118 * RT5033 charger fast-charge current lmits (as in CHGCTRL1 register),
119 * AICR mode limits the input current for example,
120 * the AIRC 100 mode limits the input current to 100 mA.
121 */
122#define RT5033_AICR_100_MODE 0x20
123#define RT5033_AICR_500_MODE 0x40
124#define RT5033_AICR_700_MODE 0x60
125#define RT5033_AICR_900_MODE 0x80
126#define RT5033_AICR_1500_MODE 0xc0
127#define RT5033_AICR_2000_MODE 0xe0
128#define RT5033_AICR_MODE_MASK 0xe0
129
130/* RT5033 use internal timer need to set time */
131#define RT5033_FAST_CHARGE_TIMER4 0x00
132#define RT5033_FAST_CHARGE_TIMER6 0x01
133#define RT5033_FAST_CHARGE_TIMER8 0x02
134#define RT5033_FAST_CHARGE_TIMER9 0x03
135#define RT5033_FAST_CHARGE_TIMER12 0x04
136#define RT5033_FAST_CHARGE_TIMER14 0x05
137#define RT5033_FAST_CHARGE_TIMER16 0x06
138
139#define RT5033_INT_TIMER_ENABLE 0x01
140
141/* RT5033 charger termination enable mask */
142#define RT5033_TE_ENABLE_MASK 0x08
143
144/*
145 * RT5033 charger opa mode. RT50300 have two opa mode charger mode
146 * and boost mode for OTG
147 */
148
149#define RT5033_CHARGER_MODE 0x00
150#define RT5033_BOOST_MODE 0x01
151
152/* RT5033 charger termination enable */
153#define RT5033_TE_ENABLE 0x08
154
155/* RT5033 charger CFO enable */
156#define RT5033_CFO_ENABLE 0x40
157
158/* RT5033 charger constant charge voltage (as in CHGCTRL2 register), uV */
159#define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MIN 3650000U
160#define RT5033_CHARGER_CONST_VOLTAGE_STEP_NUM 25000U
161#define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MAX 4400000U
162
163/* RT5033 charger pre-charge current limits (as in CHGCTRL4 register), uA */
164#define RT5033_CHARGER_PRE_CURRENT_LIMIT_MIN 350000U
165#define RT5033_CHARGER_PRE_CURRENT_STEP_NUM 100000U
166#define RT5033_CHARGER_PRE_CURRENT_LIMIT_MAX 650000U
167
168/* RT5033 charger fast-charge current (as in CHGCTRL5 register), uA */
169#define RT5033_CHARGER_FAST_CURRENT_MIN 700000U
170#define RT5033_CHARGER_FAST_CURRENT_STEP_NUM 100000U
171#define RT5033_CHARGER_FAST_CURRENT_MAX 2000000U
172
173/*
174 * RT5033 charger const-charge end of charger current (
175 * as in CHGCTRL4 register), uA
176 */
177#define RT5033_CHARGER_EOC_MIN 150000U
178#define RT5033_CHARGER_EOC_REF 300000U
179#define RT5033_CHARGER_EOC_STEP_NUM1 50000U
180#define RT5033_CHARGER_EOC_STEP_NUM2 100000U
181#define RT5033_CHARGER_EOC_MAX 600000U
182
183/*
184 * RT5033 charger pre-charge threshold volt limits
185 * (as in CHGCTRL5 register), uV
186 */
187
188#define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MIN 2300000U
189#define RT5033_CHARGER_PRE_THRESHOLD_STEP_NUM 100000U
190#define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MAX 3800000U
191
192/*
193 * RT5033 charger enable UUG, If UUG enable MOS auto control by H/W charger
194 * circuit.
195 */
196#define RT5033_CHARGER_UUG_ENABLE 0x02
197
198/* RT5033 charger High impedance mode */
199#define RT5033_CHARGER_HZ_DISABLE 0x00
200#define RT5033_CHARGER_HZ_ENABLE 0x01
201
202/* RT5033 regulator BUCK output voltage uV */
203#define RT5033_REGULATOR_BUCK_VOLTAGE_MIN 1000000U
204#define RT5033_REGULATOR_BUCK_VOLTAGE_MAX 3000000U
205#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP 100000U
206#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP_NUM 32
207
208/* RT5033 regulator LDO output voltage uV */
209#define RT5033_REGULATOR_LDO_VOLTAGE_MIN 1200000U
210#define RT5033_REGULATOR_LDO_VOLTAGE_MAX 3000000U
211#define RT5033_REGULATOR_LDO_VOLTAGE_STEP 100000U
212#define RT5033_REGULATOR_LDO_VOLTAGE_STEP_NUM 32
213
214/* RT5033 regulator SAFE LDO output voltage uV */
215#define RT5033_REGULATOR_SAFE_LDO_VOLTAGE 4900000U
216
217enum rt5033_fuel_reg {
218 RT5033_FUEL_REG_OCV_H = 0x00,
219 RT5033_FUEL_REG_OCV_L = 0x01,
220 RT5033_FUEL_REG_VBAT_H = 0x02,
221 RT5033_FUEL_REG_VBAT_L = 0x03,
222 RT5033_FUEL_REG_SOC_H = 0x04,
223 RT5033_FUEL_REG_SOC_L = 0x05,
224 RT5033_FUEL_REG_CTRL_H = 0x06,
225 RT5033_FUEL_REG_CTRL_L = 0x07,
226 RT5033_FUEL_REG_CRATE = 0x08,
227 RT5033_FUEL_REG_DEVICE_ID = 0x09,
228 RT5033_FUEL_REG_AVG_VOLT_H = 0x0A,
229 RT5033_FUEL_REG_AVG_VOLT_L = 0x0B,
230 RT5033_FUEL_REG_CONFIG_H = 0x0C,
231 RT5033_FUEL_REG_CONFIG_L = 0x0D,
232 /* Reserved 0x0E~0x0F */
233 RT5033_FUEL_REG_IRQ_CTRL = 0x10,
234 RT5033_FUEL_REG_IRQ_FLAG = 0x11,
235 RT5033_FUEL_VMIN = 0x12,
236 RT5033_FUEL_SMIN = 0x13,
237 /* Reserved 0x14~0x1F */
238 RT5033_FUEL_VGCOMP1 = 0x20,
239 RT5033_FUEL_VGCOMP2 = 0x21,
240 RT5033_FUEL_VGCOMP3 = 0x22,
241 RT5033_FUEL_VGCOMP4 = 0x23,
242 /* Reserved 0x24~0xFD */
243 RT5033_FUEL_MFA_H = 0xFE,
244 RT5033_FUEL_MFA_L = 0xFF,
245
246 RT5033_FUEL_REG_END,
247};
248
249/* RT5033 fuel gauge battery present property */
250#define RT5033_FUEL_BAT_PRESENT 0x02
251
252/* RT5033 PMIC interrupts */
253#define RT5033_PMIC_IRQ_BUCKOCP 2
254#define RT5033_PMIC_IRQ_BUCKLV 3
255#define RT5033_PMIC_IRQ_SAFELDOLV 4
256#define RT5033_PMIC_IRQ_LDOLV 5
257#define RT5033_PMIC_IRQ_OT 6
258#define RT5033_PMIC_IRQ_VDDA_UV 7
259
260#endif /* __RT5033_PRIVATE_H__ */
diff --git a/include/linux/mfd/rt5033.h b/include/linux/mfd/rt5033.h
new file mode 100644
index 000000000000..010cff49a98e
--- /dev/null
+++ b/include/linux/mfd/rt5033.h
@@ -0,0 +1,62 @@
1/*
2 * MFD core driver for the RT5033
3 *
4 * Copyright (C) 2014 Samsung Electronics
5 * Author: Beomho Seo <beomho.seo@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published bythe Free Software Foundation.
10 */
11
12#ifndef __RT5033_H__
13#define __RT5033_H__
14
15#include <linux/regulator/consumer.h>
16#include <linux/i2c.h>
17#include <linux/regmap.h>
18#include <linux/power_supply.h>
19
20/* RT5033 regulator IDs */
21enum rt5033_regulators {
22 RT5033_BUCK = 0,
23 RT5033_LDO,
24 RT5033_SAFE_LDO,
25
26 RT5033_REGULATOR_NUM,
27};
28
29struct rt5033_dev {
30 struct device *dev;
31
32 struct regmap *regmap;
33 struct regmap_irq_chip_data *irq_data;
34 int irq;
35 bool wakeup;
36};
37
38struct rt5033_battery {
39 struct i2c_client *client;
40 struct rt5033_dev *rt5033;
41 struct regmap *regmap;
42 struct power_supply psy;
43};
44
45/* RT5033 charger platform data */
46struct rt5033_charger_data {
47 unsigned int pre_uamp;
48 unsigned int pre_uvolt;
49 unsigned int const_uvolt;
50 unsigned int eoc_uamp;
51 unsigned int fast_uamp;
52};
53
54struct rt5033_charger {
55 struct device *dev;
56 struct rt5033_dev *rt5033;
57 struct power_supply psy;
58
59 struct rt5033_charger_data *chg;
60};
61
62#endif /* __RT5033_H__ */
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h
index 2bbc62aa818a..551f85456c11 100644
--- a/include/linux/mlx4/qp.h
+++ b/include/linux/mlx4/qp.h
@@ -427,7 +427,7 @@ struct mlx4_wqe_inline_seg {
427 427
428enum mlx4_update_qp_attr { 428enum mlx4_update_qp_attr {
429 MLX4_UPDATE_QP_SMAC = 1 << 0, 429 MLX4_UPDATE_QP_SMAC = 1 << 0,
430 MLX4_UPDATE_QP_VSD = 1 << 2, 430 MLX4_UPDATE_QP_VSD = 1 << 1,
431 MLX4_UPDATE_QP_SUPPORTED_ATTRS = (1 << 2) - 1 431 MLX4_UPDATE_QP_SUPPORTED_ATTRS = (1 << 2) - 1
432}; 432};
433 433
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 3301c4c289d6..f17fa75809aa 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -227,6 +227,7 @@ struct mtd_info {
227 int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs); 227 int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs);
228 int (*_suspend) (struct mtd_info *mtd); 228 int (*_suspend) (struct mtd_info *mtd);
229 void (*_resume) (struct mtd_info *mtd); 229 void (*_resume) (struct mtd_info *mtd);
230 void (*_reboot) (struct mtd_info *mtd);
230 /* 231 /*
231 * If the driver is something smart, like UBI, it may need to maintain 232 * If the driver is something smart, like UBI, it may need to maintain
232 * its own reference counting. The below functions are only for driver. 233 * its own reference counting. The below functions are only for driver.
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 63aeccf9ddc8..4720b86ee73d 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -56,6 +56,10 @@
56/* Used for Spansion flashes only. */ 56/* Used for Spansion flashes only. */
57#define SPINOR_OP_BRWR 0x17 /* Bank register write */ 57#define SPINOR_OP_BRWR 0x17 /* Bank register write */
58 58
59/* Used for Micron flashes only. */
60#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
61#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
62
59/* Status Register bits. */ 63/* Status Register bits. */
60#define SR_WIP 1 /* Write in progress */ 64#define SR_WIP 1 /* Write in progress */
61#define SR_WEL 2 /* Write enable latch */ 65#define SR_WEL 2 /* Write enable latch */
@@ -67,6 +71,9 @@
67 71
68#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */ 72#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
69 73
74/* Enhanced Volatile Configuration Register bits */
75#define EVCR_QUAD_EN_MICRON 0x80 /* Micron Quad I/O */
76
70/* Flag Status Register bits */ 77/* Flag Status Register bits */
71#define FSR_READY 0x80 78#define FSR_READY 0x80
72 79
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index 2007f3b44d05..625c8d71511b 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -2341,6 +2341,7 @@ struct gro_remcsum {
2341 2341
2342static inline void skb_gro_remcsum_init(struct gro_remcsum *grc) 2342static inline void skb_gro_remcsum_init(struct gro_remcsum *grc)
2343{ 2343{
2344 grc->offset = 0;
2344 grc->delta = 0; 2345 grc->delta = 0;
2345} 2346}
2346 2347
diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h
index 6d627b92df53..2f77e0c651c8 100644
--- a/include/linux/nfs_fs.h
+++ b/include/linux/nfs_fs.h
@@ -180,7 +180,6 @@ struct nfs_inode {
180 /* NFSv4 state */ 180 /* NFSv4 state */
181 struct list_head open_states; 181 struct list_head open_states;
182 struct nfs_delegation __rcu *delegation; 182 struct nfs_delegation __rcu *delegation;
183 fmode_t delegation_state;
184 struct rw_semaphore rwsem; 183 struct rw_semaphore rwsem;
185 184
186 /* pNFS layout information */ 185 /* pNFS layout information */
diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h
index 38d96ba935c2..4cb3eaa89cf7 100644
--- a/include/linux/nfs_xdr.h
+++ b/include/linux/nfs_xdr.h
@@ -1167,8 +1167,15 @@ struct nfs41_impl_id {
1167 struct nfstime4 date; 1167 struct nfstime4 date;
1168}; 1168};
1169 1169
1170struct nfs41_bind_conn_to_session_args {
1171 struct nfs_client *client;
1172 struct nfs4_sessionid sessionid;
1173 u32 dir;
1174 bool use_conn_in_rdma_mode;
1175};
1176
1170struct nfs41_bind_conn_to_session_res { 1177struct nfs41_bind_conn_to_session_res {
1171 struct nfs4_session *session; 1178 struct nfs4_sessionid sessionid;
1172 u32 dir; 1179 u32 dir;
1173 bool use_conn_in_rdma_mode; 1180 bool use_conn_in_rdma_mode;
1174}; 1181};
@@ -1185,6 +1192,8 @@ struct nfs41_exchange_id_res {
1185 1192
1186struct nfs41_create_session_args { 1193struct nfs41_create_session_args {
1187 struct nfs_client *client; 1194 struct nfs_client *client;
1195 u64 clientid;
1196 uint32_t seqid;
1188 uint32_t flags; 1197 uint32_t flags;
1189 uint32_t cb_program; 1198 uint32_t cb_program;
1190 struct nfs4_channel_attrs fc_attrs; /* Fore Channel */ 1199 struct nfs4_channel_attrs fc_attrs; /* Fore Channel */
@@ -1192,7 +1201,11 @@ struct nfs41_create_session_args {
1192}; 1201};
1193 1202
1194struct nfs41_create_session_res { 1203struct nfs41_create_session_res {
1195 struct nfs_client *client; 1204 struct nfs4_sessionid sessionid;
1205 uint32_t seqid;
1206 uint32_t flags;
1207 struct nfs4_channel_attrs fc_attrs; /* Fore Channel */
1208 struct nfs4_channel_attrs bc_attrs; /* Back Channel */
1196}; 1209};
1197 1210
1198struct nfs41_reclaim_complete_args { 1211struct nfs41_reclaim_complete_args {
@@ -1351,7 +1364,7 @@ struct nfs_commit_completion_ops {
1351}; 1364};
1352 1365
1353struct nfs_commit_info { 1366struct nfs_commit_info {
1354 spinlock_t *lock; 1367 spinlock_t *lock; /* inode->i_lock */
1355 struct nfs_mds_commit_info *mds; 1368 struct nfs_mds_commit_info *mds;
1356 struct pnfs_ds_commit_info *ds; 1369 struct pnfs_ds_commit_info *ds;
1357 struct nfs_direct_req *dreq; /* O_DIRECT request */ 1370 struct nfs_direct_req *dreq; /* O_DIRECT request */
diff --git a/include/linux/nvme.h b/include/linux/nvme.h
index 19a5d4b23209..0adad4a5419b 100644
--- a/include/linux/nvme.h
+++ b/include/linux/nvme.h
@@ -17,7 +17,6 @@
17 17
18#include <uapi/linux/nvme.h> 18#include <uapi/linux/nvme.h>
19#include <linux/pci.h> 19#include <linux/pci.h>
20#include <linux/miscdevice.h>
21#include <linux/kref.h> 20#include <linux/kref.h>
22#include <linux/blk-mq.h> 21#include <linux/blk-mq.h>
23 22
@@ -62,8 +61,6 @@ enum {
62 NVME_CSTS_SHST_MASK = 3 << 2, 61 NVME_CSTS_SHST_MASK = 3 << 2,
63}; 62};
64 63
65#define NVME_VS(major, minor) (major << 16 | minor)
66
67extern unsigned char nvme_io_timeout; 64extern unsigned char nvme_io_timeout;
68#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) 65#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
69 66
@@ -91,9 +88,10 @@ struct nvme_dev {
91 struct nvme_bar __iomem *bar; 88 struct nvme_bar __iomem *bar;
92 struct list_head namespaces; 89 struct list_head namespaces;
93 struct kref kref; 90 struct kref kref;
94 struct miscdevice miscdev; 91 struct device *device;
95 work_func_t reset_workfn; 92 work_func_t reset_workfn;
96 struct work_struct reset_work; 93 struct work_struct reset_work;
94 struct work_struct probe_work;
97 char name[12]; 95 char name[12];
98 char serial[20]; 96 char serial[20];
99 char model[40]; 97 char model[40];
@@ -105,7 +103,6 @@ struct nvme_dev {
105 u16 abort_limit; 103 u16 abort_limit;
106 u8 event_limit; 104 u8 event_limit;
107 u8 vwc; 105 u8 vwc;
108 u8 initialized;
109}; 106};
110 107
111/* 108/*
@@ -121,6 +118,7 @@ struct nvme_ns {
121 unsigned ns_id; 118 unsigned ns_id;
122 int lba_shift; 119 int lba_shift;
123 int ms; 120 int ms;
121 int pi_type;
124 u64 mode_select_num_blocks; 122 u64 mode_select_num_blocks;
125 u32 mode_select_block_len; 123 u32 mode_select_block_len;
126}; 124};
@@ -138,6 +136,7 @@ struct nvme_iod {
138 int nents; /* Used in scatterlist */ 136 int nents; /* Used in scatterlist */
139 int length; /* Of data, in bytes */ 137 int length; /* Of data, in bytes */
140 dma_addr_t first_dma; 138 dma_addr_t first_dma;
139 struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */
141 struct scatterlist sg[0]; 140 struct scatterlist sg[0];
142}; 141};
143 142
diff --git a/include/linux/platform_data/bfin_rotary.h b/include/linux/platform_data/bfin_rotary.h
new file mode 100644
index 000000000000..98829370fee2
--- /dev/null
+++ b/include/linux/platform_data/bfin_rotary.h
@@ -0,0 +1,117 @@
1/*
2 * board initialization should put one of these structures into platform_data
3 * and place the bfin-rotary onto platform_bus named "bfin-rotary".
4 *
5 * Copyright 2008-2010 Analog Devices Inc.
6 *
7 * Licensed under the GPL-2 or later.
8 */
9
10#ifndef _BFIN_ROTARY_H
11#define _BFIN_ROTARY_H
12
13/* mode bitmasks */
14#define ROT_QUAD_ENC CNTMODE_QUADENC /* quadrature/grey code encoder mode */
15#define ROT_BIN_ENC CNTMODE_BINENC /* binary encoder mode */
16#define ROT_UD_CNT CNTMODE_UDCNT /* rotary counter mode */
17#define ROT_DIR_CNT CNTMODE_DIRCNT /* direction counter mode */
18
19#define ROT_DEBE DEBE /* Debounce Enable */
20
21#define ROT_CDGINV CDGINV /* CDG Pin Polarity Invert */
22#define ROT_CUDINV CUDINV /* CUD Pin Polarity Invert */
23#define ROT_CZMINV CZMINV /* CZM Pin Polarity Invert */
24
25struct bfin_rotary_platform_data {
26 /* set rotary UP KEY_### or BTN_### in case you prefer
27 * bfin-rotary to send EV_KEY otherwise set 0
28 */
29 unsigned int rotary_up_key;
30 /* set rotary DOWN KEY_### or BTN_### in case you prefer
31 * bfin-rotary to send EV_KEY otherwise set 0
32 */
33 unsigned int rotary_down_key;
34 /* set rotary BUTTON KEY_### or BTN_### */
35 unsigned int rotary_button_key;
36 /* set rotary Relative Axis REL_### in case you prefer
37 * bfin-rotary to send EV_REL otherwise set 0
38 */
39 unsigned int rotary_rel_code;
40 unsigned short debounce; /* 0..17 */
41 unsigned short mode;
42 unsigned short pm_wakeup;
43 unsigned short *pin_list;
44};
45
46/* CNT_CONFIG bitmasks */
47#define CNTE (1 << 0) /* Counter Enable */
48#define DEBE (1 << 1) /* Debounce Enable */
49#define CDGINV (1 << 4) /* CDG Pin Polarity Invert */
50#define CUDINV (1 << 5) /* CUD Pin Polarity Invert */
51#define CZMINV (1 << 6) /* CZM Pin Polarity Invert */
52#define CNTMODE_SHIFT 8
53#define CNTMODE (0x7 << CNTMODE_SHIFT) /* Counter Operating Mode */
54#define ZMZC (1 << 1) /* CZM Zeroes Counter Enable */
55#define BNDMODE_SHIFT 12
56#define BNDMODE (0x3 << BNDMODE_SHIFT) /* Boundary register Mode */
57#define INPDIS (1 << 15) /* CUG and CDG Input Disable */
58
59#define CNTMODE_QUADENC (0 << CNTMODE_SHIFT) /* quadrature encoder mode */
60#define CNTMODE_BINENC (1 << CNTMODE_SHIFT) /* binary encoder mode */
61#define CNTMODE_UDCNT (2 << CNTMODE_SHIFT) /* up/down counter mode */
62#define CNTMODE_DIRCNT (4 << CNTMODE_SHIFT) /* direction counter mode */
63#define CNTMODE_DIRTMR (5 << CNTMODE_SHIFT) /* direction timer mode */
64
65#define BNDMODE_COMP (0 << BNDMODE_SHIFT) /* boundary compare mode */
66#define BNDMODE_ZERO (1 << BNDMODE_SHIFT) /* boundary compare and zero mode */
67#define BNDMODE_CAPT (2 << BNDMODE_SHIFT) /* boundary capture mode */
68#define BNDMODE_AEXT (3 << BNDMODE_SHIFT) /* boundary auto-extend mode */
69
70/* CNT_IMASK bitmasks */
71#define ICIE (1 << 0) /* Illegal Gray/Binary Code Interrupt Enable */
72#define UCIE (1 << 1) /* Up count Interrupt Enable */
73#define DCIE (1 << 2) /* Down count Interrupt Enable */
74#define MINCIE (1 << 3) /* Min Count Interrupt Enable */
75#define MAXCIE (1 << 4) /* Max Count Interrupt Enable */
76#define COV31IE (1 << 5) /* Bit 31 Overflow Interrupt Enable */
77#define COV15IE (1 << 6) /* Bit 15 Overflow Interrupt Enable */
78#define CZEROIE (1 << 7) /* Count to Zero Interrupt Enable */
79#define CZMIE (1 << 8) /* CZM Pin Interrupt Enable */
80#define CZMEIE (1 << 9) /* CZM Error Interrupt Enable */
81#define CZMZIE (1 << 10) /* CZM Zeroes Counter Interrupt Enable */
82
83/* CNT_STATUS bitmasks */
84#define ICII (1 << 0) /* Illegal Gray/Binary Code Interrupt Identifier */
85#define UCII (1 << 1) /* Up count Interrupt Identifier */
86#define DCII (1 << 2) /* Down count Interrupt Identifier */
87#define MINCII (1 << 3) /* Min Count Interrupt Identifier */
88#define MAXCII (1 << 4) /* Max Count Interrupt Identifier */
89#define COV31II (1 << 5) /* Bit 31 Overflow Interrupt Identifier */
90#define COV15II (1 << 6) /* Bit 15 Overflow Interrupt Identifier */
91#define CZEROII (1 << 7) /* Count to Zero Interrupt Identifier */
92#define CZMII (1 << 8) /* CZM Pin Interrupt Identifier */
93#define CZMEII (1 << 9) /* CZM Error Interrupt Identifier */
94#define CZMZII (1 << 10) /* CZM Zeroes Counter Interrupt Identifier */
95
96/* CNT_COMMAND bitmasks */
97#define W1LCNT 0xf /* Load Counter Register */
98#define W1LMIN 0xf0 /* Load Min Register */
99#define W1LMAX 0xf00 /* Load Max Register */
100#define W1ZMONCE (1 << 12) /* Enable CZM Clear Counter Once */
101
102#define W1LCNT_ZERO (1 << 0) /* write 1 to load CNT_COUNTER with zero */
103#define W1LCNT_MIN (1 << 2) /* write 1 to load CNT_COUNTER from CNT_MIN */
104#define W1LCNT_MAX (1 << 3) /* write 1 to load CNT_COUNTER from CNT_MAX */
105
106#define W1LMIN_ZERO (1 << 4) /* write 1 to load CNT_MIN with zero */
107#define W1LMIN_CNT (1 << 5) /* write 1 to load CNT_MIN from CNT_COUNTER */
108#define W1LMIN_MAX (1 << 7) /* write 1 to load CNT_MIN from CNT_MAX */
109
110#define W1LMAX_ZERO (1 << 8) /* write 1 to load CNT_MAX with zero */
111#define W1LMAX_CNT (1 << 9) /* write 1 to load CNT_MAX from CNT_COUNTER */
112#define W1LMAX_MIN (1 << 10) /* write 1 to load CNT_MAX from CNT_MIN */
113
114/* CNT_DEBOUNCE bitmasks */
115#define DPRESCALE 0xf /* Load Counter Register */
116
117#endif
diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h
index d8155c005242..87ac14c584f2 100644
--- a/include/linux/platform_data/dma-dw.h
+++ b/include/linux/platform_data/dma-dw.h
@@ -13,10 +13,12 @@
13 13
14#include <linux/device.h> 14#include <linux/device.h>
15 15
16#define DW_DMA_MAX_NR_MASTERS 4
17
16/** 18/**
17 * struct dw_dma_slave - Controller-specific information about a slave 19 * struct dw_dma_slave - Controller-specific information about a slave
18 * 20 *
19 * @dma_dev: required DMA master device. Depricated. 21 * @dma_dev: required DMA master device
20 * @src_id: src request line 22 * @src_id: src request line
21 * @dst_id: dst request line 23 * @dst_id: dst request line
22 * @src_master: src master for transfers on allocated channel. 24 * @src_master: src master for transfers on allocated channel.
@@ -53,7 +55,7 @@ struct dw_dma_platform_data {
53 unsigned char chan_priority; 55 unsigned char chan_priority;
54 unsigned short block_size; 56 unsigned short block_size;
55 unsigned char nr_masters; 57 unsigned char nr_masters;
56 unsigned char data_width[4]; 58 unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
57}; 59};
58 60
59#endif /* _PLATFORM_DATA_DMA_DW_H */ 61#endif /* _PLATFORM_DATA_DMA_DW_H */
diff --git a/include/linux/platform_data/dma-mmp_tdma.h b/include/linux/platform_data/dma-mmp_tdma.h
index 66574ea39f97..0c72886030ef 100644
--- a/include/linux/platform_data/dma-mmp_tdma.h
+++ b/include/linux/platform_data/dma-mmp_tdma.h
@@ -28,6 +28,13 @@ struct sram_platdata {
28 int granularity; 28 int granularity;
29}; 29};
30 30
31#ifdef CONFIG_ARM
31extern struct gen_pool *sram_get_gpool(char *pool_name); 32extern struct gen_pool *sram_get_gpool(char *pool_name);
33#else
34static inline struct gen_pool *sram_get_gpool(char *pool_name)
35{
36 return NULL;
37}
38#endif
32 39
33#endif /* __DMA_MMP_TDMA_H */ 40#endif /* __DMA_MMP_TDMA_H */
diff --git a/include/linux/rhashtable.h b/include/linux/rhashtable.h
index 58851275fed9..d438eeb08bff 100644
--- a/include/linux/rhashtable.h
+++ b/include/linux/rhashtable.h
@@ -54,10 +54,11 @@ struct rhash_head {
54 * @buckets: size * hash buckets 54 * @buckets: size * hash buckets
55 */ 55 */
56struct bucket_table { 56struct bucket_table {
57 size_t size; 57 size_t size;
58 unsigned int locks_mask; 58 unsigned int locks_mask;
59 spinlock_t *locks; 59 spinlock_t *locks;
60 struct rhash_head __rcu *buckets[]; 60
61 struct rhash_head __rcu *buckets[] ____cacheline_aligned_in_smp;
61}; 62};
62 63
63typedef u32 (*rht_hashfn_t)(const void *data, u32 len, u32 seed); 64typedef u32 (*rht_hashfn_t)(const void *data, u32 len, u32 seed);
@@ -78,12 +79,6 @@ struct rhashtable;
78 * @locks_mul: Number of bucket locks to allocate per cpu (default: 128) 79 * @locks_mul: Number of bucket locks to allocate per cpu (default: 128)
79 * @hashfn: Function to hash key 80 * @hashfn: Function to hash key
80 * @obj_hashfn: Function to hash object 81 * @obj_hashfn: Function to hash object
81 * @grow_decision: If defined, may return true if table should expand
82 * @shrink_decision: If defined, may return true if table should shrink
83 *
84 * Note: when implementing the grow and shrink decision function, min/max
85 * shift must be enforced, otherwise, resizing watermarks they set may be
86 * useless.
87 */ 82 */
88struct rhashtable_params { 83struct rhashtable_params {
89 size_t nelem_hint; 84 size_t nelem_hint;
@@ -97,10 +92,6 @@ struct rhashtable_params {
97 size_t locks_mul; 92 size_t locks_mul;
98 rht_hashfn_t hashfn; 93 rht_hashfn_t hashfn;
99 rht_obj_hashfn_t obj_hashfn; 94 rht_obj_hashfn_t obj_hashfn;
100 bool (*grow_decision)(const struct rhashtable *ht,
101 size_t new_size);
102 bool (*shrink_decision)(const struct rhashtable *ht,
103 size_t new_size);
104}; 95};
105 96
106/** 97/**
@@ -192,9 +183,6 @@ int rhashtable_init(struct rhashtable *ht, struct rhashtable_params *params);
192void rhashtable_insert(struct rhashtable *ht, struct rhash_head *node); 183void rhashtable_insert(struct rhashtable *ht, struct rhash_head *node);
193bool rhashtable_remove(struct rhashtable *ht, struct rhash_head *node); 184bool rhashtable_remove(struct rhashtable *ht, struct rhash_head *node);
194 185
195bool rht_grow_above_75(const struct rhashtable *ht, size_t new_size);
196bool rht_shrink_below_30(const struct rhashtable *ht, size_t new_size);
197
198int rhashtable_expand(struct rhashtable *ht); 186int rhashtable_expand(struct rhashtable *ht);
199int rhashtable_shrink(struct rhashtable *ht); 187int rhashtable_shrink(struct rhashtable *ht);
200 188
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 41c60e5302d7..6d77432e14ff 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -363,9 +363,6 @@ extern void show_regs(struct pt_regs *);
363 */ 363 */
364extern void show_stack(struct task_struct *task, unsigned long *sp); 364extern void show_stack(struct task_struct *task, unsigned long *sp);
365 365
366void io_schedule(void);
367long io_schedule_timeout(long timeout);
368
369extern void cpu_init (void); 366extern void cpu_init (void);
370extern void trap_init(void); 367extern void trap_init(void);
371extern void update_process_times(int user); 368extern void update_process_times(int user);
@@ -422,6 +419,13 @@ extern signed long schedule_timeout_uninterruptible(signed long timeout);
422asmlinkage void schedule(void); 419asmlinkage void schedule(void);
423extern void schedule_preempt_disabled(void); 420extern void schedule_preempt_disabled(void);
424 421
422extern long io_schedule_timeout(long timeout);
423
424static inline void io_schedule(void)
425{
426 io_schedule_timeout(MAX_SCHEDULE_TIMEOUT);
427}
428
425struct nsproxy; 429struct nsproxy;
426struct user_namespace; 430struct user_namespace;
427 431
diff --git a/include/linux/sunrpc/metrics.h b/include/linux/sunrpc/metrics.h
index 7e61a17030a4..694eecb2f1b5 100644
--- a/include/linux/sunrpc/metrics.h
+++ b/include/linux/sunrpc/metrics.h
@@ -89,8 +89,11 @@ void rpc_free_iostats(struct rpc_iostats *);
89static inline struct rpc_iostats *rpc_alloc_iostats(struct rpc_clnt *clnt) { return NULL; } 89static inline struct rpc_iostats *rpc_alloc_iostats(struct rpc_clnt *clnt) { return NULL; }
90static inline void rpc_count_iostats(const struct rpc_task *task, 90static inline void rpc_count_iostats(const struct rpc_task *task,
91 struct rpc_iostats *stats) {} 91 struct rpc_iostats *stats) {}
92static inline void rpc_count_iostats_metrics(const struct rpc_task *, 92static inline void rpc_count_iostats_metrics(const struct rpc_task *task,
93 struct rpc_iostats *) {} 93 struct rpc_iostats *stats)
94{
95}
96
94static inline void rpc_print_iostats(struct seq_file *seq, struct rpc_clnt *clnt) {} 97static inline void rpc_print_iostats(struct seq_file *seq, struct rpc_clnt *clnt) {}
95static inline void rpc_free_iostats(struct rpc_iostats *stats) {} 98static inline void rpc_free_iostats(struct rpc_iostats *stats) {}
96 99
diff --git a/include/linux/thermal.h b/include/linux/thermal.h
index fc52e307efab..5eac316490ea 100644
--- a/include/linux/thermal.h
+++ b/include/linux/thermal.h
@@ -314,6 +314,8 @@ void thermal_zone_of_sensor_unregister(struct device *dev,
314} 314}
315 315
316#endif 316#endif
317
318#if IS_ENABLED(CONFIG_THERMAL)
317struct thermal_zone_device *thermal_zone_device_register(const char *, int, int, 319struct thermal_zone_device *thermal_zone_device_register(const char *, int, int,
318 void *, struct thermal_zone_device_ops *, 320 void *, struct thermal_zone_device_ops *,
319 const struct thermal_zone_params *, int, int); 321 const struct thermal_zone_params *, int, int);
@@ -340,8 +342,58 @@ struct thermal_instance *get_thermal_instance(struct thermal_zone_device *,
340 struct thermal_cooling_device *, int); 342 struct thermal_cooling_device *, int);
341void thermal_cdev_update(struct thermal_cooling_device *); 343void thermal_cdev_update(struct thermal_cooling_device *);
342void thermal_notify_framework(struct thermal_zone_device *, int); 344void thermal_notify_framework(struct thermal_zone_device *, int);
343 345#else
344#ifdef CONFIG_NET 346static inline struct thermal_zone_device *thermal_zone_device_register(
347 const char *type, int trips, int mask, void *devdata,
348 struct thermal_zone_device_ops *ops,
349 const struct thermal_zone_params *tzp,
350 int passive_delay, int polling_delay)
351{ return ERR_PTR(-ENODEV); }
352static inline void thermal_zone_device_unregister(
353 struct thermal_zone_device *tz)
354{ }
355static inline int thermal_zone_bind_cooling_device(
356 struct thermal_zone_device *tz, int trip,
357 struct thermal_cooling_device *cdev,
358 unsigned long upper, unsigned long lower)
359{ return -ENODEV; }
360static inline int thermal_zone_unbind_cooling_device(
361 struct thermal_zone_device *tz, int trip,
362 struct thermal_cooling_device *cdev)
363{ return -ENODEV; }
364static inline void thermal_zone_device_update(struct thermal_zone_device *tz)
365{ }
366static inline struct thermal_cooling_device *
367thermal_cooling_device_register(char *type, void *devdata,
368 const struct thermal_cooling_device_ops *ops)
369{ return ERR_PTR(-ENODEV); }
370static inline struct thermal_cooling_device *
371thermal_of_cooling_device_register(struct device_node *np,
372 char *type, void *devdata, const struct thermal_cooling_device_ops *ops)
373{ return ERR_PTR(-ENODEV); }
374static inline void thermal_cooling_device_unregister(
375 struct thermal_cooling_device *cdev)
376{ }
377static inline struct thermal_zone_device *thermal_zone_get_zone_by_name(
378 const char *name)
379{ return ERR_PTR(-ENODEV); }
380static inline int thermal_zone_get_temp(
381 struct thermal_zone_device *tz, unsigned long *temp)
382{ return -ENODEV; }
383static inline int get_tz_trend(struct thermal_zone_device *tz, int trip)
384{ return -ENODEV; }
385static inline struct thermal_instance *
386get_thermal_instance(struct thermal_zone_device *tz,
387 struct thermal_cooling_device *cdev, int trip)
388{ return ERR_PTR(-ENODEV); }
389static inline void thermal_cdev_update(struct thermal_cooling_device *cdev)
390{ }
391static inline void thermal_notify_framework(struct thermal_zone_device *tz,
392 int trip)
393{ }
394#endif /* CONFIG_THERMAL */
395
396#if defined(CONFIG_NET) && IS_ENABLED(CONFIG_THERMAL)
345extern int thermal_generate_netlink_event(struct thermal_zone_device *tz, 397extern int thermal_generate_netlink_event(struct thermal_zone_device *tz,
346 enum events event); 398 enum events event);
347#else 399#else
diff --git a/include/linux/vfio.h b/include/linux/vfio.h
index d3204115f15d..2d67b8998fd8 100644
--- a/include/linux/vfio.h
+++ b/include/linux/vfio.h
@@ -26,6 +26,7 @@
26 * @ioctl: Perform ioctl(2) on device file descriptor, supporting VFIO_DEVICE_* 26 * @ioctl: Perform ioctl(2) on device file descriptor, supporting VFIO_DEVICE_*
27 * operations documented below 27 * operations documented below
28 * @mmap: Perform mmap(2) on a region of the device file descriptor 28 * @mmap: Perform mmap(2) on a region of the device file descriptor
29 * @request: Request for the bus driver to release the device
29 */ 30 */
30struct vfio_device_ops { 31struct vfio_device_ops {
31 char *name; 32 char *name;
@@ -38,6 +39,7 @@ struct vfio_device_ops {
38 long (*ioctl)(void *device_data, unsigned int cmd, 39 long (*ioctl)(void *device_data, unsigned int cmd,
39 unsigned long arg); 40 unsigned long arg);
40 int (*mmap)(void *device_data, struct vm_area_struct *vma); 41 int (*mmap)(void *device_data, struct vm_area_struct *vma);
42 void (*request)(void *device_data, unsigned int count);
41}; 43};
42 44
43extern int vfio_add_group_dev(struct device *dev, 45extern int vfio_add_group_dev(struct device *dev,
diff --git a/include/linux/virtio_mmio.h b/include/linux/virtio_mmio.h
index 5c7b6f0daef8..c4b09689ab64 100644
--- a/include/linux/virtio_mmio.h
+++ b/include/linux/virtio_mmio.h
@@ -51,23 +51,29 @@
51/* Virtio vendor ID - Read Only */ 51/* Virtio vendor ID - Read Only */
52#define VIRTIO_MMIO_VENDOR_ID 0x00c 52#define VIRTIO_MMIO_VENDOR_ID 0x00c
53 53
54/* Bitmask of the features supported by the host 54/* Bitmask of the features supported by the device (host)
55 * (32 bits per set) - Read Only */ 55 * (32 bits per set) - Read Only */
56#define VIRTIO_MMIO_HOST_FEATURES 0x010 56#define VIRTIO_MMIO_DEVICE_FEATURES 0x010
57 57
58/* Host features set selector - Write Only */ 58/* Device (host) features set selector - Write Only */
59#define VIRTIO_MMIO_HOST_FEATURES_SEL 0x014 59#define VIRTIO_MMIO_DEVICE_FEATURES_SEL 0x014
60 60
61/* Bitmask of features activated by the guest 61/* Bitmask of features activated by the driver (guest)
62 * (32 bits per set) - Write Only */ 62 * (32 bits per set) - Write Only */
63#define VIRTIO_MMIO_GUEST_FEATURES 0x020 63#define VIRTIO_MMIO_DRIVER_FEATURES 0x020
64 64
65/* Activated features set selector - Write Only */ 65/* Activated features set selector - Write Only */
66#define VIRTIO_MMIO_GUEST_FEATURES_SEL 0x024 66#define VIRTIO_MMIO_DRIVER_FEATURES_SEL 0x024
67
68
69#ifndef VIRTIO_MMIO_NO_LEGACY /* LEGACY DEVICES ONLY! */
67 70
68/* Guest's memory page size in bytes - Write Only */ 71/* Guest's memory page size in bytes - Write Only */
69#define VIRTIO_MMIO_GUEST_PAGE_SIZE 0x028 72#define VIRTIO_MMIO_GUEST_PAGE_SIZE 0x028
70 73
74#endif
75
76
71/* Queue selector - Write Only */ 77/* Queue selector - Write Only */
72#define VIRTIO_MMIO_QUEUE_SEL 0x030 78#define VIRTIO_MMIO_QUEUE_SEL 0x030
73 79
@@ -77,12 +83,21 @@
77/* Queue size for the currently selected queue - Write Only */ 83/* Queue size for the currently selected queue - Write Only */
78#define VIRTIO_MMIO_QUEUE_NUM 0x038 84#define VIRTIO_MMIO_QUEUE_NUM 0x038
79 85
86
87#ifndef VIRTIO_MMIO_NO_LEGACY /* LEGACY DEVICES ONLY! */
88
80/* Used Ring alignment for the currently selected queue - Write Only */ 89/* Used Ring alignment for the currently selected queue - Write Only */
81#define VIRTIO_MMIO_QUEUE_ALIGN 0x03c 90#define VIRTIO_MMIO_QUEUE_ALIGN 0x03c
82 91
83/* Guest's PFN for the currently selected queue - Read Write */ 92/* Guest's PFN for the currently selected queue - Read Write */
84#define VIRTIO_MMIO_QUEUE_PFN 0x040 93#define VIRTIO_MMIO_QUEUE_PFN 0x040
85 94
95#endif
96
97
98/* Ready bit for the currently selected queue - Read Write */
99#define VIRTIO_MMIO_QUEUE_READY 0x044
100
86/* Queue notifier - Write Only */ 101/* Queue notifier - Write Only */
87#define VIRTIO_MMIO_QUEUE_NOTIFY 0x050 102#define VIRTIO_MMIO_QUEUE_NOTIFY 0x050
88 103
@@ -95,6 +110,21 @@
95/* Device status register - Read Write */ 110/* Device status register - Read Write */
96#define VIRTIO_MMIO_STATUS 0x070 111#define VIRTIO_MMIO_STATUS 0x070
97 112
113/* Selected queue's Descriptor Table address, 64 bits in two halves */
114#define VIRTIO_MMIO_QUEUE_DESC_LOW 0x080
115#define VIRTIO_MMIO_QUEUE_DESC_HIGH 0x084
116
117/* Selected queue's Available Ring address, 64 bits in two halves */
118#define VIRTIO_MMIO_QUEUE_AVAIL_LOW 0x090
119#define VIRTIO_MMIO_QUEUE_AVAIL_HIGH 0x094
120
121/* Selected queue's Used Ring address, 64 bits in two halves */
122#define VIRTIO_MMIO_QUEUE_USED_LOW 0x0a0
123#define VIRTIO_MMIO_QUEUE_USED_HIGH 0x0a4
124
125/* Configuration atomicity value */
126#define VIRTIO_MMIO_CONFIG_GENERATION 0x0fc
127
98/* The config space is defined by each driver as 128/* The config space is defined by each driver as
99 * the per-driver configuration space - Read Write */ 129 * the per-driver configuration space - Read Write */
100#define VIRTIO_MMIO_CONFIG 0x100 130#define VIRTIO_MMIO_CONFIG 0x100
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-15 22:26:26 -0400