Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net

Conflicts:
	drivers/net/ethernet/rocker/rocker.c

The rocker commit was two overlapping changes, one to rename
the ->vport member to ->pport, and another making the bitmask
expression use '1ULL' instead of plain '1'.

Signed-off-by: David S. Miller <davem@davemloft.net>

74 files changed, 4232 insertions, 850 deletions

diff --git a/include/acpi/acpi_lpat.h b/include/acpi/acpi_lpat.h
new file mode 100644
index 000000000000..da37e12d23e2
--- /dev/null
+++ b/include/acpi/acpi_lpat.h
@@ -0,0 +1,65 @@
+/*
+ * acpi_lpat.h - LPAT table processing functions
+ *
+ * Copyright (C) 2015 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ACPI_LPAT_H
+#define ACPI_LPAT_H
+
+struct acpi_lpat {
+        int temp;
+        int raw;
+};
+
+struct acpi_lpat_conversion_table {
+        struct acpi_lpat *lpat;
+        int lpat_count;
+};
+
+#ifdef CONFIG_ACPI
+
+int acpi_lpat_raw_to_temp(struct acpi_lpat_conversion_table *lpat_table,
+                          int raw);
+int acpi_lpat_temp_to_raw(struct acpi_lpat_conversion_table *lpat_table,
+                          int temp);
+struct acpi_lpat_conversion_table *acpi_lpat_get_conversion_table(acpi_handle
+                                                                  handle);
+void acpi_lpat_free_conversion_table(struct acpi_lpat_conversion_table
+                                     *lpat_table);
+
+#else
+static int acpi_lpat_raw_to_temp(struct acpi_lpat_conversion_table *lpat_table,
+                                 int raw)
+{
+        return 0;
+}
+
+static int acpi_lpat_temp_to_raw(struct acpi_lpat_conversion_table *lpat_table,
+                                 int temp)
+{
+        return 0;
+}
+
+static struct acpi_lpat_conversion_table *acpi_lpat_get_conversion_table(
+                                                        acpi_handle handle)
+{
+        return NULL;
+}
+
+static void acpi_lpat_free_conversion_table(struct acpi_lpat_conversion_table
+                                            *lpat_table)
+{
+}
+
+#endif
+#endif
diff --git a/include/asm-generic/pci_iomap.h b/include/asm-generic/pci_iomap.h
index ce37349860fe..7389c87116a0 100644
--- a/include/asm-generic/pci_iomap.h
+++ b/include/asm-generic/pci_iomap.h
@@ -15,6 +15,9 @@ struct pci_dev;
 #ifdef CONFIG_PCI
 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
+extern void __iomem *pci_iomap_range(struct pci_dev *dev, int bar,
+                                     unsigned long offset,
+                                     unsigned long maxlen);
 /* Create a virtual mapping cookie for a port on a given PCI device.
  * Do not call this directly, it exists to make it easier for architectures
  * to override */
@@ -30,6 +33,13 @@ static inline void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned lon
 {
         return NULL;
 }
+
+static inline void __iomem *pci_iomap_range(struct pci_dev *dev, int bar,
+                                            unsigned long offset,
+                                            unsigned long maxlen)
+{
+        return NULL;
+}
 #endif
 
 #endif /* __ASM_GENERIC_IO_H */
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 180ad0e6de21..d016dc57f007 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -214,9 +214,9 @@
         INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
 
 #define _INTEL_BDW_M_IDS(gt, info) \
-        _INTEL_BDW_M(gt, 0x1602, info), /* ULT */ \
+        _INTEL_BDW_M(gt, 0x1602, info), /* Halo */ \
         _INTEL_BDW_M(gt, 0x1606, info), /* ULT */ \
-        _INTEL_BDW_M(gt, 0x160B, info), /* Iris */ \
+        _INTEL_BDW_M(gt, 0x160B, info), /* ULT */ \
         _INTEL_BDW_M(gt, 0x160E, info) /* ULX */
 
 #define _INTEL_BDW_D_IDS(gt, info) \
diff --git a/include/dt-bindings/clock/alphascale,asm9260.h b/include/dt-bindings/clock/alphascale,asm9260.h
new file mode 100644
index 000000000000..04e8db27daf0
--- /dev/null
+++ b/include/dt-bindings/clock/alphascale,asm9260.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ASM9260_H
+#define _DT_BINDINGS_CLK_ASM9260_H
+
+/* ahb gate */
+#define CLKID_AHB_ROM           0
+#define CLKID_AHB_RAM           1
+#define CLKID_AHB_GPIO          2
+#define CLKID_AHB_MAC           3
+#define CLKID_AHB_EMI           4
+#define CLKID_AHB_USB0          5
+#define CLKID_AHB_USB1          6
+#define CLKID_AHB_DMA0          7
+#define CLKID_AHB_DMA1          8
+#define CLKID_AHB_UART0         9
+#define CLKID_AHB_UART1         10
+#define CLKID_AHB_UART2         11
+#define CLKID_AHB_UART3         12
+#define CLKID_AHB_UART4         13
+#define CLKID_AHB_UART5         14
+#define CLKID_AHB_UART6         15
+#define CLKID_AHB_UART7         16
+#define CLKID_AHB_UART8         17
+#define CLKID_AHB_UART9         18
+#define CLKID_AHB_I2S0          19
+#define CLKID_AHB_I2C0          20
+#define CLKID_AHB_I2C1          21
+#define CLKID_AHB_SSP0          22
+#define CLKID_AHB_IOCONFIG      23
+#define CLKID_AHB_WDT           24
+#define CLKID_AHB_CAN0          25
+#define CLKID_AHB_CAN1          26
+#define CLKID_AHB_MPWM          27
+#define CLKID_AHB_SPI0          28
+#define CLKID_AHB_SPI1          29
+#define CLKID_AHB_QEI           30
+#define CLKID_AHB_QUADSPI0      31
+#define CLKID_AHB_CAMIF         32
+#define CLKID_AHB_LCDIF         33
+#define CLKID_AHB_TIMER0        34
+#define CLKID_AHB_TIMER1        35
+#define CLKID_AHB_TIMER2        36
+#define CLKID_AHB_TIMER3        37
+#define CLKID_AHB_IRQ           38
+#define CLKID_AHB_RTC           39
+#define CLKID_AHB_NAND          40
+#define CLKID_AHB_ADC0          41
+#define CLKID_AHB_LED           42
+#define CLKID_AHB_DAC0          43
+#define CLKID_AHB_LCD           44
+#define CLKID_AHB_I2S1          45
+#define CLKID_AHB_MAC1          46
+
+/* devider */
+#define CLKID_SYS_CPU           47
+#define CLKID_SYS_AHB           48
+#define CLKID_SYS_I2S0M         49
+#define CLKID_SYS_I2S0S         50
+#define CLKID_SYS_I2S1M         51
+#define CLKID_SYS_I2S1S         52
+#define CLKID_SYS_UART0         53
+#define CLKID_SYS_UART1         54
+#define CLKID_SYS_UART2         55
+#define CLKID_SYS_UART3         56
+#define CLKID_SYS_UART4         56
+#define CLKID_SYS_UART5         57
+#define CLKID_SYS_UART6         58
+#define CLKID_SYS_UART7         59
+#define CLKID_SYS_UART8         60
+#define CLKID_SYS_UART9         61
+#define CLKID_SYS_SPI0          62
+#define CLKID_SYS_SPI1          63
+#define CLKID_SYS_QUADSPI       64
+#define CLKID_SYS_SSP0          65
+#define CLKID_SYS_NAND          66
+#define CLKID_SYS_TRACE         67
+#define CLKID_SYS_CAMM          68
+#define CLKID_SYS_WDT           69
+#define CLKID_SYS_CLKOUT        70
+#define CLKID_SYS_MAC           71
+#define CLKID_SYS_LCD           72
+#define CLKID_SYS_ADCANA        73
+
+#define MAX_CLKS                74
+#endif
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 34fe28c622d0..c4b1676ea674 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -262,8 +262,13 @@
 #define CLK_DIV_MCUISP1         453 /* Exynos4x12 only */
 #define CLK_DIV_ACLK200         454 /* Exynos4x12 only */
 #define CLK_DIV_ACLK400_MCUISP  455 /* Exynos4x12 only */
+#define CLK_DIV_ACP             456
+#define CLK_DIV_DMC             457
+#define CLK_DIV_C2C             458 /* Exynos4x12 only */
+#define CLK_DIV_GDL             459
+#define CLK_DIV_GDR             460
 
 /* must be greater than maximal clock id */
-#define CLK_NR_CLKS             456
+#define CLK_NR_CLKS             461
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 8e4681b07ae7..e33c75a3c09d 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -17,7 +17,11 @@
 #define DOUT_SCLK_CC_PLL                4
 #define DOUT_SCLK_MFC_PLL               5
 #define DOUT_ACLK_CCORE_133             6
-#define TOPC_NR_CLK                     7
+#define DOUT_ACLK_MSCL_532              7
+#define ACLK_MSCL_532                   8
+#define DOUT_SCLK_AUD_PLL               9
+#define FOUT_AUD_PLL                    10
+#define TOPC_NR_CLK                     11
 
 /* TOP0 */
 #define DOUT_ACLK_PERIC1                1
@@ -26,7 +30,15 @@
 #define CLK_SCLK_UART1                  4
 #define CLK_SCLK_UART2                  5
 #define CLK_SCLK_UART3                  6
-#define TOP0_NR_CLK                     7
+#define CLK_SCLK_SPI0                   7
+#define CLK_SCLK_SPI1                   8
+#define CLK_SCLK_SPI2                   9
+#define CLK_SCLK_SPI3                   10
+#define CLK_SCLK_SPI4                   11
+#define CLK_SCLK_SPDIF                  12
+#define CLK_SCLK_PCM1                   13
+#define CLK_SCLK_I2S1                   14
+#define TOP0_NR_CLK                     15
 
 /* TOP1 */
 #define DOUT_ACLK_FSYS1_200             1
@@ -70,7 +82,23 @@
 #define PCLK_HSI2C6                     9
 #define PCLK_HSI2C7                     10
 #define PCLK_HSI2C8                     11
-#define PERIC1_NR_CLK                   12
+#define PCLK_SPI0                       12
+#define PCLK_SPI1                       13
+#define PCLK_SPI2                       14
+#define PCLK_SPI3                       15
+#define PCLK_SPI4                       16
+#define SCLK_SPI0                       17
+#define SCLK_SPI1                       18
+#define SCLK_SPI2                       19
+#define SCLK_SPI3                       20
+#define SCLK_SPI4                       21
+#define PCLK_I2S1                       22
+#define PCLK_PCM1                       23
+#define PCLK_SPDIF                      24
+#define SCLK_I2S1                       25
+#define SCLK_PCM1                       26
+#define SCLK_SPDIF                      27
+#define PERIC1_NR_CLK                   28
 
 /* PERIS */
 #define PCLK_CHIPID                     1
@@ -82,11 +110,63 @@
 
 /* FSYS0 */
 #define ACLK_MMC2                       1
-#define FSYS0_NR_CLK                    2
+#define ACLK_AXIUS_USBDRD30X_FSYS0X     2
+#define ACLK_USBDRD300                  3
+#define SCLK_USBDRD300_SUSPENDCLK       4
+#define SCLK_USBDRD300_REFCLK           5
+#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER          6
+#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER             7
+#define OSCCLK_PHY_CLKOUT_USB30_PHY             8
+#define ACLK_PDMA0                      9
+#define ACLK_PDMA1                      10
+#define FSYS0_NR_CLK                    11
 
 /* FSYS1 */
 #define ACLK_MMC1                       1
 #define ACLK_MMC0                       2
 #define FSYS1_NR_CLK                    3
 
+/* MSCL */
+#define USERMUX_ACLK_MSCL_532           1
+#define DOUT_PCLK_MSCL                  2
+#define ACLK_MSCL_0                     3
+#define ACLK_MSCL_1                     4
+#define ACLK_JPEG                       5
+#define ACLK_G2D                        6
+#define ACLK_LH_ASYNC_SI_MSCL_0         7
+#define ACLK_LH_ASYNC_SI_MSCL_1         8
+#define ACLK_AXI2ACEL_BRIDGE            9
+#define ACLK_XIU_MSCLX_0                10
+#define ACLK_XIU_MSCLX_1                11
+#define ACLK_QE_MSCL_0                  12
+#define ACLK_QE_MSCL_1                  13
+#define ACLK_QE_JPEG                    14
+#define ACLK_QE_G2D                     15
+#define ACLK_PPMU_MSCL_0                16
+#define ACLK_PPMU_MSCL_1                17
+#define ACLK_MSCLNP_133                 18
+#define ACLK_AHB2APB_MSCL0P             19
+#define ACLK_AHB2APB_MSCL1P             20
+
+#define PCLK_MSCL_0                     21
+#define PCLK_MSCL_1                     22
+#define PCLK_JPEG                       23
+#define PCLK_G2D                        24
+#define PCLK_QE_MSCL_0                  25
+#define PCLK_QE_MSCL_1                  26
+#define PCLK_QE_JPEG                    27
+#define PCLK_QE_G2D                     28
+#define PCLK_PPMU_MSCL_0                29
+#define PCLK_PPMU_MSCL_1                30
+#define PCLK_AXI2ACEL_BRIDGE            31
+#define PCLK_PMU_MSCL                   32
+#define MSCL_NR_CLK                     33
+
+/* AUD */
+#define SCLK_I2S                        1
+#define SCLK_PCM                        2
+#define PCLK_I2S                        3
+#define PCLK_PCM                        4
+#define ACLK_ADMA                       5
+#define AUD_NR_CLK                      6
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
index b857cadb0bd4..04fb29ae30e6 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -238,7 +238,6 @@
 #define PLL0_VOTE                               221
 #define PLL3                                    222
 #define PLL3_VOTE                               223
-#define PLL4                                    224
 #define PLL4_VOTE                               225
 #define PLL8                                    226
 #define PLL8_VOTE                               227
diff --git a/include/dt-bindings/clock/qcom,lcc-ipq806x.h b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
new file mode 100644
index 000000000000..4e944b85c56d
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_LCC_IPQ806X_H
+#define _DT_BINDINGS_CLK_LCC_IPQ806X_H
+
+#define PLL4                            0
+#define MI2S_OSR_SRC                    1
+#define MI2S_OSR_CLK                    2
+#define MI2S_DIV_CLK                    3
+#define MI2S_BIT_DIV_CLK                4
+#define MI2S_BIT_CLK                    5
+#define PCM_SRC                         6
+#define PCM_CLK_OUT                     7
+#define PCM_CLK                         8
+#define SPDIF_SRC                       9
+#define SPDIF_CLK                       10
+#define AHBIX_CLK                       11
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,lcc-msm8960.h b/include/dt-bindings/clock/qcom,lcc-msm8960.h
new file mode 100644
index 000000000000..4fb2aa64d9fe
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,lcc-msm8960.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_LCC_MSM8960_H
+#define _DT_BINDINGS_CLK_LCC_MSM8960_H
+
+#define PLL4                            0
+#define MI2S_OSR_SRC                    1
+#define MI2S_OSR_CLK                    2
+#define MI2S_DIV_CLK                    3
+#define MI2S_BIT_DIV_CLK                4
+#define MI2S_BIT_CLK                    5
+#define PCM_SRC                         6
+#define PCM_CLK_OUT                     7
+#define PCM_CLK                         8
+#define SLIMBUS_SRC                     9
+#define AUDIO_SLIMBUS_CLK               10
+#define SPS_SLIMBUS_CLK                 11
+#define CODEC_I2S_MIC_OSR_SRC           12
+#define CODEC_I2S_MIC_OSR_CLK           13
+#define CODEC_I2S_MIC_DIV_CLK           14
+#define CODEC_I2S_MIC_BIT_DIV_CLK       15
+#define CODEC_I2S_MIC_BIT_CLK           16
+#define SPARE_I2S_MIC_OSR_SRC           17
+#define SPARE_I2S_MIC_OSR_CLK           18
+#define SPARE_I2S_MIC_DIV_CLK           19
+#define SPARE_I2S_MIC_BIT_DIV_CLK       20
+#define SPARE_I2S_MIC_BIT_CLK           21
+#define CODEC_I2S_SPKR_OSR_SRC          22
+#define CODEC_I2S_SPKR_OSR_CLK          23
+#define CODEC_I2S_SPKR_DIV_CLK          24
+#define CODEC_I2S_SPKR_BIT_DIV_CLK      25
+#define CODEC_I2S_SPKR_BIT_CLK          26
+#define SPARE_I2S_SPKR_OSR_SRC          27
+#define SPARE_I2S_SPKR_OSR_CLK          28
+#define SPARE_I2S_SPKR_DIV_CLK          29
+#define SPARE_I2S_SPKR_BIT_DIV_CLK      30
+#define SPARE_I2S_SPKR_BIT_CLK          31
+
+#endif
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h
new file mode 100644
index 000000000000..ae2eb17a1658
--- /dev/null
+++ b/include/dt-bindings/clock/tegra124-car-common.h
@@ -0,0 +1,345 @@
+/*
+ * This header provides constants for binding nvidia,tegra124-car or
+ * nvidia,tegra132-car.
+ *
+ * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 185 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
+#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
+
+/* 0 */
+/* 1 */
+/* 2 */
+#define TEGRA124_CLK_ISPB 3
+#define TEGRA124_CLK_RTC 4
+#define TEGRA124_CLK_TIMER 5
+#define TEGRA124_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+/* 8 */
+#define TEGRA124_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA124_CLK_I2S1 11
+#define TEGRA124_CLK_I2C1 12
+/* 13 */
+#define TEGRA124_CLK_SDMMC1 14
+#define TEGRA124_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA124_CLK_PWM 17
+#define TEGRA124_CLK_I2S2 18
+/* 20 (register bit affects vi and vi_sensor) */
+/* 21 */
+#define TEGRA124_CLK_USBD 22
+#define TEGRA124_CLK_ISP 23
+/* 26 */
+/* 25 */
+#define TEGRA124_CLK_DISP2 26
+#define TEGRA124_CLK_DISP1 27
+#define TEGRA124_CLK_HOST1X 28
+#define TEGRA124_CLK_VCP 29
+#define TEGRA124_CLK_I2S0 30
+/* 31 */
+
+#define TEGRA124_CLK_MC 32
+/* 33 */
+#define TEGRA124_CLK_APBDMA 34
+/* 35 */
+#define TEGRA124_CLK_KBC 36
+/* 37 */
+/* 38 */
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA124_CLK_KFUSE 40
+#define TEGRA124_CLK_SBC1 41
+#define TEGRA124_CLK_NOR 42
+/* 43 */
+#define TEGRA124_CLK_SBC2 44
+/* 45 */
+#define TEGRA124_CLK_SBC3 46
+#define TEGRA124_CLK_I2C5 47
+#define TEGRA124_CLK_DSIA 48
+/* 49 */
+#define TEGRA124_CLK_MIPI 50
+#define TEGRA124_CLK_HDMI 51
+#define TEGRA124_CLK_CSI 52
+/* 53 */
+#define TEGRA124_CLK_I2C2 54
+#define TEGRA124_CLK_UARTC 55
+#define TEGRA124_CLK_MIPI_CAL 56
+#define TEGRA124_CLK_EMC 57
+#define TEGRA124_CLK_USB2 58
+#define TEGRA124_CLK_USB3 59
+/* 60 */
+#define TEGRA124_CLK_VDE 61
+#define TEGRA124_CLK_BSEA 62
+#define TEGRA124_CLK_BSEV 63
+
+/* 64 */
+#define TEGRA124_CLK_UARTD 65
+/* 66 */
+#define TEGRA124_CLK_I2C3 67
+#define TEGRA124_CLK_SBC4 68
+#define TEGRA124_CLK_SDMMC3 69
+#define TEGRA124_CLK_PCIE 70
+#define TEGRA124_CLK_OWR 71
+#define TEGRA124_CLK_AFI 72
+#define TEGRA124_CLK_CSITE 73
+/* 74 */
+/* 75 */
+#define TEGRA124_CLK_LA 76
+#define TEGRA124_CLK_TRACE 77
+#define TEGRA124_CLK_SOC_THERM 78
+#define TEGRA124_CLK_DTV 79
+/* 80 */
+#define TEGRA124_CLK_I2CSLOW 81
+#define TEGRA124_CLK_DSIB 82
+#define TEGRA124_CLK_TSEC 83
+/* 84 */
+/* 85 */
+/* 86 */
+/* 87 */
+/* 88 */
+#define TEGRA124_CLK_XUSB_HOST 89
+/* 90 */
+#define TEGRA124_CLK_MSENC 91
+#define TEGRA124_CLK_CSUS 92
+/* 93 */
+/* 94 */
+/* 95 (bit affects xusb_dev and xusb_dev_src) */
+
+/* 96 */
+/* 97 */
+/* 98 */
+#define TEGRA124_CLK_MSELECT 99
+#define TEGRA124_CLK_TSENSOR 100
+#define TEGRA124_CLK_I2S3 101
+#define TEGRA124_CLK_I2S4 102
+#define TEGRA124_CLK_I2C4 103
+#define TEGRA124_CLK_SBC5 104
+#define TEGRA124_CLK_SBC6 105
+#define TEGRA124_CLK_D_AUDIO 106
+#define TEGRA124_CLK_APBIF 107
+#define TEGRA124_CLK_DAM0 108
+#define TEGRA124_CLK_DAM1 109
+#define TEGRA124_CLK_DAM2 110
+#define TEGRA124_CLK_HDA2CODEC_2X 111
+/* 112 */
+#define TEGRA124_CLK_AUDIO0_2X 113
+#define TEGRA124_CLK_AUDIO1_2X 114
+#define TEGRA124_CLK_AUDIO2_2X 115
+#define TEGRA124_CLK_AUDIO3_2X 116
+#define TEGRA124_CLK_AUDIO4_2X 117
+#define TEGRA124_CLK_SPDIF_2X 118
+#define TEGRA124_CLK_ACTMON 119
+#define TEGRA124_CLK_EXTERN1 120
+#define TEGRA124_CLK_EXTERN2 121
+#define TEGRA124_CLK_EXTERN3 122
+#define TEGRA124_CLK_SATA_OOB 123
+#define TEGRA124_CLK_SATA 124
+#define TEGRA124_CLK_HDA 125
+/* 126 */
+#define TEGRA124_CLK_SE 127
+
+#define TEGRA124_CLK_HDA2HDMI 128
+#define TEGRA124_CLK_SATA_COLD 129
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+/* 136 */
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
+/*      xusb_host_src and xusb_ss_src) */
+#define TEGRA124_CLK_CILAB 144
+#define TEGRA124_CLK_CILCD 145
+#define TEGRA124_CLK_CILE 146
+#define TEGRA124_CLK_DSIALP 147
+#define TEGRA124_CLK_DSIBLP 148
+#define TEGRA124_CLK_ENTROPY 149
+#define TEGRA124_CLK_DDS 150
+/* 151 */
+#define TEGRA124_CLK_DP2 152
+#define TEGRA124_CLK_AMX 153
+#define TEGRA124_CLK_ADX 154
+/* 155 (bit affects dfll_ref and dfll_soc) */
+#define TEGRA124_CLK_XUSB_SS 156
+/* 157 */
+/* 158 */
+/* 159 */
+
+/* 160 */
+/* 161 */
+/* 162 */
+/* 163 */
+/* 164 */
+/* 165 */
+#define TEGRA124_CLK_I2C6 166
+/* 167 */
+/* 168 */
+/* 169 */
+/* 170 */
+#define TEGRA124_CLK_VIM2_CLK 171
+/* 172 */
+/* 173 */
+/* 174 */
+/* 175 */
+#define TEGRA124_CLK_HDMI_AUDIO 176
+#define TEGRA124_CLK_CLK72MHZ 177
+#define TEGRA124_CLK_VIC03 178
+/* 179 */
+#define TEGRA124_CLK_ADX1 180
+#define TEGRA124_CLK_DPAUX 181
+#define TEGRA124_CLK_SOR0 182
+/* 183 */
+#define TEGRA124_CLK_GPU 184
+#define TEGRA124_CLK_AMX1 185
+/* 186 */
+/* 187 */
+/* 188 */
+/* 189 */
+/* 190 */
+/* 191 */
+#define TEGRA124_CLK_UARTB 192
+#define TEGRA124_CLK_VFIR 193
+#define TEGRA124_CLK_SPDIF_IN 194
+#define TEGRA124_CLK_SPDIF_OUT 195
+#define TEGRA124_CLK_VI 196
+#define TEGRA124_CLK_VI_SENSOR 197
+#define TEGRA124_CLK_FUSE 198
+#define TEGRA124_CLK_FUSE_BURN 199
+#define TEGRA124_CLK_CLK_32K 200
+#define TEGRA124_CLK_CLK_M 201
+#define TEGRA124_CLK_CLK_M_DIV2 202
+#define TEGRA124_CLK_CLK_M_DIV4 203
+#define TEGRA124_CLK_PLL_REF 204
+#define TEGRA124_CLK_PLL_C 205
+#define TEGRA124_CLK_PLL_C_OUT1 206
+#define TEGRA124_CLK_PLL_C2 207
+#define TEGRA124_CLK_PLL_C3 208
+#define TEGRA124_CLK_PLL_M 209
+#define TEGRA124_CLK_PLL_M_OUT1 210
+#define TEGRA124_CLK_PLL_P 211
+#define TEGRA124_CLK_PLL_P_OUT1 212
+#define TEGRA124_CLK_PLL_P_OUT2 213
+#define TEGRA124_CLK_PLL_P_OUT3 214
+#define TEGRA124_CLK_PLL_P_OUT4 215
+#define TEGRA124_CLK_PLL_A 216
+#define TEGRA124_CLK_PLL_A_OUT0 217
+#define TEGRA124_CLK_PLL_D 218
+#define TEGRA124_CLK_PLL_D_OUT0 219
+#define TEGRA124_CLK_PLL_D2 220
+#define TEGRA124_CLK_PLL_D2_OUT0 221
+#define TEGRA124_CLK_PLL_U 222
+#define TEGRA124_CLK_PLL_U_480M 223
+
+#define TEGRA124_CLK_PLL_U_60M 224
+#define TEGRA124_CLK_PLL_U_48M 225
+#define TEGRA124_CLK_PLL_U_12M 226
+/* 227 */
+/* 228 */
+#define TEGRA124_CLK_PLL_RE_VCO 229
+#define TEGRA124_CLK_PLL_RE_OUT 230
+#define TEGRA124_CLK_PLL_E 231
+#define TEGRA124_CLK_SPDIF_IN_SYNC 232
+#define TEGRA124_CLK_I2S0_SYNC 233
+#define TEGRA124_CLK_I2S1_SYNC 234
+#define TEGRA124_CLK_I2S2_SYNC 235
+#define TEGRA124_CLK_I2S3_SYNC 236
+#define TEGRA124_CLK_I2S4_SYNC 237
+#define TEGRA124_CLK_VIMCLK_SYNC 238
+#define TEGRA124_CLK_AUDIO0 239
+#define TEGRA124_CLK_AUDIO1 240
+#define TEGRA124_CLK_AUDIO2 241
+#define TEGRA124_CLK_AUDIO3 242
+#define TEGRA124_CLK_AUDIO4 243
+#define TEGRA124_CLK_SPDIF 244
+#define TEGRA124_CLK_CLK_OUT_1 245
+#define TEGRA124_CLK_CLK_OUT_2 246
+#define TEGRA124_CLK_CLK_OUT_3 247
+#define TEGRA124_CLK_BLINK 248
+/* 249 */
+/* 250 */
+/* 251 */
+#define TEGRA124_CLK_XUSB_HOST_SRC 252
+#define TEGRA124_CLK_XUSB_FALCON_SRC 253
+#define TEGRA124_CLK_XUSB_FS_SRC 254
+#define TEGRA124_CLK_XUSB_SS_SRC 255
+
+#define TEGRA124_CLK_XUSB_DEV_SRC 256
+#define TEGRA124_CLK_XUSB_DEV 257
+#define TEGRA124_CLK_XUSB_HS_SRC 258
+#define TEGRA124_CLK_SCLK 259
+#define TEGRA124_CLK_HCLK 260
+#define TEGRA124_CLK_PCLK 261
+/* 262 */
+/* 263 */
+#define TEGRA124_CLK_DFLL_REF 264
+#define TEGRA124_CLK_DFLL_SOC 265
+#define TEGRA124_CLK_VI_SENSOR2 266
+#define TEGRA124_CLK_PLL_P_OUT5 267
+#define TEGRA124_CLK_CML0 268
+#define TEGRA124_CLK_CML1 269
+#define TEGRA124_CLK_PLL_C4 270
+#define TEGRA124_CLK_PLL_DP 271
+#define TEGRA124_CLK_PLL_E_MUX 272
+#define TEGRA124_CLK_PLLD_DSI 273
+/* 274 */
+/* 275 */
+/* 276 */
+/* 277 */
+/* 278 */
+/* 279 */
+/* 280 */
+/* 281 */
+/* 282 */
+/* 283 */
+/* 284 */
+/* 285 */
+/* 286 */
+/* 287 */
+
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA124_CLK_AUDIO0_MUX 300
+#define TEGRA124_CLK_AUDIO1_MUX 301
+#define TEGRA124_CLK_AUDIO2_MUX 302
+#define TEGRA124_CLK_AUDIO3_MUX 303
+#define TEGRA124_CLK_AUDIO4_MUX 304
+#define TEGRA124_CLK_SPDIF_MUX 305
+#define TEGRA124_CLK_CLK_OUT_1_MUX 306
+#define TEGRA124_CLK_CLK_OUT_2_MUX 307
+#define TEGRA124_CLK_CLK_OUT_3_MUX 308
+/* 309 */
+/* 310 */
+#define TEGRA124_CLK_SOR0_LVDS 311
+#define TEGRA124_CLK_XUSB_SS_DIV2 312
+
+#define TEGRA124_CLK_PLL_M_UD 313
+#define TEGRA124_CLK_PLL_C_UD 314
+
+#endif  /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
index af9bc9a3ddbc..2860737f0443 100644
--- a/include/dt-bindings/clock/tegra124-car.h
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -1,346 +1,19 @@
 /*
- * This header provides constants for binding nvidia,tegra124-car.
- *
- * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
- * registers. These IDs often match those in the CAR's RST_DEVICES registers,
- * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
- * this case, those clocks are assigned IDs above 185 in order to highlight
- * this issue. Implementations that interpret these clock IDs as bit values
- * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
- * explicitly handle these special cases.
- *
- * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
- * above.
+ * This header provides Tegra124-specific constants for binding
+ * nvidia,tegra124-car.
  */
 
+#include <dt-bindings/clock/tegra124-car-common.h>
+
 #ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
 #define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
 
-/* 0 */
-/* 1 */
-/* 2 */
-#define TEGRA124_CLK_ISPB 3
-#define TEGRA124_CLK_RTC 4
-#define TEGRA124_CLK_TIMER 5
-#define TEGRA124_CLK_UARTA 6
-/* 7 (register bit affects uartb and vfir) */
-/* 8 */
-#define TEGRA124_CLK_SDMMC2 9
-/* 10 (register bit affects spdif_in and spdif_out) */
-#define TEGRA124_CLK_I2S1 11
-#define TEGRA124_CLK_I2C1 12
-/* 13 */
-#define TEGRA124_CLK_SDMMC1 14
-#define TEGRA124_CLK_SDMMC4 15
-/* 16 */
-#define TEGRA124_CLK_PWM 17
-#define TEGRA124_CLK_I2S2 18
-/* 20 (register bit affects vi and vi_sensor) */
-/* 21 */
-#define TEGRA124_CLK_USBD 22
-#define TEGRA124_CLK_ISP 23
-/* 26 */
-/* 25 */
-#define TEGRA124_CLK_DISP2 26
-#define TEGRA124_CLK_DISP1 27
-#define TEGRA124_CLK_HOST1X 28
-#define TEGRA124_CLK_VCP 29
-#define TEGRA124_CLK_I2S0 30
-/* 31 */
-
-#define TEGRA124_CLK_MC 32
-/* 33 */
-#define TEGRA124_CLK_APBDMA 34
-/* 35 */
-#define TEGRA124_CLK_KBC 36
-/* 37 */
-/* 38 */
-/* 39 (register bit affects fuse and fuse_burn) */
-#define TEGRA124_CLK_KFUSE 40
-#define TEGRA124_CLK_SBC1 41
-#define TEGRA124_CLK_NOR 42
-/* 43 */
-#define TEGRA124_CLK_SBC2 44
-/* 45 */
-#define TEGRA124_CLK_SBC3 46
-#define TEGRA124_CLK_I2C5 47
-#define TEGRA124_CLK_DSIA 48
-/* 49 */
-#define TEGRA124_CLK_MIPI 50
-#define TEGRA124_CLK_HDMI 51
-#define TEGRA124_CLK_CSI 52
-/* 53 */
-#define TEGRA124_CLK_I2C2 54
-#define TEGRA124_CLK_UARTC 55
-#define TEGRA124_CLK_MIPI_CAL 56
-#define TEGRA124_CLK_EMC 57
-#define TEGRA124_CLK_USB2 58
-#define TEGRA124_CLK_USB3 59
-/* 60 */
-#define TEGRA124_CLK_VDE 61
-#define TEGRA124_CLK_BSEA 62
-#define TEGRA124_CLK_BSEV 63
-
-/* 64 */
-#define TEGRA124_CLK_UARTD 65
-/* 66 */
-#define TEGRA124_CLK_I2C3 67
-#define TEGRA124_CLK_SBC4 68
-#define TEGRA124_CLK_SDMMC3 69
-#define TEGRA124_CLK_PCIE 70
-#define TEGRA124_CLK_OWR 71
-#define TEGRA124_CLK_AFI 72
-#define TEGRA124_CLK_CSITE 73
-/* 74 */
-/* 75 */
-#define TEGRA124_CLK_LA 76
-#define TEGRA124_CLK_TRACE 77
-#define TEGRA124_CLK_SOC_THERM 78
-#define TEGRA124_CLK_DTV 79
-/* 80 */
-#define TEGRA124_CLK_I2CSLOW 81
-#define TEGRA124_CLK_DSIB 82
-#define TEGRA124_CLK_TSEC 83
-/* 84 */
-/* 85 */
-/* 86 */
-/* 87 */
-/* 88 */
-#define TEGRA124_CLK_XUSB_HOST 89
-/* 90 */
-#define TEGRA124_CLK_MSENC 91
-#define TEGRA124_CLK_CSUS 92
-/* 93 */
-/* 94 */
-/* 95 (bit affects xusb_dev and xusb_dev_src) */
-
-/* 96 */
-/* 97 */
-/* 98 */
-#define TEGRA124_CLK_MSELECT 99
-#define TEGRA124_CLK_TSENSOR 100
-#define TEGRA124_CLK_I2S3 101
-#define TEGRA124_CLK_I2S4 102
-#define TEGRA124_CLK_I2C4 103
-#define TEGRA124_CLK_SBC5 104
-#define TEGRA124_CLK_SBC6 105
-#define TEGRA124_CLK_D_AUDIO 106
-#define TEGRA124_CLK_APBIF 107
-#define TEGRA124_CLK_DAM0 108
-#define TEGRA124_CLK_DAM1 109
-#define TEGRA124_CLK_DAM2 110
-#define TEGRA124_CLK_HDA2CODEC_2X 111
-/* 112 */
-#define TEGRA124_CLK_AUDIO0_2X 113
-#define TEGRA124_CLK_AUDIO1_2X 114
-#define TEGRA124_CLK_AUDIO2_2X 115
-#define TEGRA124_CLK_AUDIO3_2X 116
-#define TEGRA124_CLK_AUDIO4_2X 117
-#define TEGRA124_CLK_SPDIF_2X 118
-#define TEGRA124_CLK_ACTMON 119
-#define TEGRA124_CLK_EXTERN1 120
-#define TEGRA124_CLK_EXTERN2 121
-#define TEGRA124_CLK_EXTERN3 122
-#define TEGRA124_CLK_SATA_OOB 123
-#define TEGRA124_CLK_SATA 124
-#define TEGRA124_CLK_HDA 125
-/* 126 */
-#define TEGRA124_CLK_SE 127
-
-#define TEGRA124_CLK_HDA2HDMI 128
-#define TEGRA124_CLK_SATA_COLD 129
-/* 130 */
-/* 131 */
-/* 132 */
-/* 133 */
-/* 134 */
-/* 135 */
-/* 136 */
-/* 137 */
-/* 138 */
-/* 139 */
-/* 140 */
-/* 141 */
-/* 142 */
-/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
-/*      xusb_host_src and xusb_ss_src) */
-#define TEGRA124_CLK_CILAB 144
-#define TEGRA124_CLK_CILCD 145
-#define TEGRA124_CLK_CILE 146
-#define TEGRA124_CLK_DSIALP 147
-#define TEGRA124_CLK_DSIBLP 148
-#define TEGRA124_CLK_ENTROPY 149
-#define TEGRA124_CLK_DDS 150
-/* 151 */
-#define TEGRA124_CLK_DP2 152
-#define TEGRA124_CLK_AMX 153
-#define TEGRA124_CLK_ADX 154
-/* 155 (bit affects dfll_ref and dfll_soc) */
-#define TEGRA124_CLK_XUSB_SS 156
-/* 157 */
-/* 158 */
-/* 159 */
-
-/* 160 */
-/* 161 */
-/* 162 */
-/* 163 */
-/* 164 */
-/* 165 */
-#define TEGRA124_CLK_I2C6 166
-/* 167 */
-/* 168 */
-/* 169 */
-/* 170 */
-#define TEGRA124_CLK_VIM2_CLK 171
-/* 172 */
-/* 173 */
-/* 174 */
-/* 175 */
-#define TEGRA124_CLK_HDMI_AUDIO 176
-#define TEGRA124_CLK_CLK72MHZ 177
-#define TEGRA124_CLK_VIC03 178
-/* 179 */
-#define TEGRA124_CLK_ADX1 180
-#define TEGRA124_CLK_DPAUX 181
-#define TEGRA124_CLK_SOR0 182
-/* 183 */
-#define TEGRA124_CLK_GPU 184
-#define TEGRA124_CLK_AMX1 185
-/* 186 */
-/* 187 */
-/* 188 */
-/* 189 */
-/* 190 */
-/* 191 */
-#define TEGRA124_CLK_UARTB 192
-#define TEGRA124_CLK_VFIR 193
-#define TEGRA124_CLK_SPDIF_IN 194
-#define TEGRA124_CLK_SPDIF_OUT 195
-#define TEGRA124_CLK_VI 196
-#define TEGRA124_CLK_VI_SENSOR 197
-#define TEGRA124_CLK_FUSE 198
-#define TEGRA124_CLK_FUSE_BURN 199
-#define TEGRA124_CLK_CLK_32K 200
-#define TEGRA124_CLK_CLK_M 201
-#define TEGRA124_CLK_CLK_M_DIV2 202
-#define TEGRA124_CLK_CLK_M_DIV4 203
-#define TEGRA124_CLK_PLL_REF 204
-#define TEGRA124_CLK_PLL_C 205
-#define TEGRA124_CLK_PLL_C_OUT1 206
-#define TEGRA124_CLK_PLL_C2 207
-#define TEGRA124_CLK_PLL_C3 208
-#define TEGRA124_CLK_PLL_M 209
-#define TEGRA124_CLK_PLL_M_OUT1 210
-#define TEGRA124_CLK_PLL_P 211
-#define TEGRA124_CLK_PLL_P_OUT1 212
-#define TEGRA124_CLK_PLL_P_OUT2 213
-#define TEGRA124_CLK_PLL_P_OUT3 214
-#define TEGRA124_CLK_PLL_P_OUT4 215
-#define TEGRA124_CLK_PLL_A 216
-#define TEGRA124_CLK_PLL_A_OUT0 217
-#define TEGRA124_CLK_PLL_D 218
-#define TEGRA124_CLK_PLL_D_OUT0 219
-#define TEGRA124_CLK_PLL_D2 220
-#define TEGRA124_CLK_PLL_D2_OUT0 221
-#define TEGRA124_CLK_PLL_U 222
-#define TEGRA124_CLK_PLL_U_480M 223
-
-#define TEGRA124_CLK_PLL_U_60M 224
-#define TEGRA124_CLK_PLL_U_48M 225
-#define TEGRA124_CLK_PLL_U_12M 226
-#define TEGRA124_CLK_PLL_X 227
-#define TEGRA124_CLK_PLL_X_OUT0 228
-#define TEGRA124_CLK_PLL_RE_VCO 229
-#define TEGRA124_CLK_PLL_RE_OUT 230
-#define TEGRA124_CLK_PLL_E 231
-#define TEGRA124_CLK_SPDIF_IN_SYNC 232
-#define TEGRA124_CLK_I2S0_SYNC 233
-#define TEGRA124_CLK_I2S1_SYNC 234
-#define TEGRA124_CLK_I2S2_SYNC 235
-#define TEGRA124_CLK_I2S3_SYNC 236
-#define TEGRA124_CLK_I2S4_SYNC 237
-#define TEGRA124_CLK_VIMCLK_SYNC 238
-#define TEGRA124_CLK_AUDIO0 239
-#define TEGRA124_CLK_AUDIO1 240
-#define TEGRA124_CLK_AUDIO2 241
-#define TEGRA124_CLK_AUDIO3 242
-#define TEGRA124_CLK_AUDIO4 243
-#define TEGRA124_CLK_SPDIF 244
-#define TEGRA124_CLK_CLK_OUT_1 245
-#define TEGRA124_CLK_CLK_OUT_2 246
-#define TEGRA124_CLK_CLK_OUT_3 247
-#define TEGRA124_CLK_BLINK 248
-/* 249 */
-/* 250 */
-/* 251 */
-#define TEGRA124_CLK_XUSB_HOST_SRC 252
-#define TEGRA124_CLK_XUSB_FALCON_SRC 253
-#define TEGRA124_CLK_XUSB_FS_SRC 254
-#define TEGRA124_CLK_XUSB_SS_SRC 255
-
-#define TEGRA124_CLK_XUSB_DEV_SRC 256
-#define TEGRA124_CLK_XUSB_DEV 257
-#define TEGRA124_CLK_XUSB_HS_SRC 258
-#define TEGRA124_CLK_SCLK 259
-#define TEGRA124_CLK_HCLK 260
-#define TEGRA124_CLK_PCLK 261
-#define TEGRA124_CLK_CCLK_G 262
-#define TEGRA124_CLK_CCLK_LP 263
-#define TEGRA124_CLK_DFLL_REF 264
-#define TEGRA124_CLK_DFLL_SOC 265
-#define TEGRA124_CLK_VI_SENSOR2 266
-#define TEGRA124_CLK_PLL_P_OUT5 267
-#define TEGRA124_CLK_CML0 268
-#define TEGRA124_CLK_CML1 269
-#define TEGRA124_CLK_PLL_C4 270
-#define TEGRA124_CLK_PLL_DP 271
-#define TEGRA124_CLK_PLL_E_MUX 272
-/* 273 */
-/* 274 */
-/* 275 */
-/* 276 */
-/* 277 */
-/* 278 */
-/* 279 */
-/* 280 */
-/* 281 */
-/* 282 */
-/* 283 */
-/* 284 */
-/* 285 */
-/* 286 */
-/* 287 */
-
-/* 288 */
-/* 289 */
-/* 290 */
-/* 291 */
-/* 292 */
-/* 293 */
-/* 294 */
-/* 295 */
-/* 296 */
-/* 297 */
-/* 298 */
-/* 299 */
-#define TEGRA124_CLK_AUDIO0_MUX 300
-#define TEGRA124_CLK_AUDIO1_MUX 301
-#define TEGRA124_CLK_AUDIO2_MUX 302
-#define TEGRA124_CLK_AUDIO3_MUX 303
-#define TEGRA124_CLK_AUDIO4_MUX 304
-#define TEGRA124_CLK_SPDIF_MUX 305
-#define TEGRA124_CLK_CLK_OUT_1_MUX 306
-#define TEGRA124_CLK_CLK_OUT_2_MUX 307
-#define TEGRA124_CLK_CLK_OUT_3_MUX 308
-#define TEGRA124_CLK_DSIA_MUX 309
-#define TEGRA124_CLK_DSIB_MUX 310
-#define TEGRA124_CLK_SOR0_LVDS 311
-#define TEGRA124_CLK_XUSB_SS_DIV2 312
+#define TEGRA124_CLK_PLL_X              227
+#define TEGRA124_CLK_PLL_X_OUT0         228
 
-#define TEGRA124_CLK_PLL_M_UD 313
-#define TEGRA124_CLK_PLL_C_UD 314
+#define TEGRA124_CLK_CCLK_G             262
+#define TEGRA124_CLK_CCLK_LP            263
 
-#define TEGRA124_CLK_CLK_MAX 315
+#define TEGRA124_CLK_CLK_MAX            315
 
 #endif  /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
diff --git a/include/dt-bindings/mfd/qcom-rpm.h b/include/dt-bindings/mfd/qcom-rpm.h
new file mode 100644
index 000000000000..388a6f3d6165
--- /dev/null
+++ b/include/dt-bindings/mfd/qcom-rpm.h
@@ -0,0 +1,154 @@
+/*
+ * This header provides constants for the Qualcomm RPM bindings.
+ */
+
+#ifndef _DT_BINDINGS_MFD_QCOM_RPM_H
+#define _DT_BINDINGS_MFD_QCOM_RPM_H
+
+/*
+ * Constants use to identify individual resources in the RPM.
+ */
+#define QCOM_RPM_APPS_FABRIC_ARB                1
+#define QCOM_RPM_APPS_FABRIC_CLK                2
+#define QCOM_RPM_APPS_FABRIC_HALT               3
+#define QCOM_RPM_APPS_FABRIC_IOCTL              4
+#define QCOM_RPM_APPS_FABRIC_MODE               5
+#define QCOM_RPM_APPS_L2_CACHE_CTL              6
+#define QCOM_RPM_CFPB_CLK                       7
+#define QCOM_RPM_CXO_BUFFERS                    8
+#define QCOM_RPM_CXO_CLK                        9
+#define QCOM_RPM_DAYTONA_FABRIC_CLK             10
+#define QCOM_RPM_DDR_DMM                        11
+#define QCOM_RPM_EBI1_CLK                       12
+#define QCOM_RPM_HDMI_SWITCH                    13
+#define QCOM_RPM_MMFPB_CLK                      14
+#define QCOM_RPM_MM_FABRIC_ARB                  15
+#define QCOM_RPM_MM_FABRIC_CLK                  16
+#define QCOM_RPM_MM_FABRIC_HALT                 17
+#define QCOM_RPM_MM_FABRIC_IOCTL                18
+#define QCOM_RPM_MM_FABRIC_MODE                 19
+#define QCOM_RPM_PLL_4                          20
+#define QCOM_RPM_PM8058_LDO0                    21
+#define QCOM_RPM_PM8058_LDO1                    22
+#define QCOM_RPM_PM8058_LDO2                    23
+#define QCOM_RPM_PM8058_LDO3                    24
+#define QCOM_RPM_PM8058_LDO4                    25
+#define QCOM_RPM_PM8058_LDO5                    26
+#define QCOM_RPM_PM8058_LDO6                    27
+#define QCOM_RPM_PM8058_LDO7                    28
+#define QCOM_RPM_PM8058_LDO8                    29
+#define QCOM_RPM_PM8058_LDO9                    30
+#define QCOM_RPM_PM8058_LDO10                   31
+#define QCOM_RPM_PM8058_LDO11                   32
+#define QCOM_RPM_PM8058_LDO12                   33
+#define QCOM_RPM_PM8058_LDO13                   34
+#define QCOM_RPM_PM8058_LDO14                   35
+#define QCOM_RPM_PM8058_LDO15                   36
+#define QCOM_RPM_PM8058_LDO16                   37
+#define QCOM_RPM_PM8058_LDO17                   38
+#define QCOM_RPM_PM8058_LDO18                   39
+#define QCOM_RPM_PM8058_LDO19                   40
+#define QCOM_RPM_PM8058_LDO20                   41
+#define QCOM_RPM_PM8058_LDO21                   42
+#define QCOM_RPM_PM8058_LDO22                   43
+#define QCOM_RPM_PM8058_LDO23                   44
+#define QCOM_RPM_PM8058_LDO24                   45
+#define QCOM_RPM_PM8058_LDO25                   46
+#define QCOM_RPM_PM8058_LVS0                    47
+#define QCOM_RPM_PM8058_LVS1                    48
+#define QCOM_RPM_PM8058_NCP                     49
+#define QCOM_RPM_PM8058_SMPS0                   50
+#define QCOM_RPM_PM8058_SMPS1                   51
+#define QCOM_RPM_PM8058_SMPS2                   52
+#define QCOM_RPM_PM8058_SMPS3                   53
+#define QCOM_RPM_PM8058_SMPS4                   54
+#define QCOM_RPM_PM8821_LDO1                    55
+#define QCOM_RPM_PM8821_SMPS1                   56
+#define QCOM_RPM_PM8821_SMPS2                   57
+#define QCOM_RPM_PM8901_LDO0                    58
+#define QCOM_RPM_PM8901_LDO1                    59
+#define QCOM_RPM_PM8901_LDO2                    60
+#define QCOM_RPM_PM8901_LDO3                    61
+#define QCOM_RPM_PM8901_LDO4                    62
+#define QCOM_RPM_PM8901_LDO5                    63
+#define QCOM_RPM_PM8901_LDO6                    64
+#define QCOM_RPM_PM8901_LVS0                    65
+#define QCOM_RPM_PM8901_LVS1                    66
+#define QCOM_RPM_PM8901_LVS2                    67
+#define QCOM_RPM_PM8901_LVS3                    68
+#define QCOM_RPM_PM8901_MVS                     69
+#define QCOM_RPM_PM8901_SMPS0                   70
+#define QCOM_RPM_PM8901_SMPS1                   71
+#define QCOM_RPM_PM8901_SMPS2                   72
+#define QCOM_RPM_PM8901_SMPS3                   73
+#define QCOM_RPM_PM8901_SMPS4                   74
+#define QCOM_RPM_PM8921_CLK1                    75
+#define QCOM_RPM_PM8921_CLK2                    76
+#define QCOM_RPM_PM8921_LDO1                    77
+#define QCOM_RPM_PM8921_LDO2                    78
+#define QCOM_RPM_PM8921_LDO3                    79
+#define QCOM_RPM_PM8921_LDO4                    80
+#define QCOM_RPM_PM8921_LDO5                    81
+#define QCOM_RPM_PM8921_LDO6                    82
+#define QCOM_RPM_PM8921_LDO7                    83
+#define QCOM_RPM_PM8921_LDO8                    84
+#define QCOM_RPM_PM8921_LDO9                    85
+#define QCOM_RPM_PM8921_LDO10                   86
+#define QCOM_RPM_PM8921_LDO11                   87
+#define QCOM_RPM_PM8921_LDO12                   88
+#define QCOM_RPM_PM8921_LDO13                   89
+#define QCOM_RPM_PM8921_LDO14                   90
+#define QCOM_RPM_PM8921_LDO15                   91
+#define QCOM_RPM_PM8921_LDO16                   92
+#define QCOM_RPM_PM8921_LDO17                   93
+#define QCOM_RPM_PM8921_LDO18                   94
+#define QCOM_RPM_PM8921_LDO19                   95
+#define QCOM_RPM_PM8921_LDO20                   96
+#define QCOM_RPM_PM8921_LDO21                   97
+#define QCOM_RPM_PM8921_LDO22                   98
+#define QCOM_RPM_PM8921_LDO23                   99
+#define QCOM_RPM_PM8921_LDO24                   100
+#define QCOM_RPM_PM8921_LDO25                   101
+#define QCOM_RPM_PM8921_LDO26                   102
+#define QCOM_RPM_PM8921_LDO27                   103
+#define QCOM_RPM_PM8921_LDO28                   104
+#define QCOM_RPM_PM8921_LDO29                   105
+#define QCOM_RPM_PM8921_LVS1                    106
+#define QCOM_RPM_PM8921_LVS2                    107
+#define QCOM_RPM_PM8921_LVS3                    108
+#define QCOM_RPM_PM8921_LVS4                    109
+#define QCOM_RPM_PM8921_LVS5                    110
+#define QCOM_RPM_PM8921_LVS6                    111
+#define QCOM_RPM_PM8921_LVS7                    112
+#define QCOM_RPM_PM8921_MVS                     113
+#define QCOM_RPM_PM8921_NCP                     114
+#define QCOM_RPM_PM8921_SMPS1                   115
+#define QCOM_RPM_PM8921_SMPS2                   116
+#define QCOM_RPM_PM8921_SMPS3                   117
+#define QCOM_RPM_PM8921_SMPS4                   118
+#define QCOM_RPM_PM8921_SMPS5                   119
+#define QCOM_RPM_PM8921_SMPS6                   120
+#define QCOM_RPM_PM8921_SMPS7                   121
+#define QCOM_RPM_PM8921_SMPS8                   122
+#define QCOM_RPM_PXO_CLK                        123
+#define QCOM_RPM_QDSS_CLK                       124
+#define QCOM_RPM_SFPB_CLK                       125
+#define QCOM_RPM_SMI_CLK                        126
+#define QCOM_RPM_SYS_FABRIC_ARB                 127
+#define QCOM_RPM_SYS_FABRIC_CLK                 128
+#define QCOM_RPM_SYS_FABRIC_HALT                129
+#define QCOM_RPM_SYS_FABRIC_IOCTL               130
+#define QCOM_RPM_SYS_FABRIC_MODE                131
+#define QCOM_RPM_USB_OTG_SWITCH                 132
+#define QCOM_RPM_VDDMIN_GPIO                    133
+
+/*
+ * Constants used to select force mode for regulators.
+ */
+#define QCOM_RPM_FORCE_MODE_NONE                0
+#define QCOM_RPM_FORCE_MODE_LPM                 1
+#define QCOM_RPM_FORCE_MODE_HPM                 2
+#define QCOM_RPM_FORCE_MODE_AUTO                3
+#define QCOM_RPM_FORCE_MODE_BYPASS              4
+
+#endif
diff --git a/include/linux/clk/sunxi.h b/include/dt-bindings/thermal/thermal_exynos.h
index aed28c4451d9..0646500bca69 100644
--- a/include/linux/clk/sunxi.h
+++ b/include/dt-bindings/thermal/thermal_exynos.h
@@ -1,5 +1,8 @@
 /*
- * Copyright 2013 - Hans de Goede <hdegoede@redhat.com>
+ * thermal_exynos.h - Samsung EXYNOS TMU device tree definitions
+ *
+ *  Copyright (C) 2014 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -10,13 +13,16 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
+ *
  */
 
-#ifndef __LINUX_CLK_SUNXI_H_
-#define __LINUX_CLK_SUNXI_H_
-
-#include <linux/clk.h>
+#ifndef _EXYNOS_THERMAL_TMU_DT_H
+#define _EXYNOS_THERMAL_TMU_DT_H
 
-void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output);
+#define TYPE_ONE_POINT_TRIMMING 0
+#define TYPE_ONE_POINT_TRIMMING_25 1
+#define TYPE_ONE_POINT_TRIMMING_85 2
+#define TYPE_TWO_POINT_TRIMMING 3
+#define TYPE_NONE 4
 
-#endif
+#endif /* _EXYNOS_THERMAL_TMU_DT_H */
diff --git a/include/linux/bcm47xx_wdt.h b/include/linux/bcm47xx_wdt.h
index b708786d4cbf..5582c211f594 100644
--- a/include/linux/bcm47xx_wdt.h
+++ b/include/linux/bcm47xx_wdt.h
@@ -16,6 +16,7 @@ struct bcm47xx_wdt {
 
         struct watchdog_device wdd;
         struct notifier_block notifier;
+        struct notifier_block restart_handler;
 
         struct timer_list soft_timer;
         atomic_t soft_ticks;
diff --git a/include/linux/ceph/ceph_fs.h b/include/linux/ceph/ceph_fs.h
index c0dadaac26e3..31eb03d0c766 100644
--- a/include/linux/ceph/ceph_fs.h
+++ b/include/linux/ceph/ceph_fs.h
@@ -158,17 +158,6 @@ enum {
 };
 
 
-/* pool operations */
-enum {
-  POOL_OP_CREATE                        = 0x01,
-  POOL_OP_DELETE                        = 0x02,
-  POOL_OP_AUID_CHANGE                   = 0x03,
-  POOL_OP_CREATE_SNAP                   = 0x11,
-  POOL_OP_DELETE_SNAP                   = 0x12,
-  POOL_OP_CREATE_UNMANAGED_SNAP         = 0x21,
-  POOL_OP_DELETE_UNMANAGED_SNAP         = 0x22,
-};
-
 struct ceph_mon_request_header {
         __le64 have_version;
         __le16 session_mon;
@@ -191,31 +180,6 @@ struct ceph_mon_statfs_reply {
         struct ceph_statfs st;
 } __attribute__ ((packed));
 
-const char *ceph_pool_op_name(int op);
-
-struct ceph_mon_poolop {
-        struct ceph_mon_request_header monhdr;
-        struct ceph_fsid fsid;
-        __le32 pool;
-        __le32 op;
-        __le64 auid;
-        __le64 snapid;
-        __le32 name_len;
-} __attribute__ ((packed));
-
-struct ceph_mon_poolop_reply {
-        struct ceph_mon_request_header monhdr;
-        struct ceph_fsid fsid;
-        __le32 reply_code;
-        __le32 epoch;
-        char has_data;
-        char data[0];
-} __attribute__ ((packed));
-
-struct ceph_mon_unmanaged_snap {
-        __le64 snapid;
-} __attribute__ ((packed));
-
 struct ceph_osd_getmap {
         struct ceph_mon_request_header monhdr;
         struct ceph_fsid fsid;
@@ -307,6 +271,7 @@ enum {
         CEPH_SESSION_RECALL_STATE,
         CEPH_SESSION_FLUSHMSG,
         CEPH_SESSION_FLUSHMSG_ACK,
+        CEPH_SESSION_FORCE_RO,
 };
 
 extern const char *ceph_session_op_name(int op);
diff --git a/include/linux/ceph/libceph.h b/include/linux/ceph/libceph.h
index 8b11a79ca1cb..16fff9608848 100644
--- a/include/linux/ceph/libceph.h
+++ b/include/linux/ceph/libceph.h
@@ -30,8 +30,9 @@
 #define CEPH_OPT_MYIP             (1<<2) /* specified my ip */
 #define CEPH_OPT_NOCRC            (1<<3) /* no data crc on writes */
 #define CEPH_OPT_NOMSGAUTH        (1<<4) /* not require cephx message signature */
+#define CEPH_OPT_TCP_NODELAY      (1<<5) /* TCP_NODELAY on TCP sockets */
 
-#define CEPH_OPT_DEFAULT   (0)
+#define CEPH_OPT_DEFAULT   (CEPH_OPT_TCP_NODELAY)
 
 #define ceph_set_opt(client, opt) \
         (client)->options->flags |= CEPH_OPT_##opt;
diff --git a/include/linux/ceph/messenger.h b/include/linux/ceph/messenger.h
index d9d396c16503..e15499422fdc 100644
--- a/include/linux/ceph/messenger.h
+++ b/include/linux/ceph/messenger.h
@@ -57,6 +57,7 @@ struct ceph_messenger {
 
         atomic_t stopping;
         bool nocrc;
+        bool tcp_nodelay;
 
         /*
          * the global_seq counts connections i (attempt to) initiate
@@ -264,7 +265,8 @@ extern void ceph_messenger_init(struct ceph_messenger *msgr,
                         struct ceph_entity_addr *myaddr,
                         u64 supported_features,
                         u64 required_features,
-                        bool nocrc);
+                        bool nocrc,
+                        bool tcp_nodelay);
 
 extern void ceph_con_init(struct ceph_connection *con, void *private,
                         const struct ceph_connection_operations *ops,
diff --git a/include/linux/ceph/mon_client.h b/include/linux/ceph/mon_client.h
index deb47e45ac7c..81810dc21f06 100644
--- a/include/linux/ceph/mon_client.h
+++ b/include/linux/ceph/mon_client.h
@@ -40,7 +40,7 @@ struct ceph_mon_request {
 };
 
 /*
- * ceph_mon_generic_request is being used for the statfs, poolop and
+ * ceph_mon_generic_request is being used for the statfs and
  * mon_get_version requests which are being done a bit differently
  * because we need to get data back to the caller
  */
@@ -50,7 +50,6 @@ struct ceph_mon_generic_request {
         struct rb_node node;
         int result;
         void *buf;
-        int buf_len;
         struct completion completion;
         struct ceph_msg *request;  /* original request */
         struct ceph_msg *reply;    /* and reply */
@@ -117,10 +116,4 @@ extern int ceph_monc_open_session(struct ceph_mon_client *monc);
 
 extern int ceph_monc_validate_auth(struct ceph_mon_client *monc);
 
-extern int ceph_monc_create_snapid(struct ceph_mon_client *monc,
-                                   u32 pool, u64 *snapid);
-
-extern int ceph_monc_delete_snapid(struct ceph_mon_client *monc,
-                                   u32 pool, u64 snapid);
-
 #endif
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
deleted file mode 100644
index 0ca5f6046920..000000000000
--- a/include/linux/clk-private.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- *  linux/include/linux/clk-private.h
- *
- *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
- *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __LINUX_CLK_PRIVATE_H
-#define __LINUX_CLK_PRIVATE_H
-
-#include <linux/clk-provider.h>
-#include <linux/kref.h>
-#include <linux/list.h>
-
-/*
- * WARNING: Do not include clk-private.h from any file that implements struct
- * clk_ops.  Doing so is a layering violation!
- *
- * This header exists only to allow for statically initialized clock data.  Any
- * static clock data must be defined in a separate file from the logic that
- * implements the clock operations for that same data.
- */
-
-#ifdef CONFIG_COMMON_CLK
-
-struct module;
-
-struct clk {
-        const char              *name;
-        const struct clk_ops    *ops;
-        struct clk_hw           *hw;
-        struct module           *owner;
-        struct clk              *parent;
-        const char              **parent_names;
-        struct clk              **parents;
-        u8                      num_parents;
-        u8                      new_parent_index;
-        unsigned long           rate;
-        unsigned long           new_rate;
-        struct clk              *new_parent;
-        struct clk              *new_child;
-        unsigned long           flags;
-        unsigned int            enable_count;
-        unsigned int            prepare_count;
-        unsigned long           accuracy;
-        int                     phase;
-        struct hlist_head       children;
-        struct hlist_node       child_node;
-        struct hlist_node       debug_node;
-        unsigned int            notifier_count;
-#ifdef CONFIG_DEBUG_FS
-        struct dentry           *dentry;
-#endif
-        struct kref             ref;
-};
-
-/*
- * DOC: Basic clock implementations common to many platforms
- *
- * Each basic clock hardware type is comprised of a structure describing the
- * clock hardware, implementations of the relevant callbacks in struct clk_ops,
- * unique flags for that hardware type, a registration function and an
- * alternative macro for static initialization
- */
-
-#define DEFINE_CLK(_name, _ops, _flags, _parent_names,          \
-                _parents)                                       \
-        static struct clk _name = {                             \
-                .name = #_name,                                 \
-                .ops = &_ops,                                   \
-                .hw = &_name##_hw.hw,                           \
-                .parent_names = _parent_names,                  \
-                .num_parents = ARRAY_SIZE(_parent_names),       \
-                .parents = _parents,                            \
-                .flags = _flags | CLK_IS_BASIC,                 \
-        }
-
-#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate,             \
-                                _fixed_rate_flags)              \
-        static struct clk _name;                                \
-        static const char *_name##_parent_names[] = {};         \
-        static struct clk_fixed_rate _name##_hw = {             \
-                .hw = {                                         \
-                        .clk = &_name,                          \
-                },                                              \
-                .fixed_rate = _rate,                            \
-                .flags = _fixed_rate_flags,                     \
-        };                                                      \
-        DEFINE_CLK(_name, clk_fixed_rate_ops, _flags,           \
-                        _name##_parent_names, NULL);
-
-#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr,       \
-                                _flags, _reg, _bit_idx,         \
-                                _gate_flags, _lock)             \
-        static struct clk _name;                                \
-        static const char *_name##_parent_names[] = {           \
-                _parent_name,                                   \
-        };                                                      \
-        static struct clk *_name##_parents[] = {                \
-                _parent_ptr,                                    \
-        };                                                      \
-        static struct clk_gate _name##_hw = {                   \
-                .hw = {                                         \
-                        .clk = &_name,                          \
-                },                                              \
-                .reg = _reg,                                    \
-                .bit_idx = _bit_idx,                            \
-                .flags = _gate_flags,                           \
-                .lock = _lock,                                  \
-        };                                                      \
-        DEFINE_CLK(_name, clk_gate_ops, _flags,                 \
-                        _name##_parent_names, _name##_parents);
-
-#define _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,   \
-                                _flags, _reg, _shift, _width,   \
-                                _divider_flags, _table, _lock)  \
-        static struct clk _name;                                \
-        static const char *_name##_parent_names[] = {           \
-                _parent_name,                                   \
-        };                                                      \
-        static struct clk *_name##_parents[] = {                \
-                _parent_ptr,                                    \
-        };                                                      \
-        static struct clk_divider _name##_hw = {                \
-                .hw = {                                         \
-                        .clk = &_name,                          \
-                },                                              \
-                .reg = _reg,                                    \
-                .shift = _shift,                                \
-                .width = _width,                                \
-                .flags = _divider_flags,                        \
-                .table = _table,                                \
-                .lock = _lock,                                  \
-        };                                                      \
-        DEFINE_CLK(_name, clk_divider_ops, _flags,              \
-                        _name##_parent_names, _name##_parents);
-
-#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,    \
-                                _flags, _reg, _shift, _width,   \
-                                _divider_flags, _lock)          \
-        _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,   \
-                                _flags, _reg, _shift, _width,   \
-                                _divider_flags, NULL, _lock)
-
-#define DEFINE_CLK_DIVIDER_TABLE(_name, _parent_name,           \
-                                _parent_ptr, _flags, _reg,      \
-                                _shift, _width, _divider_flags, \
-                                _table, _lock)                  \
-        _DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr,   \
-                                _flags, _reg, _shift, _width,   \
-                                _divider_flags, _table, _lock)  \
-
-#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags,  \
-                                _reg, _shift, _width,           \
-                                _mux_flags, _lock)              \
-        static struct clk _name;                                \
-        static struct clk_mux _name##_hw = {                    \
-                .hw = {                                         \
-                        .clk = &_name,                          \
-                },                                              \
-                .reg = _reg,                                    \
-                .shift = _shift,                                \
-                .mask = BIT(_width) - 1,                        \
-                .flags = _mux_flags,                            \
-                .lock = _lock,                                  \
-        };                                                      \
-        DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names,   \
-                        _parents);
-
-#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name,            \
-                                _parent_ptr, _flags,            \
-                                _mult, _div)                    \
-        static struct clk _name;                                \
-        static const char *_name##_parent_names[] = {           \
-                _parent_name,                                   \
-        };                                                      \
-        static struct clk *_name##_parents[] = {                \
-                _parent_ptr,                                    \
-        };                                                      \
-        static struct clk_fixed_factor _name##_hw = {           \
-                .hw = {                                         \
-                        .clk = &_name,                          \
-                },                                              \
-                .mult = _mult,                                  \
-                .div = _div,                                    \
-        };                                                      \
-        DEFINE_CLK(_name, clk_fixed_factor_ops, _flags,         \
-                        _name##_parent_names, _name##_parents);
-
-/**
- * __clk_init - initialize the data structures in a struct clk
- * @dev:        device initializing this clk, placeholder for now
- * @clk:        clk being initialized
- *
- * Initializes the lists in struct clk, queries the hardware for the
- * parent and rate and sets them both.
- *
- * Any struct clk passed into __clk_init must have the following members
- * populated:
- *      .name
- *      .ops
- *      .hw
- *      .parent_names
- *      .num_parents
- *      .flags
- *
- * It is not necessary to call clk_register if __clk_init is used directly with
- * statically initialized clock data.
- *
- * Returns 0 on success, otherwise an error code.
- */
-int __clk_init(struct device *dev, struct clk *clk);
-
-struct clk *__clk_register(struct device *dev, struct clk_hw *hw);
-
-#endif /* CONFIG_COMMON_CLK */
-#endif /* CLK_PRIVATE_H */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index d936409520f8..5591ea71a8d1 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -33,6 +33,7 @@
 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
 
 struct clk_hw;
+struct clk_core;
 struct dentry;
 
 /**
@@ -174,9 +175,12 @@ struct clk_ops {
                                         unsigned long parent_rate);
         long            (*round_rate)(struct clk_hw *hw, unsigned long rate,
                                         unsigned long *parent_rate);
-        long            (*determine_rate)(struct clk_hw *hw, unsigned long rate,
-                                        unsigned long *best_parent_rate,
-                                        struct clk_hw **best_parent_hw);
+        long            (*determine_rate)(struct clk_hw *hw,
+                                          unsigned long rate,
+                                          unsigned long min_rate,
+                                          unsigned long max_rate,
+                                          unsigned long *best_parent_rate,
+                                          struct clk_hw **best_parent_hw);
         int             (*set_parent)(struct clk_hw *hw, u8 index);
         u8              (*get_parent)(struct clk_hw *hw);
         int             (*set_rate)(struct clk_hw *hw, unsigned long rate,
@@ -216,13 +220,17 @@ struct clk_init_data {
  * clk_foo and then referenced by the struct clk instance that uses struct
  * clk_foo's clk_ops
  *
- * @clk: pointer to the struct clk instance that points back to this struct
- * clk_hw instance
+ * @core: pointer to the struct clk_core instance that points back to this
+ * struct clk_hw instance
+ *
+ * @clk: pointer to the per-user struct clk instance that can be used to call
+ * into the clk API
  *
  * @init: pointer to struct clk_init_data that contains the init data shared
  * with the common clock framework.
  */
 struct clk_hw {
+        struct clk_core *core;
         struct clk *clk;
         const struct clk_init_data *init;
 };
@@ -294,6 +302,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
                 const char *parent_name, unsigned long flags,
                 void __iomem *reg, u8 bit_idx,
                 u8 clk_gate_flags, spinlock_t *lock);
+void clk_unregister_gate(struct clk *clk);
 
 struct clk_div_table {
         unsigned int    val;
@@ -352,6 +361,17 @@ struct clk_divider {
 #define CLK_DIVIDER_READ_ONLY           BIT(5)
 
 extern const struct clk_ops clk_divider_ops;
+
+unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
+                unsigned int val, const struct clk_div_table *table,
+                unsigned long flags);
+long divider_round_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long *prate, const struct clk_div_table *table,
+                u8 width, unsigned long flags);
+int divider_get_val(unsigned long rate, unsigned long parent_rate,
+                const struct clk_div_table *table, u8 width,
+                unsigned long flags);
+
 struct clk *clk_register_divider(struct device *dev, const char *name,
                 const char *parent_name, unsigned long flags,
                 void __iomem *reg, u8 shift, u8 width,
@@ -361,6 +381,7 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
                 void __iomem *reg, u8 shift, u8 width,
                 u8 clk_divider_flags, const struct clk_div_table *table,
                 spinlock_t *lock);
+void clk_unregister_divider(struct clk *clk);
 
 /**
  * struct clk_mux - multiplexer clock
@@ -382,6 +403,8 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
  *      register, and mask of mux bits are in higher 16-bit of this register.
  *      While setting the mux bits, higher 16-bit should also be updated to
  *      indicate changing mux bits.
+ * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
+ *      frequency.
  */
 struct clk_mux {
         struct clk_hw   hw;
@@ -396,7 +419,8 @@ struct clk_mux {
 #define CLK_MUX_INDEX_ONE               BIT(0)
 #define CLK_MUX_INDEX_BIT               BIT(1)
 #define CLK_MUX_HIWORD_MASK             BIT(2)
-#define CLK_MUX_READ_ONLY       BIT(3) /* mux setting cannot be changed */
+#define CLK_MUX_READ_ONLY               BIT(3) /* mux can't be changed */
+#define CLK_MUX_ROUND_CLOSEST           BIT(4)
 
 extern const struct clk_ops clk_mux_ops;
 extern const struct clk_ops clk_mux_ro_ops;
@@ -411,6 +435,8 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name,
                 void __iomem *reg, u8 shift, u32 mask,
                 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
 
+void clk_unregister_mux(struct clk *clk);
+
 void of_fixed_factor_clk_setup(struct device_node *node);
 
 /**
@@ -550,15 +576,29 @@ bool __clk_is_prepared(struct clk *clk);
 bool __clk_is_enabled(struct clk *clk);
 struct clk *__clk_lookup(const char *name);
 long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
+                              unsigned long min_rate,
+                              unsigned long max_rate,
                               unsigned long *best_parent_rate,
                               struct clk_hw **best_parent_p);
+unsigned long __clk_determine_rate(struct clk_hw *core,
+                                   unsigned long rate,
+                                   unsigned long min_rate,
+                                   unsigned long max_rate);
+long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate,
+                              unsigned long min_rate,
+                              unsigned long max_rate,
+                              unsigned long *best_parent_rate,
+                              struct clk_hw **best_parent_p);
+
+static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
+{
+        dst->clk = src->clk;
+        dst->core = src->core;
+}
 
 /*
  * FIXME clock api without lock protection
  */
-int __clk_prepare(struct clk *clk);
-void __clk_unprepare(struct clk *clk);
-void __clk_reparent(struct clk *clk, struct clk *new_parent);
 unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
 
 struct of_device_id;
diff --git a/include/linux/clk.h b/include/linux/clk.h
index c7f258a81761..8381bbfbc308 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -302,6 +302,46 @@ long clk_round_rate(struct clk *clk, unsigned long rate);
 int clk_set_rate(struct clk *clk, unsigned long rate);
 
 /**
+ * clk_has_parent - check if a clock is a possible parent for another
+ * @clk: clock source
+ * @parent: parent clock source
+ *
+ * This function can be used in drivers that need to check that a clock can be
+ * the parent of another without actually changing the parent.
+ *
+ * Returns true if @parent is a possible parent for @clk, false otherwise.
+ */
+bool clk_has_parent(struct clk *clk, struct clk *parent);
+
+/**
+ * clk_set_rate_range - set a rate range for a clock source
+ * @clk: clock source
+ * @min: desired minimum clock rate in Hz, inclusive
+ * @max: desired maximum clock rate in Hz, inclusive
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max);
+
+/**
+ * clk_set_min_rate - set a minimum clock rate for a clock source
+ * @clk: clock source
+ * @rate: desired minimum clock rate in Hz, inclusive
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_min_rate(struct clk *clk, unsigned long rate);
+
+/**
+ * clk_set_max_rate - set a maximum clock rate for a clock source
+ * @clk: clock source
+ * @rate: desired maximum clock rate in Hz, inclusive
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_max_rate(struct clk *clk, unsigned long rate);
+
+/**
  * clk_set_parent - set the parent clock source for this clock
  * @clk: clock source
  * @parent: parent clock source
@@ -374,6 +414,11 @@ static inline long clk_round_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
+static inline bool clk_has_parent(struct clk *clk, struct clk *parent)
+{
+        return true;
+}
+
 static inline int clk_set_parent(struct clk *clk, struct clk *parent)
 {
         return 0;
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 3ca9fca827a2..19c4208f4752 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -120,6 +120,4 @@ static inline void tegra_cpu_clock_resume(void)
 }
 #endif
 
-void tegra_clocks_apply_init_table(void);
-
 #endif /* __LINUX_CLK_TEGRA_H_ */
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 55ef529a0dbf..67844003493d 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -15,6 +15,7 @@
 #ifndef __LINUX_CLK_TI_H__
 #define __LINUX_CLK_TI_H__
 
+#include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 
 /**
@@ -217,6 +218,13 @@ struct ti_dt_clk {
 /* Maximum number of clock memmaps */
 #define CLK_MAX_MEMMAPS                 4
 
+/* Static memmap indices */
+enum {
+        TI_CLKM_CM = 0,
+        TI_CLKM_PRM,
+        TI_CLKM_SCRM,
+};
+
 typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
 
 /**
@@ -263,6 +271,8 @@ int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
                                            u8 index);
 long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
                                        unsigned long rate,
+                                       unsigned long min_rate,
+                                       unsigned long max_rate,
                                        unsigned long *best_parent_rate,
                                        struct clk_hw **best_parent_clk);
 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
@@ -272,6 +282,8 @@ long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
                                     unsigned long *parent_rate);
 long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
                                         unsigned long rate,
+                                        unsigned long min_rate,
+                                        unsigned long max_rate,
                                         unsigned long *best_parent_rate,
                                         struct clk_hw **best_parent_clk);
 u8 omap2_init_dpll_parent(struct clk_hw *hw);
@@ -348,4 +360,17 @@ extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
 
+#ifdef CONFIG_ATAGS
+int omap3430_clk_legacy_init(void);
+int omap3430es1_clk_legacy_init(void);
+int omap36xx_clk_legacy_init(void);
+int am35xx_clk_legacy_init(void);
+#else
+static inline int omap3430_clk_legacy_init(void) { return -ENXIO; }
+static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; }
+static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; }
+static inline int am35xx_clk_legacy_init(void) { return -ENXIO; }
+#endif
+
+
 #endif
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index d1ec10a940ff..1b45e4a0519b 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -202,7 +202,7 @@ static __always_inline void data_access_exceeds_word_size(void)
 {
 }
 
-static __always_inline void __read_once_size(volatile void *p, void *res, int size)
+static __always_inline void __read_once_size(const volatile void *p, void *res, int size)
 {
         switch (size) {
         case 1: *(__u8 *)res = *(volatile __u8 *)p; break;
@@ -259,10 +259,10 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s
  */
 
 #define READ_ONCE(x) \
-        ({ typeof(x) __val; __read_once_size(&x, &__val, sizeof(__val)); __val; })
+        ({ union { typeof(x) __val; char __c[1]; } __u; __read_once_size(&(x), __u.__c, sizeof(x)); __u.__val; })
 
 #define WRITE_ONCE(x, val) \
-        ({ typeof(x) __val; __val = val; __write_once_size(&x, &__val, sizeof(__val)); __val; })
+        ({ typeof(x) __val = (val); __write_once_size(&(x), &__val, sizeof(__val)); __val; })
 
 #endif /* __KERNEL__ */
 
diff --git a/include/linux/dcache.h b/include/linux/dcache.h
index 92c08cf7670e..d8358799c594 100644
--- a/include/linux/dcache.h
+++ b/include/linux/dcache.h
@@ -215,13 +215,16 @@ struct dentry_operations {
 #define DCACHE_LRU_LIST                 0x00080000
 
 #define DCACHE_ENTRY_TYPE               0x00700000
-#define DCACHE_MISS_TYPE                0x00000000 /* Negative dentry */
-#define DCACHE_DIRECTORY_TYPE           0x00100000 /* Normal directory */
-#define DCACHE_AUTODIR_TYPE             0x00200000 /* Lookupless directory (presumed automount) */
-#define DCACHE_SYMLINK_TYPE             0x00300000 /* Symlink */
-#define DCACHE_FILE_TYPE                0x00400000 /* Other file type */
+#define DCACHE_MISS_TYPE                0x00000000 /* Negative dentry (maybe fallthru to nowhere) */
+#define DCACHE_WHITEOUT_TYPE            0x00100000 /* Whiteout dentry (stop pathwalk) */
+#define DCACHE_DIRECTORY_TYPE           0x00200000 /* Normal directory */
+#define DCACHE_AUTODIR_TYPE             0x00300000 /* Lookupless directory (presumed automount) */
+#define DCACHE_REGULAR_TYPE             0x00400000 /* Regular file type (or fallthru to such) */
+#define DCACHE_SPECIAL_TYPE             0x00500000 /* Other file type (or fallthru to such) */
+#define DCACHE_SYMLINK_TYPE             0x00600000 /* Symlink (or fallthru to such) */
 
 #define DCACHE_MAY_FREE                 0x00800000
+#define DCACHE_FALLTHRU                 0x01000000 /* Fall through to lower layer */
 
 extern seqlock_t rename_lock;
 
@@ -423,6 +426,16 @@ static inline unsigned __d_entry_type(const struct dentry *dentry)
         return dentry->d_flags & DCACHE_ENTRY_TYPE;
 }
 
+static inline bool d_is_miss(const struct dentry *dentry)
+{
+        return __d_entry_type(dentry) == DCACHE_MISS_TYPE;
+}
+
+static inline bool d_is_whiteout(const struct dentry *dentry)
+{
+        return __d_entry_type(dentry) == DCACHE_WHITEOUT_TYPE;
+}
+
 static inline bool d_can_lookup(const struct dentry *dentry)
 {
         return __d_entry_type(dentry) == DCACHE_DIRECTORY_TYPE;
@@ -443,14 +456,25 @@ static inline bool d_is_symlink(const struct dentry *dentry)
         return __d_entry_type(dentry) == DCACHE_SYMLINK_TYPE;
 }
 
+static inline bool d_is_reg(const struct dentry *dentry)
+{
+        return __d_entry_type(dentry) == DCACHE_REGULAR_TYPE;
+}
+
+static inline bool d_is_special(const struct dentry *dentry)
+{
+        return __d_entry_type(dentry) == DCACHE_SPECIAL_TYPE;
+}
+
 static inline bool d_is_file(const struct dentry *dentry)
 {
-        return __d_entry_type(dentry) == DCACHE_FILE_TYPE;
+        return d_is_reg(dentry) || d_is_special(dentry);
 }
 
 static inline bool d_is_negative(const struct dentry *dentry)
 {
-        return __d_entry_type(dentry) == DCACHE_MISS_TYPE;
+        // TODO: check d_is_whiteout(dentry) also.
+        return d_is_miss(dentry);
 }
 
 static inline bool d_is_positive(const struct dentry *dentry)
@@ -458,10 +482,75 @@ static inline bool d_is_positive(const struct dentry *dentry)
         return !d_is_negative(dentry);
 }
 
+extern void d_set_fallthru(struct dentry *dentry);
+
+static inline bool d_is_fallthru(const struct dentry *dentry)
+{
+        return dentry->d_flags & DCACHE_FALLTHRU;
+}
+
+
 extern int sysctl_vfs_cache_pressure;
 
 static inline unsigned long vfs_pressure_ratio(unsigned long val)
 {
         return mult_frac(val, sysctl_vfs_cache_pressure, 100);
 }
+
+/**
+ * d_inode - Get the actual inode of this dentry
+ * @dentry: The dentry to query
+ *
+ * This is the helper normal filesystems should use to get at their own inodes
+ * in their own dentries and ignore the layering superimposed upon them.
+ */
+static inline struct inode *d_inode(const struct dentry *dentry)
+{
+        return dentry->d_inode;
+}
+
+/**
+ * d_inode_rcu - Get the actual inode of this dentry with ACCESS_ONCE()
+ * @dentry: The dentry to query
+ *
+ * This is the helper normal filesystems should use to get at their own inodes
+ * in their own dentries and ignore the layering superimposed upon them.
+ */
+static inline struct inode *d_inode_rcu(const struct dentry *dentry)
+{
+        return ACCESS_ONCE(dentry->d_inode);
+}
+
+/**
+ * d_backing_inode - Get upper or lower inode we should be using
+ * @upper: The upper layer
+ *
+ * This is the helper that should be used to get at the inode that will be used
+ * if this dentry were to be opened as a file.  The inode may be on the upper
+ * dentry or it may be on a lower dentry pinned by the upper.
+ *
+ * Normal filesystems should not use this to access their own inodes.
+ */
+static inline struct inode *d_backing_inode(const struct dentry *upper)
+{
+        struct inode *inode = upper->d_inode;
+
+        return inode;
+}
+
+/**
+ * d_backing_dentry - Get upper or lower dentry we should be using
+ * @upper: The upper layer
+ *
+ * This is the helper that should be used to get the dentry of the inode that
+ * will be used if this dentry were opened as a file.  It may be the upper
+ * dentry or it may be a lower dentry pinned by the upper.
+ *
+ * Normal filesystems should not use this to access their own dentries.
+ */
+static inline struct dentry *d_backing_dentry(struct dentry *upper)
+{
+        return upper;
+}
+
 #endif  /* __LINUX_DCACHE_H */
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 40cd75e21ea2..b6997a0cb528 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -189,25 +189,6 @@ enum dma_ctrl_flags {
 };
 
 /**
- * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
- * on a running channel.
- * @DMA_TERMINATE_ALL: terminate all ongoing transfers
- * @DMA_PAUSE: pause ongoing transfers
- * @DMA_RESUME: resume paused transfer
- * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
- * that need to runtime reconfigure the slave channels (as opposed to passing
- * configuration data in statically from the platform). An additional
- * argument of struct dma_slave_config must be passed in with this
- * command.
- */
-enum dma_ctrl_cmd {
-        DMA_TERMINATE_ALL,
-        DMA_PAUSE,
-        DMA_RESUME,
-        DMA_SLAVE_CONFIG,
-};
-
-/**
  * enum sum_check_bits - bit position of pq_check_flags
  */
 enum sum_check_bits {
@@ -298,6 +279,9 @@ enum dma_slave_buswidth {
         DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
         DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
         DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
+        DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
+        DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
+        DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
 };
 
 /**
@@ -336,9 +320,8 @@ enum dma_slave_buswidth {
  * This struct is passed in as configuration data to a DMA engine
  * in order to set up a certain channel for DMA transport at runtime.
  * The DMA device/engine has to provide support for an additional
- * command in the channel config interface, DMA_SLAVE_CONFIG
- * and this struct will then be passed in as an argument to the
- * DMA engine device_control() function.
+ * callback in the dma_device structure, device_config and this struct
+ * will then be passed in as an argument to the function.
  *
  * The rationale for adding configuration information to this struct is as
  * follows: if it is likely that more than one DMA slave controllers in
@@ -387,7 +370,7 @@ enum dma_residue_granularity {
 /* struct dma_slave_caps - expose capabilities of a slave channel only
  *
  * @src_addr_widths: bit mask of src addr widths the channel supports
- * @dstn_addr_widths: bit mask of dstn addr widths the channel supports
+ * @dst_addr_widths: bit mask of dstn addr widths the channel supports
  * @directions: bit mask of slave direction the channel supported
  *      since the enum dma_transfer_direction is not defined as bits for each
  *      type of direction, the dma controller should fill (1 << <TYPE>) and same
@@ -398,7 +381,7 @@ enum dma_residue_granularity {
  */
 struct dma_slave_caps {
         u32 src_addr_widths;
-        u32 dstn_addr_widths;
+        u32 dst_addr_widths;
         u32 directions;
         bool cmd_pause;
         bool cmd_terminate;
@@ -594,6 +577,14 @@ struct dma_tx_state {
  * @fill_align: alignment shift for memset operations
  * @dev_id: unique device ID
  * @dev: struct device reference for dma mapping api
+ * @src_addr_widths: bit mask of src addr widths the device supports
+ * @dst_addr_widths: bit mask of dst addr widths the device supports
+ * @directions: bit mask of slave direction the device supports since
+ *      the enum dma_transfer_direction is not defined as bits for
+ *      each type of direction, the dma controller should fill (1 <<
+ *      <TYPE>) and same should be checked by controller as well
+ * @residue_granularity: granularity of the transfer residue reported
+ *      by tx_status
  * @device_alloc_chan_resources: allocate resources and return the
  *      number of allocated descriptors
  * @device_free_chan_resources: release DMA channel's resources
@@ -608,14 +599,19 @@ struct dma_tx_state {
  *      The function takes a buffer of size buf_len. The callback function will
  *      be called after period_len bytes have been transferred.
  * @device_prep_interleaved_dma: Transfer expression in a generic way.
- * @device_control: manipulate all pending operations on a channel, returns
- *      zero or error code
+ * @device_config: Pushes a new configuration to a channel, return 0 or an error
+ *      code
+ * @device_pause: Pauses any transfer happening on a channel. Returns
+ *      0 or an error code
+ * @device_resume: Resumes any transfer on a channel previously
+ *      paused. Returns 0 or an error code
+ * @device_terminate_all: Aborts all transfers on a channel. Returns 0
+ *      or an error code
  * @device_tx_status: poll for transaction completion, the optional
  *      txstate parameter can be supplied with a pointer to get a
  *      struct with auxiliary transfer status information, otherwise the call
  *      will just return a simple status code
  * @device_issue_pending: push pending transactions to hardware
- * @device_slave_caps: return the slave channel capabilities
  */
 struct dma_device {
 
@@ -635,14 +631,19 @@ struct dma_device {
         int dev_id;
         struct device *dev;
 
+        u32 src_addr_widths;
+        u32 dst_addr_widths;
+        u32 directions;
+        enum dma_residue_granularity residue_granularity;
+
         int (*device_alloc_chan_resources)(struct dma_chan *chan);
         void (*device_free_chan_resources)(struct dma_chan *chan);
 
         struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
-                struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
+                struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
                 size_t len, unsigned long flags);
         struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
-                struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
+                struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
                 unsigned int src_cnt, size_t len, unsigned long flags);
         struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
                 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
@@ -674,31 +675,26 @@ struct dma_device {
         struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
                 struct dma_chan *chan, struct dma_interleaved_template *xt,
                 unsigned long flags);
-        int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
-                unsigned long arg);
+
+        int (*device_config)(struct dma_chan *chan,
+                             struct dma_slave_config *config);
+        int (*device_pause)(struct dma_chan *chan);
+        int (*device_resume)(struct dma_chan *chan);
+        int (*device_terminate_all)(struct dma_chan *chan);
 
         enum dma_status (*device_tx_status)(struct dma_chan *chan,
                                             dma_cookie_t cookie,
                                             struct dma_tx_state *txstate);
         void (*device_issue_pending)(struct dma_chan *chan);
-        int (*device_slave_caps)(struct dma_chan *chan, struct dma_slave_caps *caps);
 };
 
-static inline int dmaengine_device_control(struct dma_chan *chan,
-                                           enum dma_ctrl_cmd cmd,
-                                           unsigned long arg)
-{
-        if (chan->device->device_control)
-                return chan->device->device_control(chan, cmd, arg);
-
-        return -ENOSYS;
-}
-
 static inline int dmaengine_slave_config(struct dma_chan *chan,
                                           struct dma_slave_config *config)
 {
-        return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
-                        (unsigned long)config);
+        if (chan->device->device_config)
+                return chan->device->device_config(chan, config);
+
+        return -ENOSYS;
 }
 
 static inline bool is_slave_direction(enum dma_transfer_direction direction)
@@ -765,34 +761,28 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg(
                         src_sg, src_nents, flags);
 }
 
-static inline int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
-{
-        if (!chan || !caps)
-                return -EINVAL;
-
-        /* check if the channel supports slave transactions */
-        if (!test_bit(DMA_SLAVE, chan->device->cap_mask.bits))
-                return -ENXIO;
-
-        if (chan->device->device_slave_caps)
-                return chan->device->device_slave_caps(chan, caps);
-
-        return -ENXIO;
-}
-
 static inline int dmaengine_terminate_all(struct dma_chan *chan)
 {
-        return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
+        if (chan->device->device_terminate_all)
+                return chan->device->device_terminate_all(chan);
+
+        return -ENOSYS;
 }
 
 static inline int dmaengine_pause(struct dma_chan *chan)
 {
-        return dmaengine_device_control(chan, DMA_PAUSE, 0);
+        if (chan->device->device_pause)
+                return chan->device->device_pause(chan);
+
+        return -ENOSYS;
 }
 
 static inline int dmaengine_resume(struct dma_chan *chan)
 {
-        return dmaengine_device_control(chan, DMA_RESUME, 0);
+        if (chan->device->device_resume)
+                return chan->device->device_resume(chan);
+
+        return -ENOSYS;
 }
 
 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
@@ -1059,6 +1049,7 @@ struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
                                                   const char *name);
 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
 void dma_release_channel(struct dma_chan *chan);
+int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
 #else
 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
 {
@@ -1093,6 +1084,11 @@ static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
 static inline void dma_release_channel(struct dma_chan *chan)
 {
 }
+static inline int dma_get_slave_caps(struct dma_chan *chan,
+                                     struct dma_slave_caps *caps)
+{
+        return -ENXIO;
+}
 #endif
 
 /* --- DMA device --- */
diff --git a/include/linux/fs.h b/include/linux/fs.h
index 447932aed1e1..b4d71b5e1ff2 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -968,9 +968,6 @@ struct file_lock_context {
         struct list_head        flc_flock;
         struct list_head        flc_posix;
         struct list_head        flc_lease;
-        int                     flc_flock_cnt;
-        int                     flc_posix_cnt;
-        int                     flc_lease_cnt;
 };
 
 /* The following constant reflects the upper bound of the file/locking space */
diff --git a/include/linux/hid-sensor-hub.h b/include/linux/hid-sensor-hub.h
index 51f7ccadf923..4173a8fdad9e 100644
--- a/include/linux/hid-sensor-hub.h
+++ b/include/linux/hid-sensor-hub.h
@@ -33,6 +33,8 @@
  * @units:              Measurment unit for this attribute.
  * @unit_expo:          Exponent used in the data.
  * @size:               Size in bytes for data size.
+ * @logical_minimum:    Logical minimum value for this attribute.
+ * @logical_maximum:    Logical maximum value for this attribute.
  */
 struct hid_sensor_hub_attribute_info {
         u32 usage_id;
@@ -146,6 +148,7 @@ int sensor_hub_input_get_attribute_info(struct hid_sensor_hub_device *hsdev,
 
 /**
 * sensor_hub_input_attr_get_raw_value() - Synchronous read request
+* @hsdev:       Hub device instance.
 * @usage_id:    Attribute usage id of parent physical device as per spec
 * @attr_usage_id:       Attribute usage id as per spec
 * @report_id:   Report id to look for
@@ -160,6 +163,7 @@ int sensor_hub_input_attr_get_raw_value(struct hid_sensor_hub_device *hsdev,
                         u32 attr_usage_id, u32 report_id);
 /**
 * sensor_hub_set_feature() - Feature set request
+* @hsdev:       Hub device instance.
 * @report_id:   Report id to look for
 * @field_index: Field index inside a report
 * @value:       Value to set
@@ -172,6 +176,7 @@ int sensor_hub_set_feature(struct hid_sensor_hub_device *hsdev, u32 report_id,
 
 /**
 * sensor_hub_get_feature() - Feature get request
+* @hsdev:       Hub device instance.
 * @report_id:   Report id to look for
 * @field_index: Field index inside a report
 * @value:       Place holder for return value
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 7c7695940ddd..f17da50402a4 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -130,8 +130,6 @@ extern s32 i2c_smbus_write_i2c_block_data(const struct i2c_client *client,
  * @probe: Callback for device binding
  * @remove: Callback for device unbinding
  * @shutdown: Callback for device shutdown
- * @suspend: Callback for device suspend
- * @resume: Callback for device resume
  * @alert: Alert callback, for example for the SMBus alert protocol
  * @command: Callback for bus-wide signaling (optional)
  * @driver: Device driver model driver
@@ -174,8 +172,6 @@ struct i2c_driver {
 
         /* driver model interfaces that don't relate to enumeration  */
         void (*shutdown)(struct i2c_client *);
-        int (*suspend)(struct i2c_client *, pm_message_t mesg);
-        int (*resume)(struct i2c_client *);
 
         /* Alert callback, for example for the SMBus alert protocol.
          * The format and meaning of the data value depends on the protocol.
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h
index 420f77b34d02..e6a6aac451db 100644
--- a/include/linux/irqchip/mips-gic.h
+++ b/include/linux/irqchip/mips-gic.h
@@ -243,7 +243,6 @@ extern void gic_write_cpu_compare(cycle_t cnt, int cpu);
 extern void gic_send_ipi(unsigned int intr);
 extern unsigned int plat_ipi_call_int_xlate(unsigned int);
 extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
-extern unsigned int gic_get_timer_pending(void);
 extern int gic_get_c0_compare_int(void);
 extern int gic_get_c0_perfcount_int(void);
 #endif /* __LINUX_IRQCHIP_MIPS_GIC_H */
diff --git a/include/linux/kdb.h b/include/linux/kdb.h
index 75ae2e2631fc..a19bcf9e762e 100644
--- a/include/linux/kdb.h
+++ b/include/linux/kdb.h
@@ -156,8 +156,14 @@ typedef enum {
         KDB_REASON_SYSTEM_NMI,  /* In NMI due to SYSTEM cmd; regs valid */
 } kdb_reason_t;
 
+enum kdb_msgsrc {
+        KDB_MSGSRC_INTERNAL, /* direct call to kdb_printf() */
+        KDB_MSGSRC_PRINTK, /* trapped from printk() */
+};
+
 extern int kdb_trap_printk;
-extern __printf(1, 0) int vkdb_printf(const char *fmt, va_list args);
+extern __printf(2, 0) int vkdb_printf(enum kdb_msgsrc src, const char *fmt,
+                                      va_list args);
 extern __printf(1, 2) int kdb_printf(const char *, ...);
 typedef __printf(1, 2) int (*kdb_printf_t)(const char *, ...);
 
diff --git a/include/linux/lguest_launcher.h b/include/linux/lguest_launcher.h
index 495203ff221c..acd5b12565cc 100644
--- a/include/linux/lguest_launcher.h
+++ b/include/linux/lguest_launcher.h
@@ -8,52 +8,13 @@
  *
  * The Guest needs devices to do anything useful.  Since we don't let it touch
  * real devices (think of the damage it could do!) we provide virtual devices.
- * We could emulate a PCI bus with various devices on it, but that is a fairly
- * complex burden for the Host and suboptimal for the Guest, so we have our own
- * simple lguest bus and we use "virtio" drivers.  These drivers need a set of
- * routines from us which will actually do the virtual I/O, but they handle all
- * the net/block/console stuff themselves.  This means that if we want to add
- * a new device, we simply need to write a new virtio driver and create support
- * for it in the Launcher: this code won't need to change.
+ * We emulate a PCI bus with virtio devices on it; we used to have our own
+ * lguest bus which was far simpler, but this tests the virtio 1.0 standard.
  *
  * Virtio devices are also used by kvm, so we can simply reuse their optimized
  * device drivers.  And one day when everyone uses virtio, my plan will be
  * complete.  Bwahahahah!
- *
- * Devices are described by a simplified ID, a status byte, and some "config"
- * bytes which describe this device's configuration.  This is placed by the
- * Launcher just above the top of physical memory:
- */
-struct lguest_device_desc {
-        /* The device type: console, network, disk etc.  Type 0 terminates. */
-        __u8 type;
-        /* The number of virtqueues (first in config array) */
-        __u8 num_vq;
-        /*
-         * The number of bytes of feature bits.  Multiply by 2: one for host
-         * features and one for Guest acknowledgements.
-         */
-        __u8 feature_len;
-        /* The number of bytes of the config array after virtqueues. */
-        __u8 config_len;
-        /* A status byte, written by the Guest. */
-        __u8 status;
-        __u8 config[0];
-};
-
-/*D:135
- * This is how we expect the device configuration field for a virtqueue
- * to be laid out in config space.
  */
-struct lguest_vqconfig {
-        /* The number of entries in the virtio_ring */
-        __u16 num;
-        /* The interrupt we get when something happens. */
-        __u16 irq;
-        /* The page number of the virtio ring for this device. */
-        __u32 pfn;
-};
-/*:*/
 
 /* Write command first word is a request. */
 enum lguest_req
@@ -62,12 +23,22 @@ enum lguest_req
         LHREQ_GETDMA, /* No longer used */
         LHREQ_IRQ, /* + irq */
         LHREQ_BREAK, /* No longer used */
-        LHREQ_EVENTFD, /* + address, fd. */
+        LHREQ_EVENTFD, /* No longer used. */
+        LHREQ_GETREG, /* + offset within struct pt_regs (then read value). */
+        LHREQ_SETREG, /* + offset within struct pt_regs, value. */
+        LHREQ_TRAP, /* + trap number to deliver to guest. */
 };
 
 /*
- * The alignment to use between consumer and producer parts of vring.
- * x86 pagesize for historical reasons.
+ * This is what read() of the lguest fd populates.  trap ==
+ * LGUEST_TRAP_ENTRY for an LHCALL_NOTIFY (addr is the
+ * argument), 14 for a page fault in the MMIO region (addr is
+ * the trap address, insn is the instruction), or 13 for a GPF
+ * (insn is the instruction).
  */
-#define LGUEST_VRING_ALIGN      4096
+struct lguest_pending {
+        __u8 trap;
+        __u8 insn[7];
+        __u32 addr;
+};
 #endif /* _LINUX_LGUEST_LAUNCHER */
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h
index 81589d176ae8..dfabd6db7ddf 100644
--- a/include/linux/mfd/axp20x.h
+++ b/include/linux/mfd/axp20x.h
@@ -124,10 +124,27 @@ enum {
 #define AXP288_PMIC_ADC_H               0x56
 #define AXP288_PMIC_ADC_L               0x57
 #define AXP288_ADC_TS_PIN_CTRL          0x84
-
 #define AXP288_PMIC_ADC_EN              0x84
-#define AXP288_FG_TUNE5                 0xed
 
+/* Fuel Gauge */
+#define AXP288_FG_RDC1_REG          0xba
+#define AXP288_FG_RDC0_REG          0xbb
+#define AXP288_FG_OCVH_REG          0xbc
+#define AXP288_FG_OCVL_REG          0xbd
+#define AXP288_FG_OCV_CURVE_REG     0xc0
+#define AXP288_FG_DES_CAP1_REG      0xe0
+#define AXP288_FG_DES_CAP0_REG      0xe1
+#define AXP288_FG_CC_MTR1_REG       0xe2
+#define AXP288_FG_CC_MTR0_REG       0xe3
+#define AXP288_FG_OCV_CAP_REG       0xe4
+#define AXP288_FG_CC_CAP_REG        0xe5
+#define AXP288_FG_LOW_CAP_REG       0xe6
+#define AXP288_FG_TUNE0             0xe8
+#define AXP288_FG_TUNE1             0xe9
+#define AXP288_FG_TUNE2             0xea
+#define AXP288_FG_TUNE3             0xeb
+#define AXP288_FG_TUNE4             0xec
+#define AXP288_FG_TUNE5             0xed
 
 /* Regulators IDs */
 enum {
@@ -236,4 +253,26 @@ struct axp20x_dev {
         const struct regmap_irq_chip    *regmap_irq_chip;
 };
 
+#define BATTID_LEN                              64
+#define OCV_CURVE_SIZE                  32
+#define MAX_THERM_CURVE_SIZE    25
+#define PD_DEF_MIN_TEMP                 0
+#define PD_DEF_MAX_TEMP                 55
+
+struct axp20x_fg_pdata {
+        char battid[BATTID_LEN + 1];
+        int design_cap;
+        int min_volt;
+        int max_volt;
+        int max_temp;
+        int min_temp;
+        int cap1;
+        int cap0;
+        int rdc1;
+        int rdc0;
+        int ocv_curve[OCV_CURVE_SIZE];
+        int tcsz;
+        int thermistor_curve[MAX_THERM_CURVE_SIZE][2];
+};
+
 #endif /* __LINUX_MFD_AXP20X_H */
diff --git a/include/linux/mfd/da9063/core.h b/include/linux/mfd/da9063/core.h
index b92a3262f8f6..79f4d822ba13 100644
--- a/include/linux/mfd/da9063/core.h
+++ b/include/linux/mfd/da9063/core.h
@@ -36,6 +36,7 @@ enum da9063_models {
 enum da9063_variant_codes {
         PMIC_DA9063_AD = 0x3,
         PMIC_DA9063_BB = 0x5,
+        PMIC_DA9063_CA = 0x6,
 };
 
 /* Interrupts */
diff --git a/include/linux/mfd/da9150/core.h b/include/linux/mfd/da9150/core.h
new file mode 100644
index 000000000000..76e668933a77
--- /dev/null
+++ b/include/linux/mfd/da9150/core.h
@@ -0,0 +1,68 @@
+/*
+ * DA9150 MFD Driver - Core Data
+ *
+ * Copyright (c) 2014 Dialog Semiconductor
+ *
+ * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __DA9150_CORE_H
+#define __DA9150_CORE_H
+
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/regmap.h>
+
+/* I2C address paging */
+#define DA9150_REG_PAGE_SHIFT   8
+#define DA9150_REG_PAGE_MASK    0xFF
+
+/* IRQs */
+#define DA9150_NUM_IRQ_REGS     4
+#define DA9150_IRQ_VBUS         0
+#define DA9150_IRQ_CHG          1
+#define DA9150_IRQ_TCLASS       2
+#define DA9150_IRQ_TJUNC        3
+#define DA9150_IRQ_VFAULT       4
+#define DA9150_IRQ_CONF         5
+#define DA9150_IRQ_DAT          6
+#define DA9150_IRQ_DTYPE        7
+#define DA9150_IRQ_ID           8
+#define DA9150_IRQ_ADP          9
+#define DA9150_IRQ_SESS_END     10
+#define DA9150_IRQ_SESS_VLD     11
+#define DA9150_IRQ_FG           12
+#define DA9150_IRQ_GP           13
+#define DA9150_IRQ_TBAT         14
+#define DA9150_IRQ_GPIOA        15
+#define DA9150_IRQ_GPIOB        16
+#define DA9150_IRQ_GPIOC        17
+#define DA9150_IRQ_GPIOD        18
+#define DA9150_IRQ_GPADC        19
+#define DA9150_IRQ_WKUP         20
+
+struct da9150_pdata {
+        int irq_base;
+};
+
+struct da9150 {
+        struct device *dev;
+        struct regmap *regmap;
+        struct regmap_irq_chip_data *regmap_irq_data;
+        int irq;
+        int irq_base;
+};
+
+/* Device I/O */
+u8 da9150_reg_read(struct da9150 *da9150, u16 reg);
+void da9150_reg_write(struct da9150 *da9150, u16 reg, u8 val);
+void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val);
+
+void da9150_bulk_read(struct da9150 *da9150, u16 reg, int count, u8 *buf);
+void da9150_bulk_write(struct da9150 *da9150, u16 reg, int count, const u8 *buf);
+#endif /* __DA9150_CORE_H */
diff --git a/include/linux/mfd/da9150/registers.h b/include/linux/mfd/da9150/registers.h
new file mode 100644
index 000000000000..27ca6ee4d840
--- /dev/null
+++ b/include/linux/mfd/da9150/registers.h
@@ -0,0 +1,1155 @@
+/*
+ * DA9150 MFD Driver - Registers
+ *
+ * Copyright (c) 2014 Dialog Semiconductor
+ *
+ * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __DA9150_REGISTERS_H
+#define __DA9150_REGISTERS_H
+
+#include <linux/bitops.h>
+
+/* Registers */
+#define DA9150_PAGE_CON                 0x000
+#define DA9150_STATUS_A                 0x068
+#define DA9150_STATUS_B                 0x069
+#define DA9150_STATUS_C                 0x06A
+#define DA9150_STATUS_D                 0x06B
+#define DA9150_STATUS_E                 0x06C
+#define DA9150_STATUS_F                 0x06D
+#define DA9150_STATUS_G                 0x06E
+#define DA9150_STATUS_H                 0x06F
+#define DA9150_STATUS_I                 0x070
+#define DA9150_STATUS_J                 0x071
+#define DA9150_STATUS_K                 0x072
+#define DA9150_STATUS_L                 0x073
+#define DA9150_STATUS_N                 0x074
+#define DA9150_FAULT_LOG_A              0x076
+#define DA9150_FAULT_LOG_B              0x077
+#define DA9150_EVENT_E                  0x078
+#define DA9150_EVENT_F                  0x079
+#define DA9150_EVENT_G                  0x07A
+#define DA9150_EVENT_H                  0x07B
+#define DA9150_IRQ_MASK_E               0x07C
+#define DA9150_IRQ_MASK_F               0x07D
+#define DA9150_IRQ_MASK_G               0x07E
+#define DA9150_IRQ_MASK_H               0x07F
+#define DA9150_PAGE_CON_1               0x080
+#define DA9150_CONFIG_A                 0x0E0
+#define DA9150_CONFIG_B                 0x0E1
+#define DA9150_CONFIG_C                 0x0E2
+#define DA9150_CONFIG_D                 0x0E3
+#define DA9150_CONFIG_E                 0x0E4
+#define DA9150_CONTROL_A                0x0E5
+#define DA9150_CONTROL_B                0x0E6
+#define DA9150_CONTROL_C                0x0E7
+#define DA9150_GPIO_A_B                 0x0E8
+#define DA9150_GPIO_C_D                 0x0E9
+#define DA9150_GPIO_MODE_CONT           0x0EA
+#define DA9150_GPIO_CTRL_B              0x0EB
+#define DA9150_GPIO_CTRL_A              0x0EC
+#define DA9150_GPIO_CTRL_C              0x0ED
+#define DA9150_GPIO_CFG_A               0x0EE
+#define DA9150_GPIO_CFG_B               0x0EF
+#define DA9150_GPIO_CFG_C               0x0F0
+#define DA9150_GPADC_MAN                0x0F2
+#define DA9150_GPADC_RES_A              0x0F4
+#define DA9150_GPADC_RES_B              0x0F5
+#define DA9150_PAGE_CON_2               0x100
+#define DA9150_OTP_CONT_SHARED          0x101
+#define DA9150_INTERFACE_SHARED         0x105
+#define DA9150_CONFIG_A_SHARED          0x106
+#define DA9150_CONFIG_D_SHARED          0x109
+#define DA9150_ADETVB_CFG_C             0x150
+#define DA9150_ADETD_STAT               0x151
+#define DA9150_ADET_CMPSTAT             0x152
+#define DA9150_ADET_CTRL_A              0x153
+#define DA9150_ADETVB_CFG_B             0x154
+#define DA9150_ADETVB_CFG_A             0x155
+#define DA9150_ADETAC_CFG_A             0x156
+#define DA9150_ADDETAC_CFG_B            0x157
+#define DA9150_ADETAC_CFG_C             0x158
+#define DA9150_ADETAC_CFG_D             0x159
+#define DA9150_ADETVB_CFG_D             0x15A
+#define DA9150_ADETID_CFG_A             0x15B
+#define DA9150_ADET_RID_PT_CHG_H        0x15C
+#define DA9150_ADET_RID_PT_CHG_L        0x15D
+#define DA9150_PPR_TCTR_B               0x160
+#define DA9150_PPR_BKCTRL_A             0x163
+#define DA9150_PPR_BKCFG_A              0x164
+#define DA9150_PPR_BKCFG_B              0x165
+#define DA9150_PPR_CHGCTRL_A            0x166
+#define DA9150_PPR_CHGCTRL_B            0x167
+#define DA9150_PPR_CHGCTRL_C            0x168
+#define DA9150_PPR_TCTR_A               0x169
+#define DA9150_PPR_CHGCTRL_D            0x16A
+#define DA9150_PPR_CHGCTRL_E            0x16B
+#define DA9150_PPR_CHGCTRL_F            0x16C
+#define DA9150_PPR_CHGCTRL_G            0x16D
+#define DA9150_PPR_CHGCTRL_H            0x16E
+#define DA9150_PPR_CHGCTRL_I            0x16F
+#define DA9150_PPR_CHGCTRL_J            0x170
+#define DA9150_PPR_CHGCTRL_K            0x171
+#define DA9150_PPR_CHGCTRL_L            0x172
+#define DA9150_PPR_CHGCTRL_M            0x173
+#define DA9150_PPR_THYST_A              0x174
+#define DA9150_PPR_THYST_B              0x175
+#define DA9150_PPR_THYST_C              0x176
+#define DA9150_PPR_THYST_D              0x177
+#define DA9150_PPR_THYST_E              0x178
+#define DA9150_PPR_THYST_F              0x179
+#define DA9150_PPR_THYST_G              0x17A
+#define DA9150_PAGE_CON_3               0x180
+#define DA9150_PAGE_CON_4               0x200
+#define DA9150_PAGE_CON_5               0x280
+#define DA9150_PAGE_CON_6               0x300
+#define DA9150_COREBTLD_STAT_A          0x302
+#define DA9150_COREBTLD_CTRL_A          0x303
+#define DA9150_CORE_CONFIG_A            0x304
+#define DA9150_CORE_CONFIG_C            0x305
+#define DA9150_CORE_CONFIG_B            0x306
+#define DA9150_CORE_CFG_DATA_A          0x307
+#define DA9150_CORE_CFG_DATA_B          0x308
+#define DA9150_CORE_CMD_A               0x309
+#define DA9150_CORE_DATA_A              0x30A
+#define DA9150_CORE_DATA_B              0x30B
+#define DA9150_CORE_DATA_C              0x30C
+#define DA9150_CORE_DATA_D              0x30D
+#define DA9150_CORE2WIRE_STAT_A         0x310
+#define DA9150_CORE2WIRE_CTRL_A         0x311
+#define DA9150_FW_CTRL_A                0x312
+#define DA9150_FW_CTRL_C                0x313
+#define DA9150_FW_CTRL_D                0x314
+#define DA9150_FG_CTRL_A                0x315
+#define DA9150_FG_CTRL_B                0x316
+#define DA9150_FW_CTRL_E                0x317
+#define DA9150_FW_CTRL_B                0x318
+#define DA9150_GPADC_CMAN               0x320
+#define DA9150_GPADC_CRES_A             0x322
+#define DA9150_GPADC_CRES_B             0x323
+#define DA9150_CC_CFG_A                 0x328
+#define DA9150_CC_CFG_B                 0x329
+#define DA9150_CC_ICHG_RES_A            0x32A
+#define DA9150_CC_ICHG_RES_B            0x32B
+#define DA9150_CC_IAVG_RES_A            0x32C
+#define DA9150_CC_IAVG_RES_B            0x32D
+#define DA9150_TAUX_CTRL_A              0x330
+#define DA9150_TAUX_RELOAD_H            0x332
+#define DA9150_TAUX_RELOAD_L            0x333
+#define DA9150_TAUX_VALUE_H             0x334
+#define DA9150_TAUX_VALUE_L             0x335
+#define DA9150_AUX_DATA_0               0x338
+#define DA9150_AUX_DATA_1               0x339
+#define DA9150_AUX_DATA_2               0x33A
+#define DA9150_AUX_DATA_3               0x33B
+#define DA9150_BIF_CTRL                 0x340
+#define DA9150_TBAT_CTRL_A              0x342
+#define DA9150_TBAT_CTRL_B              0x343
+#define DA9150_TBAT_RES_A               0x344
+#define DA9150_TBAT_RES_B               0x345
+
+/* DA9150_PAGE_CON = 0x000 */
+#define DA9150_PAGE_SHIFT                       0
+#define DA9150_PAGE_MASK                        (0x3f << 0)
+#define DA9150_I2C_PAGE_SHIFT                   1
+#define DA9150_I2C_PAGE_MASK                    (0x1f << 1)
+#define DA9150_WRITE_MODE_SHIFT                 6
+#define DA9150_WRITE_MODE_MASK                  BIT(6)
+#define DA9150_REVERT_SHIFT                     7
+#define DA9150_REVERT_MASK                      BIT(7)
+
+/* DA9150_STATUS_A = 0x068 */
+#define DA9150_WKUP_STAT_SHIFT                  2
+#define DA9150_WKUP_STAT_MASK                   (0x0f << 2)
+#define DA9150_SLEEP_STAT_SHIFT                 6
+#define DA9150_SLEEP_STAT_MASK                  (0x03 << 6)
+
+/* DA9150_STATUS_B = 0x069 */
+#define DA9150_VFAULT_STAT_SHIFT                0
+#define DA9150_VFAULT_STAT_MASK                 BIT(0)
+#define DA9150_TFAULT_STAT_SHIFT                1
+#define DA9150_TFAULT_STAT_MASK                 BIT(1)
+
+/* DA9150_STATUS_C = 0x06A */
+#define DA9150_VDD33_STAT_SHIFT                 0
+#define DA9150_VDD33_STAT_MASK                  BIT(0)
+#define DA9150_VDD33_SLEEP_SHIFT                1
+#define DA9150_VDD33_SLEEP_MASK                 BIT(1)
+#define DA9150_LFOSC_STAT_SHIFT                 7
+#define DA9150_LFOSC_STAT_MASK                  BIT(7)
+
+/* DA9150_STATUS_D = 0x06B */
+#define DA9150_GPIOA_STAT_SHIFT                 0
+#define DA9150_GPIOA_STAT_MASK                  BIT(0)
+#define DA9150_GPIOB_STAT_SHIFT                 1
+#define DA9150_GPIOB_STAT_MASK                  BIT(1)
+#define DA9150_GPIOC_STAT_SHIFT                 2
+#define DA9150_GPIOC_STAT_MASK                  BIT(2)
+#define DA9150_GPIOD_STAT_SHIFT                 3
+#define DA9150_GPIOD_STAT_MASK                  BIT(3)
+
+/* DA9150_STATUS_E = 0x06C */
+#define DA9150_DTYPE_SHIFT                      0
+#define DA9150_DTYPE_MASK                       (0x1f << 0)
+#define DA9150_DTYPE_DT_NIL                     (0x00 << 0)
+#define DA9150_DTYPE_DT_USB_OTG                 BIT(0)
+#define DA9150_DTYPE_DT_USB_STD                 (0x02 << 0)
+#define DA9150_DTYPE_DT_USB_CHG                 (0x03 << 0)
+#define DA9150_DTYPE_DT_ACA_CHG                 (0x04 << 0)
+#define DA9150_DTYPE_DT_ACA_OTG                 (0x05 << 0)
+#define DA9150_DTYPE_DT_ACA_DOC                 (0x06 << 0)
+#define DA9150_DTYPE_DT_DED_CHG                 (0x07 << 0)
+#define DA9150_DTYPE_DT_CR5_CHG                 (0x08 << 0)
+#define DA9150_DTYPE_DT_CR4_CHG                 (0x0c << 0)
+#define DA9150_DTYPE_DT_PT_CHG                  (0x11 << 0)
+#define DA9150_DTYPE_DT_NN_ACC                  (0x16 << 0)
+#define DA9150_DTYPE_DT_NN_CHG                  (0x17 << 0)
+
+/* DA9150_STATUS_F = 0x06D */
+#define DA9150_SESS_VLD_SHIFT                   0
+#define DA9150_SESS_VLD_MASK                    BIT(0)
+#define DA9150_ID_ERR_SHIFT                     1
+#define DA9150_ID_ERR_MASK                      BIT(1)
+#define DA9150_PT_CHG_SHIFT                     2
+#define DA9150_PT_CHG_MASK                      BIT(2)
+
+/* DA9150_STATUS_G = 0x06E */
+#define DA9150_RID_SHIFT                        0
+#define DA9150_RID_MASK                         (0xff << 0)
+
+/* DA9150_STATUS_H = 0x06F */
+#define DA9150_VBUS_STAT_SHIFT                  0
+#define DA9150_VBUS_STAT_MASK                   (0x07 << 0)
+#define DA9150_VBUS_STAT_OFF                    (0x00 << 0)
+#define DA9150_VBUS_STAT_WAIT                   BIT(0)
+#define DA9150_VBUS_STAT_CHG                    (0x02 << 0)
+#define DA9150_VBUS_TRED_SHIFT                  3
+#define DA9150_VBUS_TRED_MASK                   BIT(3)
+#define DA9150_VBUS_DROP_STAT_SHIFT             4
+#define DA9150_VBUS_DROP_STAT_MASK              (0x0f << 4)
+
+/* DA9150_STATUS_I = 0x070 */
+#define DA9150_VBUS_ISET_STAT_SHIFT             0
+#define DA9150_VBUS_ISET_STAT_MASK              (0x1f << 0)
+#define DA9150_VBUS_OT_SHIFT                    7
+#define DA9150_VBUS_OT_MASK                     BIT(7)
+
+/* DA9150_STATUS_J = 0x071 */
+#define DA9150_CHG_STAT_SHIFT                   0
+#define DA9150_CHG_STAT_MASK                    (0x0f << 0)
+#define DA9150_CHG_STAT_OFF                     (0x00 << 0)
+#define DA9150_CHG_STAT_SUSP                    BIT(0)
+#define DA9150_CHG_STAT_ACT                     (0x02 << 0)
+#define DA9150_CHG_STAT_PRE                     (0x03 << 0)
+#define DA9150_CHG_STAT_CC                      (0x04 << 0)
+#define DA9150_CHG_STAT_CV                      (0x05 << 0)
+#define DA9150_CHG_STAT_FULL                    (0x06 << 0)
+#define DA9150_CHG_STAT_TEMP                    (0x07 << 0)
+#define DA9150_CHG_STAT_TIME                    (0x08 << 0)
+#define DA9150_CHG_STAT_BAT                     (0x09 << 0)
+#define DA9150_CHG_TEMP_SHIFT                   4
+#define DA9150_CHG_TEMP_MASK                    (0x07 << 4)
+#define DA9150_CHG_TEMP_UNDER                   (0x06 << 4)
+#define DA9150_CHG_TEMP_OVER                    (0x07 << 4)
+#define DA9150_CHG_IEND_STAT_SHIFT              7
+#define DA9150_CHG_IEND_STAT_MASK               BIT(7)
+
+/* DA9150_STATUS_K = 0x072 */
+#define DA9150_CHG_IAV_H_SHIFT                  0
+#define DA9150_CHG_IAV_H_MASK                   (0xff << 0)
+
+/* DA9150_STATUS_L = 0x073 */
+#define DA9150_CHG_IAV_L_SHIFT                  5
+#define DA9150_CHG_IAV_L_MASK                   (0x07 << 5)
+
+/* DA9150_STATUS_N = 0x074 */
+#define DA9150_CHG_TIME_SHIFT                   1
+#define DA9150_CHG_TIME_MASK                    BIT(1)
+#define DA9150_CHG_TRED_SHIFT                   2
+#define DA9150_CHG_TRED_MASK                    BIT(2)
+#define DA9150_CHG_TJUNC_CLASS_SHIFT            3
+#define DA9150_CHG_TJUNC_CLASS_MASK             (0x07 << 3)
+#define DA9150_CHG_TJUNC_CLASS_6                (0x06 << 3)
+#define DA9150_EBS_STAT_SHIFT                   6
+#define DA9150_EBS_STAT_MASK                    BIT(6)
+#define DA9150_CHG_BAT_REMOVED_SHIFT            7
+#define DA9150_CHG_BAT_REMOVED_MASK             BIT(7)
+
+/* DA9150_FAULT_LOG_A = 0x076 */
+#define DA9150_TEMP_FAULT_SHIFT                 0
+#define DA9150_TEMP_FAULT_MASK                  BIT(0)
+#define DA9150_VSYS_FAULT_SHIFT                 1
+#define DA9150_VSYS_FAULT_MASK                  BIT(1)
+#define DA9150_START_FAULT_SHIFT                2
+#define DA9150_START_FAULT_MASK                 BIT(2)
+#define DA9150_EXT_FAULT_SHIFT                  3
+#define DA9150_EXT_FAULT_MASK                   BIT(3)
+#define DA9150_POR_FAULT_SHIFT                  4
+#define DA9150_POR_FAULT_MASK                   BIT(4)
+
+/* DA9150_FAULT_LOG_B = 0x077 */
+#define DA9150_VBUS_FAULT_SHIFT                 0
+#define DA9150_VBUS_FAULT_MASK                  BIT(0)
+#define DA9150_OTG_FAULT_SHIFT                  1
+#define DA9150_OTG_FAULT_MASK                   BIT(1)
+
+/* DA9150_EVENT_E = 0x078 */
+#define DA9150_E_VBUS_SHIFT                     0
+#define DA9150_E_VBUS_MASK                      BIT(0)
+#define DA9150_E_CHG_SHIFT                      1
+#define DA9150_E_CHG_MASK                       BIT(1)
+#define DA9150_E_TCLASS_SHIFT                   2
+#define DA9150_E_TCLASS_MASK                    BIT(2)
+#define DA9150_E_TJUNC_SHIFT                    3
+#define DA9150_E_TJUNC_MASK                     BIT(3)
+#define DA9150_E_VFAULT_SHIFT                   4
+#define DA9150_E_VFAULT_MASK                    BIT(4)
+#define DA9150_EVENTS_H_SHIFT                   5
+#define DA9150_EVENTS_H_MASK                    BIT(5)
+#define DA9150_EVENTS_G_SHIFT                   6
+#define DA9150_EVENTS_G_MASK                    BIT(6)
+#define DA9150_EVENTS_F_SHIFT                   7
+#define DA9150_EVENTS_F_MASK                    BIT(7)
+
+/* DA9150_EVENT_F = 0x079 */
+#define DA9150_E_CONF_SHIFT                     0
+#define DA9150_E_CONF_MASK                      BIT(0)
+#define DA9150_E_DAT_SHIFT                      1
+#define DA9150_E_DAT_MASK                       BIT(1)
+#define DA9150_E_DTYPE_SHIFT                    3
+#define DA9150_E_DTYPE_MASK                     BIT(3)
+#define DA9150_E_ID_SHIFT                       4
+#define DA9150_E_ID_MASK                        BIT(4)
+#define DA9150_E_ADP_SHIFT                      5
+#define DA9150_E_ADP_MASK                       BIT(5)
+#define DA9150_E_SESS_END_SHIFT                 6
+#define DA9150_E_SESS_END_MASK                  BIT(6)
+#define DA9150_E_SESS_VLD_SHIFT                 7
+#define DA9150_E_SESS_VLD_MASK                  BIT(7)
+
+/* DA9150_EVENT_G = 0x07A */
+#define DA9150_E_FG_SHIFT                       0
+#define DA9150_E_FG_MASK                        BIT(0)
+#define DA9150_E_GP_SHIFT                       1
+#define DA9150_E_GP_MASK                        BIT(1)
+#define DA9150_E_TBAT_SHIFT                     2
+#define DA9150_E_TBAT_MASK                      BIT(2)
+#define DA9150_E_GPIOA_SHIFT                    3
+#define DA9150_E_GPIOA_MASK                     BIT(3)
+#define DA9150_E_GPIOB_SHIFT                    4
+#define DA9150_E_GPIOB_MASK                     BIT(4)
+#define DA9150_E_GPIOC_SHIFT                    5
+#define DA9150_E_GPIOC_MASK                     BIT(5)
+#define DA9150_E_GPIOD_SHIFT                    6
+#define DA9150_E_GPIOD_MASK                     BIT(6)
+#define DA9150_E_GPADC_SHIFT                    7
+#define DA9150_E_GPADC_MASK                     BIT(7)
+
+/* DA9150_EVENT_H = 0x07B */
+#define DA9150_E_WKUP_SHIFT                     0
+#define DA9150_E_WKUP_MASK                      BIT(0)
+
+/* DA9150_IRQ_MASK_E = 0x07C */
+#define DA9150_M_VBUS_SHIFT                     0
+#define DA9150_M_VBUS_MASK                      BIT(0)
+#define DA9150_M_CHG_SHIFT                      1
+#define DA9150_M_CHG_MASK                       BIT(1)
+#define DA9150_M_TJUNC_SHIFT                    3
+#define DA9150_M_TJUNC_MASK                     BIT(3)
+#define DA9150_M_VFAULT_SHIFT                   4
+#define DA9150_M_VFAULT_MASK                    BIT(4)
+
+/* DA9150_IRQ_MASK_F = 0x07D */
+#define DA9150_M_CONF_SHIFT                     0
+#define DA9150_M_CONF_MASK                      BIT(0)
+#define DA9150_M_DAT_SHIFT                      1
+#define DA9150_M_DAT_MASK                       BIT(1)
+#define DA9150_M_DTYPE_SHIFT                    3
+#define DA9150_M_DTYPE_MASK                     BIT(3)
+#define DA9150_M_ID_SHIFT                       4
+#define DA9150_M_ID_MASK                        BIT(4)
+#define DA9150_M_ADP_SHIFT                      5
+#define DA9150_M_ADP_MASK                       BIT(5)
+#define DA9150_M_SESS_END_SHIFT                 6
+#define DA9150_M_SESS_END_MASK                  BIT(6)
+#define DA9150_M_SESS_VLD_SHIFT                 7
+#define DA9150_M_SESS_VLD_MASK                  BIT(7)
+
+/* DA9150_IRQ_MASK_G = 0x07E */
+#define DA9150_M_FG_SHIFT                       0
+#define DA9150_M_FG_MASK                        BIT(0)
+#define DA9150_M_GP_SHIFT                       1
+#define DA9150_M_GP_MASK                        BIT(1)
+#define DA9150_M_TBAT_SHIFT                     2
+#define DA9150_M_TBAT_MASK                      BIT(2)
+#define DA9150_M_GPIOA_SHIFT                    3
+#define DA9150_M_GPIOA_MASK                     BIT(3)
+#define DA9150_M_GPIOB_SHIFT                    4
+#define DA9150_M_GPIOB_MASK                     BIT(4)
+#define DA9150_M_GPIOC_SHIFT                    5
+#define DA9150_M_GPIOC_MASK                     BIT(5)
+#define DA9150_M_GPIOD_SHIFT                    6
+#define DA9150_M_GPIOD_MASK                     BIT(6)
+#define DA9150_M_GPADC_SHIFT                    7
+#define DA9150_M_GPADC_MASK                     BIT(7)
+
+/* DA9150_IRQ_MASK_H = 0x07F */
+#define DA9150_M_WKUP_SHIFT                     0
+#define DA9150_M_WKUP_MASK                      BIT(0)
+
+/* DA9150_PAGE_CON_1 = 0x080 */
+#define DA9150_PAGE_SHIFT                       0
+#define DA9150_PAGE_MASK                        (0x3f << 0)
+#define DA9150_WRITE_MODE_SHIFT                 6
+#define DA9150_WRITE_MODE_MASK                  BIT(6)
+#define DA9150_REVERT_SHIFT                     7
+#define DA9150_REVERT_MASK                      BIT(7)
+
+/* DA9150_CONFIG_A = 0x0E0 */
+#define DA9150_RESET_DUR_SHIFT                  0
+#define DA9150_RESET_DUR_MASK                   (0x03 << 0)
+#define DA9150_RESET_EXT_SHIFT                  2
+#define DA9150_RESET_EXT_MASK                   (0x03 << 2)
+#define DA9150_START_MAX_SHIFT                  4
+#define DA9150_START_MAX_MASK                   (0x03 << 4)
+#define DA9150_PS_WAIT_EN_SHIFT                 6
+#define DA9150_PS_WAIT_EN_MASK                  BIT(6)
+#define DA9150_PS_DISABLE_DIRECT_SHIFT          7
+#define DA9150_PS_DISABLE_DIRECT_MASK           BIT(7)
+
+/* DA9150_CONFIG_B = 0x0E1 */
+#define DA9150_VFAULT_ADJ_SHIFT                 0
+#define DA9150_VFAULT_ADJ_MASK                  (0x0f << 0)
+#define DA9150_VFAULT_HYST_SHIFT                4
+#define DA9150_VFAULT_HYST_MASK                 (0x07 << 4)
+#define DA9150_VFAULT_EN_SHIFT                  7
+#define DA9150_VFAULT_EN_MASK                   BIT(7)
+
+/* DA9150_CONFIG_C = 0x0E2 */
+#define DA9150_VSYS_MIN_SHIFT                   3
+#define DA9150_VSYS_MIN_MASK                    (0x1f << 3)
+
+/* DA9150_CONFIG_D = 0x0E3 */
+#define DA9150_LFOSC_EXT_SHIFT                  0
+#define DA9150_LFOSC_EXT_MASK                   BIT(0)
+#define DA9150_VDD33_DWN_SHIFT                  1
+#define DA9150_VDD33_DWN_MASK                   BIT(1)
+#define DA9150_WKUP_PM_EN_SHIFT                 2
+#define DA9150_WKUP_PM_EN_MASK                  BIT(2)
+#define DA9150_WKUP_CE_SEL_SHIFT                3
+#define DA9150_WKUP_CE_SEL_MASK                 (0x03 << 3)
+#define DA9150_WKUP_CLK32K_EN_SHIFT             5
+#define DA9150_WKUP_CLK32K_EN_MASK              BIT(5)
+#define DA9150_DISABLE_DEL_SHIFT                7
+#define DA9150_DISABLE_DEL_MASK                 BIT(7)
+
+/* DA9150_CONFIG_E = 0x0E4 */
+#define DA9150_PM_SPKSUP_DIS_SHIFT              0
+#define DA9150_PM_SPKSUP_DIS_MASK               BIT(0)
+#define DA9150_PM_MERGE_SHIFT                   1
+#define DA9150_PM_MERGE_MASK                    BIT(1)
+#define DA9150_PM_SR_OFF_SHIFT                  2
+#define DA9150_PM_SR_OFF_MASK                   BIT(2)
+#define DA9150_PM_TIMEOUT_EN_SHIFT              3
+#define DA9150_PM_TIMEOUT_EN_MASK               BIT(3)
+#define DA9150_PM_DLY_SEL_SHIFT                 4
+#define DA9150_PM_DLY_SEL_MASK                  (0x07 << 4)
+#define DA9150_PM_OUT_DLY_SEL_SHIFT             7
+#define DA9150_PM_OUT_DLY_SEL_MASK              BIT(7)
+
+/* DA9150_CONTROL_A = 0x0E5 */
+#define DA9150_VDD33_SL_SHIFT                   0
+#define DA9150_VDD33_SL_MASK                    BIT(0)
+#define DA9150_VDD33_LPM_SHIFT                  1
+#define DA9150_VDD33_LPM_MASK                   (0x03 << 1)
+#define DA9150_VDD33_EN_SHIFT                   3
+#define DA9150_VDD33_EN_MASK                    BIT(3)
+#define DA9150_GPI_LPM_SHIFT                    6
+#define DA9150_GPI_LPM_MASK                     BIT(6)
+#define DA9150_PM_IF_LPM_SHIFT                  7
+#define DA9150_PM_IF_LPM_MASK                   BIT(7)
+
+/* DA9150_CONTROL_B = 0x0E6 */
+#define DA9150_LPM_SHIFT                        0
+#define DA9150_LPM_MASK                         BIT(0)
+#define DA9150_RESET_SHIFT                      1
+#define DA9150_RESET_MASK                       BIT(1)
+#define DA9150_RESET_USRCONF_EN_SHIFT           2
+#define DA9150_RESET_USRCONF_EN_MASK            BIT(2)
+
+/* DA9150_CONTROL_C = 0x0E7 */
+#define DA9150_DISABLE_SHIFT                    0
+#define DA9150_DISABLE_MASK                     BIT(0)
+
+/* DA9150_GPIO_A_B = 0x0E8 */
+#define DA9150_GPIOA_PIN_SHIFT                  0
+#define DA9150_GPIOA_PIN_MASK                   (0x07 << 0)
+#define DA9150_GPIOA_PIN_GPI                    (0x00 << 0)
+#define DA9150_GPIOA_PIN_GPO_OD                 BIT(0)
+#define DA9150_GPIOA_TYPE_SHIFT                 3
+#define DA9150_GPIOA_TYPE_MASK                  BIT(3)
+#define DA9150_GPIOB_PIN_SHIFT                  4
+#define DA9150_GPIOB_PIN_MASK                   (0x07 << 4)
+#define DA9150_GPIOB_PIN_GPI                    (0x00 << 4)
+#define DA9150_GPIOB_PIN_GPO_OD                 BIT(4)
+#define DA9150_GPIOB_TYPE_SHIFT                 7
+#define DA9150_GPIOB_TYPE_MASK                  BIT(7)
+
+/* DA9150_GPIO_C_D = 0x0E9 */
+#define DA9150_GPIOC_PIN_SHIFT                  0
+#define DA9150_GPIOC_PIN_MASK                   (0x07 << 0)
+#define DA9150_GPIOC_PIN_GPI                    (0x00 << 0)
+#define DA9150_GPIOC_PIN_GPO_OD                 BIT(0)
+#define DA9150_GPIOC_TYPE_SHIFT                 3
+#define DA9150_GPIOC_TYPE_MASK                  BIT(3)
+#define DA9150_GPIOD_PIN_SHIFT                  4
+#define DA9150_GPIOD_PIN_MASK                   (0x07 << 4)
+#define DA9150_GPIOD_PIN_GPI                    (0x00 << 4)
+#define DA9150_GPIOD_PIN_GPO_OD                 BIT(4)
+#define DA9150_GPIOD_TYPE_SHIFT                 7
+#define DA9150_GPIOD_TYPE_MASK                  BIT(7)
+
+/* DA9150_GPIO_MODE_CONT = 0x0EA */
+#define DA9150_GPIOA_MODE_SHIFT                 0
+#define DA9150_GPIOA_MODE_MASK                  BIT(0)
+#define DA9150_GPIOB_MODE_SHIFT                 1
+#define DA9150_GPIOB_MODE_MASK                  BIT(1)
+#define DA9150_GPIOC_MODE_SHIFT                 2
+#define DA9150_GPIOC_MODE_MASK                  BIT(2)
+#define DA9150_GPIOD_MODE_SHIFT                 3
+#define DA9150_GPIOD_MODE_MASK                  BIT(3)
+#define DA9150_GPIOA_CONT_SHIFT                 4
+#define DA9150_GPIOA_CONT_MASK                  BIT(4)
+#define DA9150_GPIOB_CONT_SHIFT                 5
+#define DA9150_GPIOB_CONT_MASK                  BIT(5)
+#define DA9150_GPIOC_CONT_SHIFT                 6
+#define DA9150_GPIOC_CONT_MASK                  BIT(6)
+#define DA9150_GPIOD_CONT_SHIFT                 7
+#define DA9150_GPIOD_CONT_MASK                  BIT(7)
+
+/* DA9150_GPIO_CTRL_B = 0x0EB */
+#define DA9150_WAKE_PIN_SHIFT                   0
+#define DA9150_WAKE_PIN_MASK                    (0x03 << 0)
+#define DA9150_WAKE_MODE_SHIFT                  2
+#define DA9150_WAKE_MODE_MASK                   BIT(2)
+#define DA9150_WAKE_CONT_SHIFT                  3
+#define DA9150_WAKE_CONT_MASK                   BIT(3)
+#define DA9150_WAKE_DLY_SHIFT                   4
+#define DA9150_WAKE_DLY_MASK                    BIT(4)
+
+/* DA9150_GPIO_CTRL_A = 0x0EC */
+#define DA9150_GPIOA_ANAEN_SHIFT                0
+#define DA9150_GPIOA_ANAEN_MASK                 BIT(0)
+#define DA9150_GPIOB_ANAEN_SHIFT                1
+#define DA9150_GPIOB_ANAEN_MASK                 BIT(1)
+#define DA9150_GPIOC_ANAEN_SHIFT                2
+#define DA9150_GPIOC_ANAEN_MASK                 BIT(2)
+#define DA9150_GPIOD_ANAEN_SHIFT                3
+#define DA9150_GPIOD_ANAEN_MASK                 BIT(3)
+#define DA9150_GPIO_ANAEN                       0x01
+#define DA9150_GPIO_ANAEN_MASK                  0x0F
+#define DA9150_CHGLED_PIN_SHIFT                 5
+#define DA9150_CHGLED_PIN_MASK                  (0x07 << 5)
+
+/* DA9150_GPIO_CTRL_C = 0x0ED */
+#define DA9150_CHGBL_DUR_SHIFT                  0
+#define DA9150_CHGBL_DUR_MASK                   (0x03 << 0)
+#define DA9150_CHGBL_DBL_SHIFT                  2
+#define DA9150_CHGBL_DBL_MASK                   BIT(2)
+#define DA9150_CHGBL_FRQ_SHIFT                  3
+#define DA9150_CHGBL_FRQ_MASK                   (0x03 << 3)
+#define DA9150_CHGBL_FLKR_SHIFT                 5
+#define DA9150_CHGBL_FLKR_MASK                  BIT(5)
+
+/* DA9150_GPIO_CFG_A = 0x0EE */
+#define DA9150_CE_LPM_DEB_SHIFT                 0
+#define DA9150_CE_LPM_DEB_MASK                  (0x07 << 0)
+
+/* DA9150_GPIO_CFG_B = 0x0EF */
+#define DA9150_GPIOA_PUPD_SHIFT                 0
+#define DA9150_GPIOA_PUPD_MASK                  BIT(0)
+#define DA9150_GPIOB_PUPD_SHIFT                 1
+#define DA9150_GPIOB_PUPD_MASK                  BIT(1)
+#define DA9150_GPIOC_PUPD_SHIFT                 2
+#define DA9150_GPIOC_PUPD_MASK                  BIT(2)
+#define DA9150_GPIOD_PUPD_SHIFT                 3
+#define DA9150_GPIOD_PUPD_MASK                  BIT(3)
+#define DA9150_GPIO_PUPD_MASK                   (0xF << 0)
+#define DA9150_GPI_DEB_SHIFT                    4
+#define DA9150_GPI_DEB_MASK                     (0x07 << 4)
+#define DA9150_LPM_EN_SHIFT                     7
+#define DA9150_LPM_EN_MASK                      BIT(7)
+
+/* DA9150_GPIO_CFG_C = 0x0F0 */
+#define DA9150_GPI_V_SHIFT                      0
+#define DA9150_GPI_V_MASK                       BIT(0)
+#define DA9150_VDDIO_INT_SHIFT                  1
+#define DA9150_VDDIO_INT_MASK                   BIT(1)
+#define DA9150_FAULT_PIN_SHIFT                  3
+#define DA9150_FAULT_PIN_MASK                   (0x07 << 3)
+#define DA9150_FAULT_TYPE_SHIFT                 6
+#define DA9150_FAULT_TYPE_MASK                  BIT(6)
+#define DA9150_NIRQ_PUPD_SHIFT                  7
+#define DA9150_NIRQ_PUPD_MASK                   BIT(7)
+
+/* DA9150_GPADC_MAN = 0x0F2 */
+#define DA9150_GPADC_EN_SHIFT                   0
+#define DA9150_GPADC_EN_MASK                    BIT(0)
+#define DA9150_GPADC_MUX_SHIFT                  1
+#define DA9150_GPADC_MUX_MASK                   (0x1f << 1)
+
+/* DA9150_GPADC_RES_A = 0x0F4 */
+#define DA9150_GPADC_RES_H_SHIFT                0
+#define DA9150_GPADC_RES_H_MASK                 (0xff << 0)
+
+/* DA9150_GPADC_RES_B = 0x0F5 */
+#define DA9150_GPADC_RUN_SHIFT                  0
+#define DA9150_GPADC_RUN_MASK                   BIT(0)
+#define DA9150_GPADC_RES_L_SHIFT                6
+#define DA9150_GPADC_RES_L_MASK                 (0x03 << 6)
+#define DA9150_GPADC_RES_L_BITS                 2
+
+/* DA9150_PAGE_CON_2 = 0x100 */
+#define DA9150_PAGE_SHIFT                       0
+#define DA9150_PAGE_MASK                        (0x3f << 0)
+#define DA9150_WRITE_MODE_SHIFT                 6
+#define DA9150_WRITE_MODE_MASK                  BIT(6)
+#define DA9150_REVERT_SHIFT                     7
+#define DA9150_REVERT_MASK                      BIT(7)
+
+/* DA9150_OTP_CONT_SHARED = 0x101 */
+#define DA9150_PC_DONE_SHIFT                    3
+#define DA9150_PC_DONE_MASK                     BIT(3)
+
+/* DA9150_INTERFACE_SHARED = 0x105 */
+#define DA9150_IF_BASE_ADDR_SHIFT               4
+#define DA9150_IF_BASE_ADDR_MASK                (0x0f << 4)
+
+/* DA9150_CONFIG_A_SHARED = 0x106 */
+#define DA9150_NIRQ_VDD_SHIFT                   1
+#define DA9150_NIRQ_VDD_MASK                    BIT(1)
+#define DA9150_NIRQ_PIN_SHIFT                   2
+#define DA9150_NIRQ_PIN_MASK                    BIT(2)
+#define DA9150_NIRQ_TYPE_SHIFT                  3
+#define DA9150_NIRQ_TYPE_MASK                   BIT(3)
+#define DA9150_PM_IF_V_SHIFT                    4
+#define DA9150_PM_IF_V_MASK                     BIT(4)
+#define DA9150_PM_IF_FMP_SHIFT                  5
+#define DA9150_PM_IF_FMP_MASK                   BIT(5)
+#define DA9150_PM_IF_HSM_SHIFT                  6
+#define DA9150_PM_IF_HSM_MASK                   BIT(6)
+
+/* DA9150_CONFIG_D_SHARED = 0x109 */
+#define DA9150_NIRQ_MODE_SHIFT                  1
+#define DA9150_NIRQ_MODE_MASK                   BIT(1)
+
+/* DA9150_ADETVB_CFG_C = 0x150 */
+#define DA9150_TADP_RISE_SHIFT                  0
+#define DA9150_TADP_RISE_MASK                   (0xff << 0)
+
+/* DA9150_ADETD_STAT = 0x151 */
+#define DA9150_DCD_STAT_SHIFT                   0
+#define DA9150_DCD_STAT_MASK                    BIT(0)
+#define DA9150_PCD_STAT_SHIFT                   1
+#define DA9150_PCD_STAT_MASK                    (0x03 << 1)
+#define DA9150_SCD_STAT_SHIFT                   3
+#define DA9150_SCD_STAT_MASK                    (0x03 << 3)
+#define DA9150_DP_STAT_SHIFT                    5
+#define DA9150_DP_STAT_MASK                     BIT(5)
+#define DA9150_DM_STAT_SHIFT                    6
+#define DA9150_DM_STAT_MASK                     BIT(6)
+
+/* DA9150_ADET_CMPSTAT = 0x152 */
+#define DA9150_DP_COMP_SHIFT                    1
+#define DA9150_DP_COMP_MASK                     BIT(1)
+#define DA9150_DM_COMP_SHIFT                    2
+#define DA9150_DM_COMP_MASK                     BIT(2)
+#define DA9150_ADP_SNS_COMP_SHIFT               3
+#define DA9150_ADP_SNS_COMP_MASK                BIT(3)
+#define DA9150_ADP_PRB_COMP_SHIFT               4
+#define DA9150_ADP_PRB_COMP_MASK                BIT(4)
+#define DA9150_ID_COMP_SHIFT                    5
+#define DA9150_ID_COMP_MASK                     BIT(5)
+
+/* DA9150_ADET_CTRL_A = 0x153 */
+#define DA9150_AID_DAT_SHIFT                    0
+#define DA9150_AID_DAT_MASK                     BIT(0)
+#define DA9150_AID_ID_SHIFT                     1
+#define DA9150_AID_ID_MASK                      BIT(1)
+#define DA9150_AID_TRIG_SHIFT                   2
+#define DA9150_AID_TRIG_MASK                    BIT(2)
+
+/* DA9150_ADETVB_CFG_B = 0x154 */
+#define DA9150_VB_MODE_SHIFT                    0
+#define DA9150_VB_MODE_MASK                     (0x03 << 0)
+#define DA9150_VB_MODE_VB_SESS                  BIT(0)
+
+#define DA9150_TADP_PRB_SHIFT                   2
+#define DA9150_TADP_PRB_MASK                    BIT(2)
+#define DA9150_DAT_RPD_EXT_SHIFT                5
+#define DA9150_DAT_RPD_EXT_MASK                 BIT(5)
+#define DA9150_CONF_RPD_SHIFT                   6
+#define DA9150_CONF_RPD_MASK                    BIT(6)
+#define DA9150_CONF_SRP_SHIFT                   7
+#define DA9150_CONF_SRP_MASK                    BIT(7)
+
+/* DA9150_ADETVB_CFG_A = 0x155 */
+#define DA9150_AID_MODE_SHIFT                   0
+#define DA9150_AID_MODE_MASK                    (0x03 << 0)
+#define DA9150_AID_EXT_POL_SHIFT                2
+#define DA9150_AID_EXT_POL_MASK                 BIT(2)
+
+/* DA9150_ADETAC_CFG_A = 0x156 */
+#define DA9150_ISET_CDP_SHIFT                   0
+#define DA9150_ISET_CDP_MASK                    (0x1f << 0)
+#define DA9150_CONF_DBP_SHIFT                   5
+#define DA9150_CONF_DBP_MASK                    BIT(5)
+
+/* DA9150_ADDETAC_CFG_B = 0x157 */
+#define DA9150_ISET_DCHG_SHIFT                  0
+#define DA9150_ISET_DCHG_MASK                   (0x1f << 0)
+#define DA9150_CONF_GPIOA_SHIFT                 5
+#define DA9150_CONF_GPIOA_MASK                  BIT(5)
+#define DA9150_CONF_GPIOB_SHIFT                 6
+#define DA9150_CONF_GPIOB_MASK                  BIT(6)
+#define DA9150_AID_VB_SHIFT                     7
+#define DA9150_AID_VB_MASK                      BIT(7)
+
+/* DA9150_ADETAC_CFG_C = 0x158 */
+#define DA9150_ISET_DEF_SHIFT                   0
+#define DA9150_ISET_DEF_MASK                    (0x1f << 0)
+#define DA9150_CONF_MODE_SHIFT                  5
+#define DA9150_CONF_MODE_MASK                   (0x03 << 5)
+#define DA9150_AID_CR_DIS_SHIFT                 7
+#define DA9150_AID_CR_DIS_MASK                  BIT(7)
+
+/* DA9150_ADETAC_CFG_D = 0x159 */
+#define DA9150_ISET_UNIT_SHIFT                  0
+#define DA9150_ISET_UNIT_MASK                   (0x1f << 0)
+#define DA9150_AID_UNCLAMP_SHIFT                5
+#define DA9150_AID_UNCLAMP_MASK                 BIT(5)
+
+/* DA9150_ADETVB_CFG_D = 0x15A */
+#define DA9150_ID_MODE_SHIFT                    0
+#define DA9150_ID_MODE_MASK                     (0x03 << 0)
+#define DA9150_DAT_MODE_SHIFT                   2
+#define DA9150_DAT_MODE_MASK                    (0x0f << 2)
+#define DA9150_DAT_SWP_SHIFT                    6
+#define DA9150_DAT_SWP_MASK                     BIT(6)
+#define DA9150_DAT_CLAMP_EXT_SHIFT              7
+#define DA9150_DAT_CLAMP_EXT_MASK               BIT(7)
+
+/* DA9150_ADETID_CFG_A = 0x15B */
+#define DA9150_TID_POLL_SHIFT                   0
+#define DA9150_TID_POLL_MASK                    (0x07 << 0)
+#define DA9150_RID_CONV_SHIFT                   3
+#define DA9150_RID_CONV_MASK                    BIT(3)
+
+/* DA9150_ADET_RID_PT_CHG_H = 0x15C */
+#define DA9150_RID_PT_CHG_H_SHIFT               0
+#define DA9150_RID_PT_CHG_H_MASK                (0xff << 0)
+
+/* DA9150_ADET_RID_PT_CHG_L = 0x15D */
+#define DA9150_RID_PT_CHG_L_SHIFT               6
+#define DA9150_RID_PT_CHG_L_MASK                (0x03 << 6)
+
+/* DA9150_PPR_TCTR_B = 0x160 */
+#define DA9150_CHG_TCTR_VAL_SHIFT               0
+#define DA9150_CHG_TCTR_VAL_MASK                (0xff << 0)
+
+/* DA9150_PPR_BKCTRL_A = 0x163 */
+#define DA9150_VBUS_MODE_SHIFT                  0
+#define DA9150_VBUS_MODE_MASK                   (0x03 << 0)
+#define DA9150_VBUS_MODE_CHG                    BIT(0)
+#define DA9150_VBUS_MODE_OTG                    (0x02 << 0)
+#define DA9150_VBUS_LPM_SHIFT                   2
+#define DA9150_VBUS_LPM_MASK                    (0x03 << 2)
+#define DA9150_VBUS_SUSP_SHIFT                  4
+#define DA9150_VBUS_SUSP_MASK                   BIT(4)
+#define DA9150_VBUS_PWM_SHIFT                   5
+#define DA9150_VBUS_PWM_MASK                    BIT(5)
+#define DA9150_VBUS_ISO_SHIFT                   6
+#define DA9150_VBUS_ISO_MASK                    BIT(6)
+#define DA9150_VBUS_LDO_SHIFT                   7
+#define DA9150_VBUS_LDO_MASK                    BIT(7)
+
+/* DA9150_PPR_BKCFG_A = 0x164 */
+#define DA9150_VBUS_ISET_SHIFT                  0
+#define DA9150_VBUS_ISET_MASK                   (0x1f << 0)
+#define DA9150_VBUS_IMAX_SHIFT                  5
+#define DA9150_VBUS_IMAX_MASK                   BIT(5)
+#define DA9150_VBUS_IOTG_SHIFT                  6
+#define DA9150_VBUS_IOTG_MASK                   (0x03 << 6)
+
+/* DA9150_PPR_BKCFG_B = 0x165 */
+#define DA9150_VBUS_DROP_SHIFT                  0
+#define DA9150_VBUS_DROP_MASK                   (0x0f << 0)
+#define DA9150_VBUS_FAULT_DIS_SHIFT             6
+#define DA9150_VBUS_FAULT_DIS_MASK              BIT(6)
+#define DA9150_OTG_FAULT_DIS_SHIFT              7
+#define DA9150_OTG_FAULT_DIS_MASK               BIT(7)
+
+/* DA9150_PPR_CHGCTRL_A = 0x166 */
+#define DA9150_CHG_EN_SHIFT                     0
+#define DA9150_CHG_EN_MASK                      BIT(0)
+
+/* DA9150_PPR_CHGCTRL_B = 0x167 */
+#define DA9150_CHG_VBAT_SHIFT                   0
+#define DA9150_CHG_VBAT_MASK                    (0x1f << 0)
+#define DA9150_CHG_VDROP_SHIFT                  6
+#define DA9150_CHG_VDROP_MASK                   (0x03 << 6)
+
+/* DA9150_PPR_CHGCTRL_C = 0x168 */
+#define DA9150_CHG_VFAULT_SHIFT                 0
+#define DA9150_CHG_VFAULT_MASK                  (0x0f << 0)
+#define DA9150_CHG_IPRE_SHIFT                   4
+#define DA9150_CHG_IPRE_MASK                    (0x03 << 4)
+
+/* DA9150_PPR_TCTR_A = 0x169 */
+#define DA9150_CHG_TCTR_SHIFT                   0
+#define DA9150_CHG_TCTR_MASK                    (0x07 << 0)
+#define DA9150_CHG_TCTR_MODE_SHIFT              4
+#define DA9150_CHG_TCTR_MODE_MASK               BIT(4)
+
+/* DA9150_PPR_CHGCTRL_D = 0x16A */
+#define DA9150_CHG_IBAT_SHIFT                   0
+#define DA9150_CHG_IBAT_MASK                    (0xff << 0)
+
+/* DA9150_PPR_CHGCTRL_E = 0x16B */
+#define DA9150_CHG_IEND_SHIFT                   0
+#define DA9150_CHG_IEND_MASK                    (0xff << 0)
+
+/* DA9150_PPR_CHGCTRL_F = 0x16C */
+#define DA9150_CHG_VCOLD_SHIFT                  0
+#define DA9150_CHG_VCOLD_MASK                   (0x1f << 0)
+#define DA9150_TBAT_TQA_EN_SHIFT                6
+#define DA9150_TBAT_TQA_EN_MASK                 BIT(6)
+#define DA9150_TBAT_TDP_EN_SHIFT                7
+#define DA9150_TBAT_TDP_EN_MASK                 BIT(7)
+
+/* DA9150_PPR_CHGCTRL_G = 0x16D */
+#define DA9150_CHG_VWARM_SHIFT                  0
+#define DA9150_CHG_VWARM_MASK                   (0x1f << 0)
+
+/* DA9150_PPR_CHGCTRL_H = 0x16E */
+#define DA9150_CHG_VHOT_SHIFT                   0
+#define DA9150_CHG_VHOT_MASK                    (0x1f << 0)
+
+/* DA9150_PPR_CHGCTRL_I = 0x16F */
+#define DA9150_CHG_ICOLD_SHIFT                  0
+#define DA9150_CHG_ICOLD_MASK                   (0xff << 0)
+
+/* DA9150_PPR_CHGCTRL_J = 0x170 */
+#define DA9150_CHG_IWARM_SHIFT                  0
+#define DA9150_CHG_IWARM_MASK                   (0xff << 0)
+
+/* DA9150_PPR_CHGCTRL_K = 0x171 */
+#define DA9150_CHG_IHOT_SHIFT                   0
+#define DA9150_CHG_IHOT_MASK                    (0xff << 0)
+
+/* DA9150_PPR_CHGCTRL_L = 0x172 */
+#define DA9150_CHG_IBAT_TRED_SHIFT              0
+#define DA9150_CHG_IBAT_TRED_MASK               (0xff << 0)
+
+/* DA9150_PPR_CHGCTRL_M = 0x173 */
+#define DA9150_CHG_VFLOAT_SHIFT                 0
+#define DA9150_CHG_VFLOAT_MASK                  (0x0f << 0)
+#define DA9150_CHG_LPM_SHIFT                    5
+#define DA9150_CHG_LPM_MASK                     BIT(5)
+#define DA9150_CHG_NBLO_SHIFT                   6
+#define DA9150_CHG_NBLO_MASK                    BIT(6)
+#define DA9150_EBS_EN_SHIFT                     7
+#define DA9150_EBS_EN_MASK                      BIT(7)
+
+/* DA9150_PPR_THYST_A = 0x174 */
+#define DA9150_TBAT_T1_SHIFT                    0
+#define DA9150_TBAT_T1_MASK                     (0xff << 0)
+
+/* DA9150_PPR_THYST_B = 0x175 */
+#define DA9150_TBAT_T2_SHIFT                    0
+#define DA9150_TBAT_T2_MASK                     (0xff << 0)
+
+/* DA9150_PPR_THYST_C = 0x176 */
+#define DA9150_TBAT_T3_SHIFT                    0
+#define DA9150_TBAT_T3_MASK                     (0xff << 0)
+
+/* DA9150_PPR_THYST_D = 0x177 */
+#define DA9150_TBAT_T4_SHIFT                    0
+#define DA9150_TBAT_T4_MASK                     (0xff << 0)
+
+/* DA9150_PPR_THYST_E = 0x178 */
+#define DA9150_TBAT_T5_SHIFT                    0
+#define DA9150_TBAT_T5_MASK                     (0xff << 0)
+
+/* DA9150_PPR_THYST_F = 0x179 */
+#define DA9150_TBAT_H1_SHIFT                    0
+#define DA9150_TBAT_H1_MASK                     (0xff << 0)
+
+/* DA9150_PPR_THYST_G = 0x17A */
+#define DA9150_TBAT_H5_SHIFT                    0
+#define DA9150_TBAT_H5_MASK                     (0xff << 0)
+
+/* DA9150_PAGE_CON_3 = 0x180 */
+#define DA9150_PAGE_SHIFT                       0
+#define DA9150_PAGE_MASK                        (0x3f << 0)
+#define DA9150_WRITE_MODE_SHIFT                 6
+#define DA9150_WRITE_MODE_MASK                  BIT(6)
+#define DA9150_REVERT_SHIFT                     7
+#define DA9150_REVERT_MASK                      BIT(7)
+
+/* DA9150_PAGE_CON_4 = 0x200 */
+#define DA9150_PAGE_SHIFT                       0
+#define DA9150_PAGE_MASK                        (0x3f << 0)
+#define DA9150_WRITE_MODE_SHIFT                 6
+#define DA9150_WRITE_MODE_MASK                  BIT(6)
+#define DA9150_REVERT_SHIFT                     7
+#define DA9150_REVERT_MASK                      BIT(7)
+
+/* DA9150_PAGE_CON_5 = 0x280 */
+#define DA9150_PAGE_SHIFT                       0
+#define DA9150_PAGE_MASK                        (0x3f << 0)
+#define DA9150_WRITE_MODE_SHIFT                 6
+#define DA9150_WRITE_MODE_MASK                  BIT(6)
+#define DA9150_REVERT_SHIFT                     7
+#define DA9150_REVERT_MASK                      BIT(7)
+
+/* DA9150_PAGE_CON_6 = 0x300 */
+#define DA9150_PAGE_SHIFT                       0
+#define DA9150_PAGE_MASK                        (0x3f << 0)
+#define DA9150_WRITE_MODE_SHIFT                 6
+#define DA9150_WRITE_MODE_MASK                  BIT(6)
+#define DA9150_REVERT_SHIFT                     7
+#define DA9150_REVERT_MASK                      BIT(7)
+
+/* DA9150_COREBTLD_STAT_A = 0x302 */
+#define DA9150_BOOTLD_STAT_SHIFT                0
+#define DA9150_BOOTLD_STAT_MASK                 (0x03 << 0)
+#define DA9150_CORE_LOCKUP_SHIFT                2
+#define DA9150_CORE_LOCKUP_MASK                 BIT(2)
+
+/* DA9150_COREBTLD_CTRL_A = 0x303 */
+#define DA9150_CORE_RESET_SHIFT                 0
+#define DA9150_CORE_RESET_MASK                  BIT(0)
+#define DA9150_CORE_STOP_SHIFT                  1
+#define DA9150_CORE_STOP_MASK                   BIT(1)
+
+/* DA9150_CORE_CONFIG_A = 0x304 */
+#define DA9150_CORE_MEMMUX_SHIFT                0
+#define DA9150_CORE_MEMMUX_MASK                 (0x03 << 0)
+#define DA9150_WDT_AUTO_START_SHIFT             2
+#define DA9150_WDT_AUTO_START_MASK              BIT(2)
+#define DA9150_WDT_AUTO_LOCK_SHIFT              3
+#define DA9150_WDT_AUTO_LOCK_MASK               BIT(3)
+#define DA9150_WDT_HLT_NO_CLK_SHIFT             4
+#define DA9150_WDT_HLT_NO_CLK_MASK              BIT(4)
+
+/* DA9150_CORE_CONFIG_C = 0x305 */
+#define DA9150_CORE_SW_SIZE_SHIFT               0
+#define DA9150_CORE_SW_SIZE_MASK                (0xff << 0)
+
+/* DA9150_CORE_CONFIG_B = 0x306 */
+#define DA9150_BOOTLD_EN_SHIFT                  0
+#define DA9150_BOOTLD_EN_MASK                   BIT(0)
+#define DA9150_CORE_EN_SHIFT                    2
+#define DA9150_CORE_EN_MASK                     BIT(2)
+#define DA9150_CORE_SW_SRC_SHIFT                3
+#define DA9150_CORE_SW_SRC_MASK                 (0x07 << 3)
+#define DA9150_DEEP_SLEEP_EN_SHIFT              7
+#define DA9150_DEEP_SLEEP_EN_MASK               BIT(7)
+
+/* DA9150_CORE_CFG_DATA_A = 0x307 */
+#define DA9150_CORE_CFG_DT_A_SHIFT              0
+#define DA9150_CORE_CFG_DT_A_MASK               (0xff << 0)
+
+/* DA9150_CORE_CFG_DATA_B = 0x308 */
+#define DA9150_CORE_CFG_DT_B_SHIFT              0
+#define DA9150_CORE_CFG_DT_B_MASK               (0xff << 0)
+
+/* DA9150_CORE_CMD_A = 0x309 */
+#define DA9150_CORE_CMD_SHIFT                   0
+#define DA9150_CORE_CMD_MASK                    (0xff << 0)
+
+/* DA9150_CORE_DATA_A = 0x30A */
+#define DA9150_CORE_DATA_0_SHIFT                0
+#define DA9150_CORE_DATA_0_MASK                 (0xff << 0)
+
+/* DA9150_CORE_DATA_B = 0x30B */
+#define DA9150_CORE_DATA_1_SHIFT                0
+#define DA9150_CORE_DATA_1_MASK                 (0xff << 0)
+
+/* DA9150_CORE_DATA_C = 0x30C */
+#define DA9150_CORE_DATA_2_SHIFT                0
+#define DA9150_CORE_DATA_2_MASK                 (0xff << 0)
+
+/* DA9150_CORE_DATA_D = 0x30D */
+#define DA9150_CORE_DATA_3_SHIFT                0
+#define DA9150_CORE_DATA_3_MASK                 (0xff << 0)
+
+/* DA9150_CORE2WIRE_STAT_A = 0x310 */
+#define DA9150_FW_FWDL_ERR_SHIFT                7
+#define DA9150_FW_FWDL_ERR_MASK                 BIT(7)
+
+/* DA9150_CORE2WIRE_CTRL_A = 0x311 */
+#define DA9150_FW_FWDL_EN_SHIFT                 0
+#define DA9150_FW_FWDL_EN_MASK                  BIT(0)
+#define DA9150_FG_QIF_EN_SHIFT                  1
+#define DA9150_FG_QIF_EN_MASK                   BIT(1)
+#define DA9150_CORE_BASE_ADDR_SHIFT             4
+#define DA9150_CORE_BASE_ADDR_MASK              (0x0f << 4)
+
+/* DA9150_FW_CTRL_A = 0x312 */
+#define DA9150_FW_SEAL_SHIFT                    0
+#define DA9150_FW_SEAL_MASK                     (0xff << 0)
+
+/* DA9150_FW_CTRL_C = 0x313 */
+#define DA9150_FW_FWDL_CRC_SHIFT                0
+#define DA9150_FW_FWDL_CRC_MASK                 (0xff << 0)
+
+/* DA9150_FW_CTRL_D = 0x314 */
+#define DA9150_FW_FWDL_BASE_SHIFT               0
+#define DA9150_FW_FWDL_BASE_MASK                (0x0f << 0)
+
+/* DA9150_FG_CTRL_A = 0x315 */
+#define DA9150_FG_QIF_CODE_SHIFT                0
+#define DA9150_FG_QIF_CODE_MASK                 (0xff << 0)
+
+/* DA9150_FG_CTRL_B = 0x316 */
+#define DA9150_FG_QIF_VALUE_SHIFT               0
+#define DA9150_FG_QIF_VALUE_MASK                (0xff << 0)
+
+/* DA9150_FW_CTRL_E = 0x317 */
+#define DA9150_FW_FWDL_SEG_SHIFT                0
+#define DA9150_FW_FWDL_SEG_MASK                 (0xff << 0)
+
+/* DA9150_FW_CTRL_B = 0x318 */
+#define DA9150_FW_FWDL_VALUE_SHIFT              0
+#define DA9150_FW_FWDL_VALUE_MASK               (0xff << 0)
+
+/* DA9150_GPADC_CMAN = 0x320 */
+#define DA9150_GPADC_CEN_SHIFT                  0
+#define DA9150_GPADC_CEN_MASK                   BIT(0)
+#define DA9150_GPADC_CMUX_SHIFT                 1
+#define DA9150_GPADC_CMUX_MASK                  (0x1f << 1)
+
+/* DA9150_GPADC_CRES_A = 0x322 */
+#define DA9150_GPADC_CRES_H_SHIFT               0
+#define DA9150_GPADC_CRES_H_MASK                (0xff << 0)
+
+/* DA9150_GPADC_CRES_B = 0x323 */
+#define DA9150_GPADC_CRUN_SHIFT                 0
+#define DA9150_GPADC_CRUN_MASK                  BIT(0)
+#define DA9150_GPADC_CRES_L_SHIFT               6
+#define DA9150_GPADC_CRES_L_MASK                (0x03 << 6)
+
+/* DA9150_CC_CFG_A = 0x328 */
+#define DA9150_CC_EN_SHIFT                      0
+#define DA9150_CC_EN_MASK                       BIT(0)
+#define DA9150_CC_TIMEBASE_SHIFT                1
+#define DA9150_CC_TIMEBASE_MASK                 (0x03 << 1)
+#define DA9150_CC_CFG_SHIFT                     5
+#define DA9150_CC_CFG_MASK                      (0x03 << 5)
+#define DA9150_CC_ENDLESS_MODE_SHIFT            7
+#define DA9150_CC_ENDLESS_MODE_MASK             BIT(7)
+
+/* DA9150_CC_CFG_B = 0x329 */
+#define DA9150_CC_OPT_SHIFT                     0
+#define DA9150_CC_OPT_MASK                      (0x03 << 0)
+#define DA9150_CC_PREAMP_SHIFT                  2
+#define DA9150_CC_PREAMP_MASK                   (0x03 << 2)
+
+/* DA9150_CC_ICHG_RES_A = 0x32A */
+#define DA9150_CC_ICHG_RES_H_SHIFT              0
+#define DA9150_CC_ICHG_RES_H_MASK               (0xff << 0)
+
+/* DA9150_CC_ICHG_RES_B = 0x32B */
+#define DA9150_CC_ICHG_RES_L_SHIFT              3
+#define DA9150_CC_ICHG_RES_L_MASK               (0x1f << 3)
+
+/* DA9150_CC_IAVG_RES_A = 0x32C */
+#define DA9150_CC_IAVG_RES_H_SHIFT              0
+#define DA9150_CC_IAVG_RES_H_MASK               (0xff << 0)
+
+/* DA9150_CC_IAVG_RES_B = 0x32D */
+#define DA9150_CC_IAVG_RES_L_SHIFT              0
+#define DA9150_CC_IAVG_RES_L_MASK               (0xff << 0)
+
+/* DA9150_TAUX_CTRL_A = 0x330 */
+#define DA9150_TAUX_EN_SHIFT                    0
+#define DA9150_TAUX_EN_MASK                     BIT(0)
+#define DA9150_TAUX_MOD_SHIFT                   1
+#define DA9150_TAUX_MOD_MASK                    BIT(1)
+#define DA9150_TAUX_UPDATE_SHIFT                2
+#define DA9150_TAUX_UPDATE_MASK                 BIT(2)
+
+/* DA9150_TAUX_RELOAD_H = 0x332 */
+#define DA9150_TAUX_RLD_H_SHIFT                 0
+#define DA9150_TAUX_RLD_H_MASK                  (0xff << 0)
+
+/* DA9150_TAUX_RELOAD_L = 0x333 */
+#define DA9150_TAUX_RLD_L_SHIFT                 3
+#define DA9150_TAUX_RLD_L_MASK                  (0x1f << 3)
+
+/* DA9150_TAUX_VALUE_H = 0x334 */
+#define DA9150_TAUX_VAL_H_SHIFT                 0
+#define DA9150_TAUX_VAL_H_MASK                  (0xff << 0)
+
+/* DA9150_TAUX_VALUE_L = 0x335 */
+#define DA9150_TAUX_VAL_L_SHIFT                 3
+#define DA9150_TAUX_VAL_L_MASK                  (0x1f << 3)
+
+/* DA9150_AUX_DATA_0 = 0x338 */
+#define DA9150_AUX_DAT_0_SHIFT                  0
+#define DA9150_AUX_DAT_0_MASK                   (0xff << 0)
+
+/* DA9150_AUX_DATA_1 = 0x339 */
+#define DA9150_AUX_DAT_1_SHIFT                  0
+#define DA9150_AUX_DAT_1_MASK                   (0xff << 0)
+
+/* DA9150_AUX_DATA_2 = 0x33A */
+#define DA9150_AUX_DAT_2_SHIFT                  0
+#define DA9150_AUX_DAT_2_MASK                   (0xff << 0)
+
+/* DA9150_AUX_DATA_3 = 0x33B */
+#define DA9150_AUX_DAT_3_SHIFT                  0
+#define DA9150_AUX_DAT_3_MASK                   (0xff << 0)
+
+/* DA9150_BIF_CTRL = 0x340 */
+#define DA9150_BIF_ISRC_EN_SHIFT                0
+#define DA9150_BIF_ISRC_EN_MASK                 BIT(0)
+
+/* DA9150_TBAT_CTRL_A = 0x342 */
+#define DA9150_TBAT_EN_SHIFT                    0
+#define DA9150_TBAT_EN_MASK                     BIT(0)
+#define DA9150_TBAT_SW1_SHIFT                   1
+#define DA9150_TBAT_SW1_MASK                    BIT(1)
+#define DA9150_TBAT_SW2_SHIFT                   2
+#define DA9150_TBAT_SW2_MASK                    BIT(2)
+
+/* DA9150_TBAT_CTRL_B = 0x343 */
+#define DA9150_TBAT_SW_FRC_SHIFT                0
+#define DA9150_TBAT_SW_FRC_MASK                 BIT(0)
+#define DA9150_TBAT_STAT_SW1_SHIFT              1
+#define DA9150_TBAT_STAT_SW1_MASK               BIT(1)
+#define DA9150_TBAT_STAT_SW2_SHIFT              2
+#define DA9150_TBAT_STAT_SW2_MASK               BIT(2)
+#define DA9150_TBAT_HIGH_CURR_SHIFT             3
+#define DA9150_TBAT_HIGH_CURR_MASK              BIT(3)
+
+/* DA9150_TBAT_RES_A = 0x344 */
+#define DA9150_TBAT_RES_H_SHIFT                 0
+#define DA9150_TBAT_RES_H_MASK                  (0xff << 0)
+
+/* DA9150_TBAT_RES_B = 0x345 */
+#define DA9150_TBAT_RES_DIS_SHIFT               0
+#define DA9150_TBAT_RES_DIS_MASK                BIT(0)
+#define DA9150_TBAT_RES_L_SHIFT                 6
+#define DA9150_TBAT_RES_L_MASK                  (0x03 << 6)
+
+#endif /* __DA9150_REGISTERS_H */
diff --git a/include/linux/mfd/max77686-private.h b/include/linux/mfd/max77686-private.h
index 960b92ad450d..f5043490d67c 100644
--- a/include/linux/mfd/max77686-private.h
+++ b/include/linux/mfd/max77686-private.h
@@ -447,7 +447,6 @@ struct max77686_dev {
         struct regmap_irq_chip_data *rtc_irq_data;
 
         int irq;
-        bool wakeup;
         struct mutex irqlock;
         int irq_masks_cur[MAX77686_IRQ_GROUP_NR];
         int irq_masks_cache[MAX77686_IRQ_GROUP_NR];
diff --git a/include/linux/mfd/max77686.h b/include/linux/mfd/max77686.h
index 553f7d09258a..bb995ab9a575 100644
--- a/include/linux/mfd/max77686.h
+++ b/include/linux/mfd/max77686.h
@@ -119,12 +119,6 @@ enum max77802_regulators {
         MAX77802_REG_MAX,
 };
 
-struct max77686_regulator_data {
-        int id;
-        struct regulator_init_data *initdata;
-        struct device_node *of_node;
-};
-
 enum max77686_opmode {
         MAX77686_OPMODE_NORMAL,
         MAX77686_OPMODE_LP,
@@ -136,26 +130,4 @@ struct max77686_opmode_data {
         int mode;
 };
 
-struct max77686_platform_data {
-        int ono;
-        int wakeup;
-
-        /* ---- PMIC ---- */
-        struct max77686_regulator_data *regulators;
-        int num_regulators;
-
-        struct max77686_opmode_data *opmode_data;
-
-        /*
-         * GPIO-DVS feature is not enabled with the current version of
-         * MAX77686 driver. Buck2/3/4_voltages[0] is used as the default
-         * voltage at probe. DVS/SELB gpios are set as OUTPUT-LOW.
-         */
-        int buck234_gpio_dvs[3]; /* GPIO of [0]DVS1, [1]DVS2, [2]DVS3 */
-        int buck234_gpio_selb[3]; /* [0]SELB2, [1]SELB3, [2]SELB4 */
-        unsigned int buck2_voltage[8]; /* buckx_voltage in uV */
-        unsigned int buck3_voltage[8];
-        unsigned int buck4_voltage[8];
-};
-
 #endif /* __LINUX_MFD_MAX77686_H */
diff --git a/include/linux/mfd/qcom_rpm.h b/include/linux/mfd/qcom_rpm.h
new file mode 100644
index 000000000000..742ebf1b76ca
--- /dev/null
+++ b/include/linux/mfd/qcom_rpm.h
@@ -0,0 +1,13 @@
+#ifndef __QCOM_RPM_H__
+#define __QCOM_RPM_H__
+
+#include <linux/types.h>
+
+struct qcom_rpm;
+
+#define QCOM_RPM_ACTIVE_STATE   0
+#define QCOM_RPM_SLEEP_STATE    1
+
+int qcom_rpm_write(struct qcom_rpm *rpm, int state, int resource, u32 *buf, size_t count);
+
+#endif
diff --git a/include/linux/mfd/rt5033-private.h b/include/linux/mfd/rt5033-private.h
new file mode 100644
index 000000000000..1b63fc2f42d1
--- /dev/null
+++ b/include/linux/mfd/rt5033-private.h
@@ -0,0 +1,260 @@
+/*
+ * MFD core driver for Richtek RT5033
+ *
+ * Copyright (C) 2014 Samsung Electronics, Co., Ltd.
+ * Author: Beomho Seo <beomho.seo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published bythe Free Software Foundation.
+ */
+
+#ifndef __RT5033_PRIVATE_H__
+#define __RT5033_PRIVATE_H__
+
+enum rt5033_reg {
+        RT5033_REG_CHG_STAT             = 0x00,
+        RT5033_REG_CHG_CTRL1            = 0x01,
+        RT5033_REG_CHG_CTRL2            = 0x02,
+        RT5033_REG_DEVICE_ID            = 0x03,
+        RT5033_REG_CHG_CTRL3            = 0x04,
+        RT5033_REG_CHG_CTRL4            = 0x05,
+        RT5033_REG_CHG_CTRL5            = 0x06,
+        RT5033_REG_RT_CTRL0             = 0x07,
+        RT5033_REG_CHG_RESET            = 0x08,
+        /* Reserved 0x09~0x18 */
+        RT5033_REG_RT_CTRL1             = 0x19,
+        /* Reserved 0x1A~0x20 */
+        RT5033_REG_FLED_FUNCTION1       = 0x21,
+        RT5033_REG_FLED_FUNCTION2       = 0x22,
+        RT5033_REG_FLED_STROBE_CTRL1    = 0x23,
+        RT5033_REG_FLED_STROBE_CTRL2    = 0x24,
+        RT5033_REG_FLED_CTRL1           = 0x25,
+        RT5033_REG_FLED_CTRL2           = 0x26,
+        RT5033_REG_FLED_CTRL3           = 0x27,
+        RT5033_REG_FLED_CTRL4           = 0x28,
+        RT5033_REG_FLED_CTRL5           = 0x29,
+        /* Reserved 0x2A~0x40 */
+        RT5033_REG_CTRL                 = 0x41,
+        RT5033_REG_BUCK_CTRL            = 0x42,
+        RT5033_REG_LDO_CTRL             = 0x43,
+        /* Reserved 0x44~0x46 */
+        RT5033_REG_MANUAL_RESET_CTRL    = 0x47,
+        /* Reserved 0x48~0x5F */
+        RT5033_REG_CHG_IRQ1             = 0x60,
+        RT5033_REG_CHG_IRQ2             = 0x61,
+        RT5033_REG_CHG_IRQ3             = 0x62,
+        RT5033_REG_CHG_IRQ1_CTRL        = 0x63,
+        RT5033_REG_CHG_IRQ2_CTRL        = 0x64,
+        RT5033_REG_CHG_IRQ3_CTRL        = 0x65,
+        RT5033_REG_LED_IRQ_STAT         = 0x66,
+        RT5033_REG_LED_IRQ_CTRL         = 0x67,
+        RT5033_REG_PMIC_IRQ_STAT        = 0x68,
+        RT5033_REG_PMIC_IRQ_CTRL        = 0x69,
+        RT5033_REG_SHDN_CTRL            = 0x6A,
+        RT5033_REG_OFF_EVENT            = 0x6B,
+
+        RT5033_REG_END,
+};
+
+/* RT5033 Charger state register */
+#define RT5033_CHG_STAT_MASK            0x20
+#define RT5033_CHG_STAT_DISCHARGING     0x00
+#define RT5033_CHG_STAT_FULL            0x10
+#define RT5033_CHG_STAT_CHARGING        0x20
+#define RT5033_CHG_STAT_NOT_CHARGING    0x30
+#define RT5033_CHG_STAT_TYPE_MASK       0x60
+#define RT5033_CHG_STAT_TYPE_PRE        0x20
+#define RT5033_CHG_STAT_TYPE_FAST       0x60
+
+/* RT5033 CHGCTRL1 register */
+#define RT5033_CHGCTRL1_IAICR_MASK      0xe0
+#define RT5033_CHGCTRL1_MODE_MASK       0x01
+
+/* RT5033 CHGCTRL2 register */
+#define RT5033_CHGCTRL2_CV_MASK         0xfc
+
+/* RT5033 CHGCTRL3 register */
+#define RT5033_CHGCTRL3_CFO_EN_MASK     0x40
+#define RT5033_CHGCTRL3_TIMER_MASK      0x38
+#define RT5033_CHGCTRL3_TIMER_EN_MASK   0x01
+
+/* RT5033 CHGCTRL4 register */
+#define RT5033_CHGCTRL4_EOC_MASK        0x07
+#define RT5033_CHGCTRL4_IPREC_MASK      0x18
+
+/* RT5033 CHGCTRL5 register */
+#define RT5033_CHGCTRL5_VPREC_MASK      0x0f
+#define RT5033_CHGCTRL5_ICHG_MASK       0xf0
+#define RT5033_CHGCTRL5_ICHG_SHIFT      0x04
+#define RT5033_CHG_MAX_CURRENT          0x0d
+
+/* RT5033 RT CTRL1 register */
+#define RT5033_RT_CTRL1_UUG_MASK        0x02
+#define RT5033_RT_HZ_MASK               0x01
+
+/* RT5033 control register */
+#define RT5033_CTRL_FCCM_BUCK_MASK              0x00
+#define RT5033_CTRL_BUCKOMS_MASK                0x01
+#define RT5033_CTRL_LDOOMS_MASK                 0x02
+#define RT5033_CTRL_SLDOOMS_MASK                0x03
+#define RT5033_CTRL_EN_BUCK_MASK                0x04
+#define RT5033_CTRL_EN_LDO_MASK                 0x05
+#define RT5033_CTRL_EN_SAFE_LDO_MASK            0x06
+#define RT5033_CTRL_LDO_SLEEP_MASK              0x07
+
+/* RT5033 BUCK control register */
+#define RT5033_BUCK_CTRL_MASK                   0x1f
+
+/* RT5033 LDO control register */
+#define RT5033_LDO_CTRL_MASK                    0x1f
+
+/* RT5033 charger property - model, manufacturer */
+
+#define RT5033_CHARGER_MODEL    "RT5033WSC Charger"
+#define RT5033_MANUFACTURER     "Richtek Technology Corporation"
+
+/*
+ * RT5033 charger fast-charge current lmits (as in CHGCTRL1 register),
+ * AICR mode limits the input current for example,
+ * the AIRC 100 mode limits the input current to 100 mA.
+ */
+#define RT5033_AICR_100_MODE                    0x20
+#define RT5033_AICR_500_MODE                    0x40
+#define RT5033_AICR_700_MODE                    0x60
+#define RT5033_AICR_900_MODE                    0x80
+#define RT5033_AICR_1500_MODE                   0xc0
+#define RT5033_AICR_2000_MODE                   0xe0
+#define RT5033_AICR_MODE_MASK                   0xe0
+
+/* RT5033 use internal timer need to set time */
+#define RT5033_FAST_CHARGE_TIMER4               0x00
+#define RT5033_FAST_CHARGE_TIMER6               0x01
+#define RT5033_FAST_CHARGE_TIMER8               0x02
+#define RT5033_FAST_CHARGE_TIMER9               0x03
+#define RT5033_FAST_CHARGE_TIMER12              0x04
+#define RT5033_FAST_CHARGE_TIMER14              0x05
+#define RT5033_FAST_CHARGE_TIMER16              0x06
+
+#define RT5033_INT_TIMER_ENABLE                 0x01
+
+/* RT5033 charger termination enable mask */
+#define RT5033_TE_ENABLE_MASK                   0x08
+
+/*
+ * RT5033 charger opa mode. RT50300 have two opa mode charger mode
+ * and boost mode for OTG
+ */
+
+#define RT5033_CHARGER_MODE                     0x00
+#define RT5033_BOOST_MODE                       0x01
+
+/* RT5033 charger termination enable */
+#define RT5033_TE_ENABLE                        0x08
+
+/* RT5033 charger CFO enable */
+#define RT5033_CFO_ENABLE                       0x40
+
+/* RT5033 charger constant charge voltage (as in CHGCTRL2 register), uV */
+#define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MIN  3650000U
+#define RT5033_CHARGER_CONST_VOLTAGE_STEP_NUM   25000U
+#define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MAX  4400000U
+
+/* RT5033 charger pre-charge current limits (as in CHGCTRL4 register), uA */
+#define RT5033_CHARGER_PRE_CURRENT_LIMIT_MIN    350000U
+#define RT5033_CHARGER_PRE_CURRENT_STEP_NUM     100000U
+#define RT5033_CHARGER_PRE_CURRENT_LIMIT_MAX    650000U
+
+/* RT5033 charger fast-charge current (as in CHGCTRL5 register), uA */
+#define RT5033_CHARGER_FAST_CURRENT_MIN         700000U
+#define RT5033_CHARGER_FAST_CURRENT_STEP_NUM    100000U
+#define RT5033_CHARGER_FAST_CURRENT_MAX         2000000U
+
+/*
+ * RT5033 charger const-charge end of charger current (
+ * as in CHGCTRL4 register), uA
+ */
+#define RT5033_CHARGER_EOC_MIN                  150000U
+#define RT5033_CHARGER_EOC_REF                  300000U
+#define RT5033_CHARGER_EOC_STEP_NUM1            50000U
+#define RT5033_CHARGER_EOC_STEP_NUM2            100000U
+#define RT5033_CHARGER_EOC_MAX                  600000U
+
+/*
+ * RT5033 charger pre-charge threshold volt limits
+ * (as in CHGCTRL5 register), uV
+ */
+
+#define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MIN  2300000U
+#define RT5033_CHARGER_PRE_THRESHOLD_STEP_NUM   100000U
+#define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MAX  3800000U
+
+/*
+ * RT5033 charger enable UUG, If UUG enable MOS auto control by H/W charger
+ * circuit.
+ */
+#define RT5033_CHARGER_UUG_ENABLE               0x02
+
+/* RT5033 charger High impedance mode */
+#define RT5033_CHARGER_HZ_DISABLE               0x00
+#define RT5033_CHARGER_HZ_ENABLE                0x01
+
+/* RT5033 regulator BUCK output voltage uV */
+#define RT5033_REGULATOR_BUCK_VOLTAGE_MIN               1000000U
+#define RT5033_REGULATOR_BUCK_VOLTAGE_MAX               3000000U
+#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP              100000U
+#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP_NUM          32
+
+/* RT5033 regulator LDO output voltage uV */
+#define RT5033_REGULATOR_LDO_VOLTAGE_MIN                1200000U
+#define RT5033_REGULATOR_LDO_VOLTAGE_MAX                3000000U
+#define RT5033_REGULATOR_LDO_VOLTAGE_STEP               100000U
+#define RT5033_REGULATOR_LDO_VOLTAGE_STEP_NUM           32
+
+/* RT5033 regulator SAFE LDO output voltage uV */
+#define RT5033_REGULATOR_SAFE_LDO_VOLTAGE               4900000U
+
+enum rt5033_fuel_reg {
+        RT5033_FUEL_REG_OCV_H           = 0x00,
+        RT5033_FUEL_REG_OCV_L           = 0x01,
+        RT5033_FUEL_REG_VBAT_H          = 0x02,
+        RT5033_FUEL_REG_VBAT_L          = 0x03,
+        RT5033_FUEL_REG_SOC_H           = 0x04,
+        RT5033_FUEL_REG_SOC_L           = 0x05,
+        RT5033_FUEL_REG_CTRL_H          = 0x06,
+        RT5033_FUEL_REG_CTRL_L          = 0x07,
+        RT5033_FUEL_REG_CRATE           = 0x08,
+        RT5033_FUEL_REG_DEVICE_ID       = 0x09,
+        RT5033_FUEL_REG_AVG_VOLT_H      = 0x0A,
+        RT5033_FUEL_REG_AVG_VOLT_L      = 0x0B,
+        RT5033_FUEL_REG_CONFIG_H        = 0x0C,
+        RT5033_FUEL_REG_CONFIG_L        = 0x0D,
+        /* Reserved 0x0E~0x0F */
+        RT5033_FUEL_REG_IRQ_CTRL        = 0x10,
+        RT5033_FUEL_REG_IRQ_FLAG        = 0x11,
+        RT5033_FUEL_VMIN                = 0x12,
+        RT5033_FUEL_SMIN                = 0x13,
+        /* Reserved 0x14~0x1F */
+        RT5033_FUEL_VGCOMP1             = 0x20,
+        RT5033_FUEL_VGCOMP2             = 0x21,
+        RT5033_FUEL_VGCOMP3             = 0x22,
+        RT5033_FUEL_VGCOMP4             = 0x23,
+        /* Reserved 0x24~0xFD */
+        RT5033_FUEL_MFA_H               = 0xFE,
+        RT5033_FUEL_MFA_L               = 0xFF,
+
+        RT5033_FUEL_REG_END,
+};
+
+/* RT5033 fuel gauge battery present property */
+#define RT5033_FUEL_BAT_PRESENT         0x02
+
+/* RT5033 PMIC interrupts */
+#define RT5033_PMIC_IRQ_BUCKOCP         2
+#define RT5033_PMIC_IRQ_BUCKLV          3
+#define RT5033_PMIC_IRQ_SAFELDOLV       4
+#define RT5033_PMIC_IRQ_LDOLV           5
+#define RT5033_PMIC_IRQ_OT              6
+#define RT5033_PMIC_IRQ_VDDA_UV         7
+
+#endif /* __RT5033_PRIVATE_H__ */
diff --git a/include/linux/mfd/rt5033.h b/include/linux/mfd/rt5033.h
new file mode 100644
index 000000000000..010cff49a98e
--- /dev/null
+++ b/include/linux/mfd/rt5033.h
@@ -0,0 +1,62 @@
+/*
+ * MFD core driver for the RT5033
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ * Author: Beomho Seo <beomho.seo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published bythe Free Software Foundation.
+ */
+
+#ifndef __RT5033_H__
+#define __RT5033_H__
+
+#include <linux/regulator/consumer.h>
+#include <linux/i2c.h>
+#include <linux/regmap.h>
+#include <linux/power_supply.h>
+
+/* RT5033 regulator IDs */
+enum rt5033_regulators {
+        RT5033_BUCK = 0,
+        RT5033_LDO,
+        RT5033_SAFE_LDO,
+
+        RT5033_REGULATOR_NUM,
+};
+
+struct rt5033_dev {
+        struct device *dev;
+
+        struct regmap *regmap;
+        struct regmap_irq_chip_data *irq_data;
+        int irq;
+        bool wakeup;
+};
+
+struct rt5033_battery {
+        struct i2c_client       *client;
+        struct rt5033_dev       *rt5033;
+        struct regmap           *regmap;
+        struct power_supply     psy;
+};
+
+/* RT5033 charger platform data */
+struct rt5033_charger_data {
+        unsigned int pre_uamp;
+        unsigned int pre_uvolt;
+        unsigned int const_uvolt;
+        unsigned int eoc_uamp;
+        unsigned int fast_uamp;
+};
+
+struct rt5033_charger {
+        struct device           *dev;
+        struct rt5033_dev       *rt5033;
+        struct power_supply     psy;
+
+        struct rt5033_charger_data      *chg;
+};
+
+#endif /* __RT5033_H__ */
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h
index 2bbc62aa818a..551f85456c11 100644
--- a/include/linux/mlx4/qp.h
+++ b/include/linux/mlx4/qp.h
@@ -427,7 +427,7 @@ struct mlx4_wqe_inline_seg {
 
 enum mlx4_update_qp_attr {
         MLX4_UPDATE_QP_SMAC             = 1 << 0,
-        MLX4_UPDATE_QP_VSD              = 1 << 2,
+        MLX4_UPDATE_QP_VSD              = 1 << 1,
         MLX4_UPDATE_QP_SUPPORTED_ATTRS  = (1 << 2) - 1
 };
 
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 3301c4c289d6..f17fa75809aa 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -227,6 +227,7 @@ struct mtd_info {
         int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs);
         int (*_suspend) (struct mtd_info *mtd);
         void (*_resume) (struct mtd_info *mtd);
+        void (*_reboot) (struct mtd_info *mtd);
         /*
          * If the driver is something smart, like UBI, it may need to maintain
          * its own reference counting. The below functions are only for driver.
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 63aeccf9ddc8..4720b86ee73d 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -56,6 +56,10 @@
 /* Used for Spansion flashes only. */
 #define SPINOR_OP_BRWR          0x17    /* Bank register write */
 
+/* Used for Micron flashes only. */
+#define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */
+#define SPINOR_OP_WD_EVCR      0x61    /* Write EVCR register */
+
 /* Status Register bits. */
 #define SR_WIP                  1       /* Write in progress */
 #define SR_WEL                  2       /* Write enable latch */
@@ -67,6 +71,9 @@
 
 #define SR_QUAD_EN_MX           0x40    /* Macronix Quad I/O */
 
+/* Enhanced Volatile Configuration Register bits */
+#define EVCR_QUAD_EN_MICRON    0x80    /* Micron Quad I/O */
+
 /* Flag Status Register bits */
 #define FSR_READY               0x80
 
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index 2007f3b44d05..625c8d71511b 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -2341,6 +2341,7 @@ struct gro_remcsum {
 
 static inline void skb_gro_remcsum_init(struct gro_remcsum *grc)
 {
+        grc->offset = 0;
         grc->delta = 0;
 }
 
diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h
index 6d627b92df53..2f77e0c651c8 100644
--- a/include/linux/nfs_fs.h
+++ b/include/linux/nfs_fs.h
@@ -180,7 +180,6 @@ struct nfs_inode {
         /* NFSv4 state */
         struct list_head        open_states;
         struct nfs_delegation __rcu *delegation;
-        fmode_t                  delegation_state;
         struct rw_semaphore     rwsem;
 
         /* pNFS layout information */
diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h
index 38d96ba935c2..4cb3eaa89cf7 100644
--- a/include/linux/nfs_xdr.h
+++ b/include/linux/nfs_xdr.h
@@ -1167,8 +1167,15 @@ struct nfs41_impl_id {
         struct nfstime4                 date;
 };
 
+struct nfs41_bind_conn_to_session_args {
+        struct nfs_client               *client;
+        struct nfs4_sessionid           sessionid;
+        u32                             dir;
+        bool                            use_conn_in_rdma_mode;
+};
+
 struct nfs41_bind_conn_to_session_res {
-        struct nfs4_session             *session;
+        struct nfs4_sessionid           sessionid;
         u32                             dir;
         bool                            use_conn_in_rdma_mode;
 };
@@ -1185,6 +1192,8 @@ struct nfs41_exchange_id_res {
 
 struct nfs41_create_session_args {
         struct nfs_client              *client;
+        u64                             clientid;
+        uint32_t                        seqid;
         uint32_t                        flags;
         uint32_t                        cb_program;
         struct nfs4_channel_attrs       fc_attrs;       /* Fore Channel */
@@ -1192,7 +1201,11 @@ struct nfs41_create_session_args {
 };
 
 struct nfs41_create_session_res {
-        struct nfs_client              *client;
+        struct nfs4_sessionid           sessionid;
+        uint32_t                        seqid;
+        uint32_t                        flags;
+        struct nfs4_channel_attrs       fc_attrs;       /* Fore Channel */
+        struct nfs4_channel_attrs       bc_attrs;       /* Back Channel */
 };
 
 struct nfs41_reclaim_complete_args {
@@ -1351,7 +1364,7 @@ struct nfs_commit_completion_ops {
 };
 
 struct nfs_commit_info {
-        spinlock_t                      *lock;
+        spinlock_t                      *lock;  /* inode->i_lock */
         struct nfs_mds_commit_info      *mds;
         struct pnfs_ds_commit_info      *ds;
         struct nfs_direct_req           *dreq;  /* O_DIRECT request */
diff --git a/include/linux/nvme.h b/include/linux/nvme.h
index 19a5d4b23209..0adad4a5419b 100644
--- a/include/linux/nvme.h
+++ b/include/linux/nvme.h
@@ -17,7 +17,6 @@
 
 #include <uapi/linux/nvme.h>
 #include <linux/pci.h>
-#include <linux/miscdevice.h>
 #include <linux/kref.h>
 #include <linux/blk-mq.h>
 
@@ -62,8 +61,6 @@ enum {
         NVME_CSTS_SHST_MASK     = 3 << 2,
 };
 
-#define NVME_VS(major, minor)   (major << 16 | minor)
-
 extern unsigned char nvme_io_timeout;
 #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
 
@@ -91,9 +88,10 @@ struct nvme_dev {
         struct nvme_bar __iomem *bar;
         struct list_head namespaces;
         struct kref kref;
-        struct miscdevice miscdev;
+        struct device *device;
         work_func_t reset_workfn;
         struct work_struct reset_work;
+        struct work_struct probe_work;
         char name[12];
         char serial[20];
         char model[40];
@@ -105,7 +103,6 @@ struct nvme_dev {
         u16 abort_limit;
         u8 event_limit;
         u8 vwc;
-        u8 initialized;
 };
 
 /*
@@ -121,6 +118,7 @@ struct nvme_ns {
         unsigned ns_id;
         int lba_shift;
         int ms;
+        int pi_type;
         u64 mode_select_num_blocks;
         u32 mode_select_block_len;
 };
@@ -138,6 +136,7 @@ struct nvme_iod {
         int nents;              /* Used in scatterlist */
         int length;             /* Of data, in bytes */
         dma_addr_t first_dma;
+        struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */
         struct scatterlist sg[0];
 };
 
diff --git a/include/linux/platform_data/bfin_rotary.h b/include/linux/platform_data/bfin_rotary.h
new file mode 100644
index 000000000000..98829370fee2
--- /dev/null
+++ b/include/linux/platform_data/bfin_rotary.h
@@ -0,0 +1,117 @@
+/*
+ * board initialization should put one of these structures into platform_data
+ * and place the bfin-rotary onto platform_bus named "bfin-rotary".
+ *
+ * Copyright 2008-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _BFIN_ROTARY_H
+#define _BFIN_ROTARY_H
+
+/* mode bitmasks */
+#define ROT_QUAD_ENC    CNTMODE_QUADENC /* quadrature/grey code encoder mode */
+#define ROT_BIN_ENC     CNTMODE_BINENC  /* binary encoder mode */
+#define ROT_UD_CNT      CNTMODE_UDCNT   /* rotary counter mode */
+#define ROT_DIR_CNT     CNTMODE_DIRCNT  /* direction counter mode */
+
+#define ROT_DEBE        DEBE            /* Debounce Enable */
+
+#define ROT_CDGINV      CDGINV          /* CDG Pin Polarity Invert */
+#define ROT_CUDINV      CUDINV          /* CUD Pin Polarity Invert */
+#define ROT_CZMINV      CZMINV          /* CZM Pin Polarity Invert */
+
+struct bfin_rotary_platform_data {
+        /* set rotary UP KEY_### or BTN_### in case you prefer
+         * bfin-rotary to send EV_KEY otherwise set 0
+         */
+        unsigned int rotary_up_key;
+        /* set rotary DOWN KEY_### or BTN_### in case you prefer
+         * bfin-rotary to send EV_KEY otherwise set 0
+         */
+        unsigned int rotary_down_key;
+        /* set rotary BUTTON KEY_### or BTN_### */
+        unsigned int rotary_button_key;
+        /* set rotary Relative Axis REL_### in case you prefer
+         * bfin-rotary to send EV_REL otherwise set 0
+         */
+        unsigned int rotary_rel_code;
+        unsigned short debounce;        /* 0..17 */
+        unsigned short mode;
+        unsigned short pm_wakeup;
+        unsigned short *pin_list;
+};
+
+/* CNT_CONFIG bitmasks */
+#define CNTE            (1 << 0)        /* Counter Enable */
+#define DEBE            (1 << 1)        /* Debounce Enable */
+#define CDGINV          (1 << 4)        /* CDG Pin Polarity Invert */
+#define CUDINV          (1 << 5)        /* CUD Pin Polarity Invert */
+#define CZMINV          (1 << 6)        /* CZM Pin Polarity Invert */
+#define CNTMODE_SHIFT   8
+#define CNTMODE         (0x7 << CNTMODE_SHIFT)  /* Counter Operating Mode */
+#define ZMZC            (1 << 1)        /* CZM Zeroes Counter Enable */
+#define BNDMODE_SHIFT   12
+#define BNDMODE         (0x3 << BNDMODE_SHIFT)  /* Boundary register Mode */
+#define INPDIS          (1 << 15)       /* CUG and CDG Input Disable */
+
+#define CNTMODE_QUADENC (0 << CNTMODE_SHIFT)    /* quadrature encoder mode */
+#define CNTMODE_BINENC  (1 << CNTMODE_SHIFT)    /* binary encoder mode */
+#define CNTMODE_UDCNT   (2 << CNTMODE_SHIFT)    /* up/down counter mode */
+#define CNTMODE_DIRCNT  (4 << CNTMODE_SHIFT)    /* direction counter mode */
+#define CNTMODE_DIRTMR  (5 << CNTMODE_SHIFT)    /* direction timer mode */
+
+#define BNDMODE_COMP    (0 << BNDMODE_SHIFT)    /* boundary compare mode */
+#define BNDMODE_ZERO    (1 << BNDMODE_SHIFT)    /* boundary compare and zero mode */
+#define BNDMODE_CAPT    (2 << BNDMODE_SHIFT)    /* boundary capture mode */
+#define BNDMODE_AEXT    (3 << BNDMODE_SHIFT)    /* boundary auto-extend mode */
+
+/* CNT_IMASK bitmasks */
+#define ICIE            (1 << 0)        /* Illegal Gray/Binary Code Interrupt Enable */
+#define UCIE            (1 << 1)        /* Up count Interrupt Enable */
+#define DCIE            (1 << 2)        /* Down count Interrupt Enable */
+#define MINCIE          (1 << 3)        /* Min Count Interrupt Enable */
+#define MAXCIE          (1 << 4)        /* Max Count Interrupt Enable */
+#define COV31IE         (1 << 5)        /* Bit 31 Overflow Interrupt Enable */
+#define COV15IE         (1 << 6)        /* Bit 15 Overflow Interrupt Enable */
+#define CZEROIE         (1 << 7)        /* Count to Zero Interrupt Enable */
+#define CZMIE           (1 << 8)        /* CZM Pin Interrupt Enable */
+#define CZMEIE          (1 << 9)        /* CZM Error Interrupt Enable */
+#define CZMZIE          (1 << 10)       /* CZM Zeroes Counter Interrupt Enable */
+
+/* CNT_STATUS bitmasks */
+#define ICII            (1 << 0)        /* Illegal Gray/Binary Code Interrupt Identifier */
+#define UCII            (1 << 1)        /* Up count Interrupt Identifier */
+#define DCII            (1 << 2)        /* Down count Interrupt Identifier */
+#define MINCII          (1 << 3)        /* Min Count Interrupt Identifier */
+#define MAXCII          (1 << 4)        /* Max Count Interrupt Identifier */
+#define COV31II         (1 << 5)        /* Bit 31 Overflow Interrupt Identifier */
+#define COV15II         (1 << 6)        /* Bit 15 Overflow Interrupt Identifier */
+#define CZEROII         (1 << 7)        /* Count to Zero Interrupt Identifier */
+#define CZMII           (1 << 8)        /* CZM Pin Interrupt Identifier */
+#define CZMEII          (1 << 9)        /* CZM Error Interrupt Identifier */
+#define CZMZII          (1 << 10)       /* CZM Zeroes Counter Interrupt Identifier */
+
+/* CNT_COMMAND bitmasks */
+#define W1LCNT          0xf             /* Load Counter Register */
+#define W1LMIN          0xf0            /* Load Min Register */
+#define W1LMAX          0xf00           /* Load Max Register */
+#define W1ZMONCE        (1 << 12)       /* Enable CZM Clear Counter Once */
+
+#define W1LCNT_ZERO     (1 << 0)        /* write 1 to load CNT_COUNTER with zero */
+#define W1LCNT_MIN      (1 << 2)        /* write 1 to load CNT_COUNTER from CNT_MIN */
+#define W1LCNT_MAX      (1 << 3)        /* write 1 to load CNT_COUNTER from CNT_MAX */
+
+#define W1LMIN_ZERO     (1 << 4)        /* write 1 to load CNT_MIN with zero */
+#define W1LMIN_CNT      (1 << 5)        /* write 1 to load CNT_MIN from CNT_COUNTER */
+#define W1LMIN_MAX      (1 << 7)        /* write 1 to load CNT_MIN from CNT_MAX */
+
+#define W1LMAX_ZERO     (1 << 8)        /* write 1 to load CNT_MAX with zero */
+#define W1LMAX_CNT      (1 << 9)        /* write 1 to load CNT_MAX from CNT_COUNTER */
+#define W1LMAX_MIN      (1 << 10)       /* write 1 to load CNT_MAX from CNT_MIN */
+
+/* CNT_DEBOUNCE bitmasks */
+#define DPRESCALE       0xf             /* Load Counter Register */
+
+#endif
diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h
index d8155c005242..87ac14c584f2 100644
--- a/include/linux/platform_data/dma-dw.h
+++ b/include/linux/platform_data/dma-dw.h
@@ -13,10 +13,12 @@
 
 #include <linux/device.h>
 
+#define DW_DMA_MAX_NR_MASTERS   4
+
 /**
  * struct dw_dma_slave - Controller-specific information about a slave
  *
- * @dma_dev: required DMA master device. Depricated.
+ * @dma_dev:    required DMA master device
  * @src_id:     src request line
  * @dst_id:     dst request line
  * @src_master: src master for transfers on allocated channel.
@@ -53,7 +55,7 @@ struct dw_dma_platform_data {
         unsigned char   chan_priority;
         unsigned short  block_size;
         unsigned char   nr_masters;
-        unsigned char   data_width[4];
+        unsigned char   data_width[DW_DMA_MAX_NR_MASTERS];
 };
 
 #endif /* _PLATFORM_DATA_DMA_DW_H */
diff --git a/include/linux/platform_data/dma-mmp_tdma.h b/include/linux/platform_data/dma-mmp_tdma.h
index 66574ea39f97..0c72886030ef 100644
--- a/include/linux/platform_data/dma-mmp_tdma.h
+++ b/include/linux/platform_data/dma-mmp_tdma.h
@@ -28,6 +28,13 @@ struct sram_platdata {
         int granularity;
 };
 
+#ifdef CONFIG_ARM
 extern struct gen_pool *sram_get_gpool(char *pool_name);
+#else
+static inline struct gen_pool *sram_get_gpool(char *pool_name)
+{
+        return NULL;
+}
+#endif
 
 #endif /* __DMA_MMP_TDMA_H */
diff --git a/include/linux/rhashtable.h b/include/linux/rhashtable.h
index 58851275fed9..d438eeb08bff 100644
--- a/include/linux/rhashtable.h
+++ b/include/linux/rhashtable.h
@@ -54,10 +54,11 @@ struct rhash_head {
  * @buckets: size * hash buckets
  */
 struct bucket_table {
-        size_t                          size;
-        unsigned int                    locks_mask;
-        spinlock_t                      *locks;
-        struct rhash_head __rcu         *buckets[];
+        size_t                  size;
+        unsigned int            locks_mask;
+        spinlock_t              *locks;
+
+        struct rhash_head __rcu *buckets[] ____cacheline_aligned_in_smp;
 };
 
 typedef u32 (*rht_hashfn_t)(const void *data, u32 len, u32 seed);
@@ -78,12 +79,6 @@ struct rhashtable;
  * @locks_mul: Number of bucket locks to allocate per cpu (default: 128)
  * @hashfn: Function to hash key
  * @obj_hashfn: Function to hash object
- * @grow_decision: If defined, may return true if table should expand
- * @shrink_decision: If defined, may return true if table should shrink
- *
- * Note: when implementing the grow and shrink decision function, min/max
- * shift must be enforced, otherwise, resizing watermarks they set may be
- * useless.
  */
 struct rhashtable_params {
         size_t                  nelem_hint;
@@ -97,10 +92,6 @@ struct rhashtable_params {
         size_t                  locks_mul;
         rht_hashfn_t            hashfn;
         rht_obj_hashfn_t        obj_hashfn;
-        bool                    (*grow_decision)(const struct rhashtable *ht,
-                                                 size_t new_size);
-        bool                    (*shrink_decision)(const struct rhashtable *ht,
-                                                   size_t new_size);
 };
 
 /**
@@ -192,9 +183,6 @@ int rhashtable_init(struct rhashtable *ht, struct rhashtable_params *params);
 void rhashtable_insert(struct rhashtable *ht, struct rhash_head *node);
 bool rhashtable_remove(struct rhashtable *ht, struct rhash_head *node);
 
-bool rht_grow_above_75(const struct rhashtable *ht, size_t new_size);
-bool rht_shrink_below_30(const struct rhashtable *ht, size_t new_size);
-
 int rhashtable_expand(struct rhashtable *ht);
 int rhashtable_shrink(struct rhashtable *ht);
 
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 41c60e5302d7..6d77432e14ff 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -363,9 +363,6 @@ extern void show_regs(struct pt_regs *);
  */
 extern void show_stack(struct task_struct *task, unsigned long *sp);
 
-void io_schedule(void);
-long io_schedule_timeout(long timeout);
-
 extern void cpu_init (void);
 extern void trap_init(void);
 extern void update_process_times(int user);
@@ -422,6 +419,13 @@ extern signed long schedule_timeout_uninterruptible(signed long timeout);
 asmlinkage void schedule(void);
 extern void schedule_preempt_disabled(void);
 
+extern long io_schedule_timeout(long timeout);
+
+static inline void io_schedule(void)
+{
+        io_schedule_timeout(MAX_SCHEDULE_TIMEOUT);
+}
+
 struct nsproxy;
 struct user_namespace;
 
diff --git a/include/linux/sunrpc/metrics.h b/include/linux/sunrpc/metrics.h
index 7e61a17030a4..694eecb2f1b5 100644
--- a/include/linux/sunrpc/metrics.h
+++ b/include/linux/sunrpc/metrics.h
@@ -89,8 +89,11 @@ void			rpc_free_iostats(struct rpc_iostats *);
 static inline struct rpc_iostats *rpc_alloc_iostats(struct rpc_clnt *clnt) { return NULL; }
 static inline void rpc_count_iostats(const struct rpc_task *task,
                                      struct rpc_iostats *stats) {}
-static inline void rpc_count_iostats_metrics(const struct rpc_task *,
-                                             struct rpc_iostats *) {}
+static inline void rpc_count_iostats_metrics(const struct rpc_task *task,
+                                             struct rpc_iostats *stats)
+{
+}
+
 static inline void rpc_print_iostats(struct seq_file *seq, struct rpc_clnt *clnt) {}
 static inline void rpc_free_iostats(struct rpc_iostats *stats) {}
 
diff --git a/include/linux/thermal.h b/include/linux/thermal.h
index fc52e307efab..5eac316490ea 100644
--- a/include/linux/thermal.h
+++ b/include/linux/thermal.h
@@ -314,6 +314,8 @@ void thermal_zone_of_sensor_unregister(struct device *dev,
 }
 
 #endif
+
+#if IS_ENABLED(CONFIG_THERMAL)
 struct thermal_zone_device *thermal_zone_device_register(const char *, int, int,
                 void *, struct thermal_zone_device_ops *,
                 const struct thermal_zone_params *, int, int);
@@ -340,8 +342,58 @@ struct thermal_instance *get_thermal_instance(struct thermal_zone_device *,
                 struct thermal_cooling_device *, int);
 void thermal_cdev_update(struct thermal_cooling_device *);
 void thermal_notify_framework(struct thermal_zone_device *, int);
-
-#ifdef CONFIG_NET
+#else
+static inline struct thermal_zone_device *thermal_zone_device_register(
+        const char *type, int trips, int mask, void *devdata,
+        struct thermal_zone_device_ops *ops,
+        const struct thermal_zone_params *tzp,
+        int passive_delay, int polling_delay)
+{ return ERR_PTR(-ENODEV); }
+static inline void thermal_zone_device_unregister(
+        struct thermal_zone_device *tz)
+{ }
+static inline int thermal_zone_bind_cooling_device(
+        struct thermal_zone_device *tz, int trip,
+        struct thermal_cooling_device *cdev,
+        unsigned long upper, unsigned long lower)
+{ return -ENODEV; }
+static inline int thermal_zone_unbind_cooling_device(
+        struct thermal_zone_device *tz, int trip,
+        struct thermal_cooling_device *cdev)
+{ return -ENODEV; }
+static inline void thermal_zone_device_update(struct thermal_zone_device *tz)
+{ }
+static inline struct thermal_cooling_device *
+thermal_cooling_device_register(char *type, void *devdata,
+        const struct thermal_cooling_device_ops *ops)
+{ return ERR_PTR(-ENODEV); }
+static inline struct thermal_cooling_device *
+thermal_of_cooling_device_register(struct device_node *np,
+        char *type, void *devdata, const struct thermal_cooling_device_ops *ops)
+{ return ERR_PTR(-ENODEV); }
+static inline void thermal_cooling_device_unregister(
+        struct thermal_cooling_device *cdev)
+{ }
+static inline struct thermal_zone_device *thermal_zone_get_zone_by_name(
+                const char *name)
+{ return ERR_PTR(-ENODEV); }
+static inline int thermal_zone_get_temp(
+                struct thermal_zone_device *tz, unsigned long *temp)
+{ return -ENODEV; }
+static inline int get_tz_trend(struct thermal_zone_device *tz, int trip)
+{ return -ENODEV; }
+static inline struct thermal_instance *
+get_thermal_instance(struct thermal_zone_device *tz,
+        struct thermal_cooling_device *cdev, int trip)
+{ return ERR_PTR(-ENODEV); }
+static inline void thermal_cdev_update(struct thermal_cooling_device *cdev)
+{ }
+static inline void thermal_notify_framework(struct thermal_zone_device *tz,
+        int trip)
+{ }
+#endif /* CONFIG_THERMAL */
+
+#if defined(CONFIG_NET) && IS_ENABLED(CONFIG_THERMAL)
 extern int thermal_generate_netlink_event(struct thermal_zone_device *tz,
                                                 enum events event);
 #else
diff --git a/include/linux/vfio.h b/include/linux/vfio.h
index d3204115f15d..2d67b8998fd8 100644
--- a/include/linux/vfio.h
+++ b/include/linux/vfio.h
@@ -26,6 +26,7 @@
  * @ioctl: Perform ioctl(2) on device file descriptor, supporting VFIO_DEVICE_*
  *         operations documented below
  * @mmap: Perform mmap(2) on a region of the device file descriptor
+ * @request: Request for the bus driver to release the device
  */
 struct vfio_device_ops {
         char    *name;
@@ -38,6 +39,7 @@ struct vfio_device_ops {
         long    (*ioctl)(void *device_data, unsigned int cmd,
                          unsigned long arg);
         int     (*mmap)(void *device_data, struct vm_area_struct *vma);
+        void    (*request)(void *device_data, unsigned int count);
 };
 
 extern int vfio_add_group_dev(struct device *dev,
diff --git a/include/linux/virtio_mmio.h b/include/linux/virtio_mmio.h
index 5c7b6f0daef8..c4b09689ab64 100644
--- a/include/linux/virtio_mmio.h
+++ b/include/linux/virtio_mmio.h
@@ -51,23 +51,29 @@
 /* Virtio vendor ID - Read Only */
 #define VIRTIO_MMIO_VENDOR_ID           0x00c
 
-/* Bitmask of the features supported by the host
+/* Bitmask of the features supported by the device (host)
  * (32 bits per set) - Read Only */
-#define VIRTIO_MMIO_HOST_FEATURES       0x010
+#define VIRTIO_MMIO_DEVICE_FEATURES     0x010
 
-/* Host features set selector - Write Only */
-#define VIRTIO_MMIO_HOST_FEATURES_SEL   0x014
+/* Device (host) features set selector - Write Only */
+#define VIRTIO_MMIO_DEVICE_FEATURES_SEL 0x014
 
-/* Bitmask of features activated by the guest
+/* Bitmask of features activated by the driver (guest)
  * (32 bits per set) - Write Only */
-#define VIRTIO_MMIO_GUEST_FEATURES      0x020
+#define VIRTIO_MMIO_DRIVER_FEATURES     0x020
 
 /* Activated features set selector - Write Only */
-#define VIRTIO_MMIO_GUEST_FEATURES_SEL  0x024
+#define VIRTIO_MMIO_DRIVER_FEATURES_SEL 0x024
+
+
+#ifndef VIRTIO_MMIO_NO_LEGACY /* LEGACY DEVICES ONLY! */
 
 /* Guest's memory page size in bytes - Write Only */
 #define VIRTIO_MMIO_GUEST_PAGE_SIZE     0x028
 
+#endif
+
+
 /* Queue selector - Write Only */
 #define VIRTIO_MMIO_QUEUE_SEL           0x030
 
@@ -77,12 +83,21 @@
 /* Queue size for the currently selected queue - Write Only */
 #define VIRTIO_MMIO_QUEUE_NUM           0x038
 
+
+#ifndef VIRTIO_MMIO_NO_LEGACY /* LEGACY DEVICES ONLY! */
+
 /* Used Ring alignment for the currently selected queue - Write Only */
 #define VIRTIO_MMIO_QUEUE_ALIGN         0x03c
 
 /* Guest's PFN for the currently selected queue - Read Write */
 #define VIRTIO_MMIO_QUEUE_PFN           0x040
 
+#endif
+
+
+/* Ready bit for the currently selected queue - Read Write */
+#define VIRTIO_MMIO_QUEUE_READY         0x044
+
 /* Queue notifier - Write Only */
 #define VIRTIO_MMIO_QUEUE_NOTIFY        0x050
 
@@ -95,6 +110,21 @@
 /* Device status register - Read Write */
 #define VIRTIO_MMIO_STATUS              0x070
 
+/* Selected queue's Descriptor Table address, 64 bits in two halves */
+#define VIRTIO_MMIO_QUEUE_DESC_LOW      0x080
+#define VIRTIO_MMIO_QUEUE_DESC_HIGH     0x084
+
+/* Selected queue's Available Ring address, 64 bits in two halves */
+#define VIRTIO_MMIO_QUEUE_AVAIL_LOW     0x090
+#define VIRTIO_MMIO_QUEUE_AVAIL_HIGH    0x094
+
+/* Selected queue's Used Ring address, 64 bits in two halves */
+#define VIRTIO_MMIO_QUEUE_USED_LOW      0x0a0
+#define VIRTIO_MMIO_QUEUE_USED_HIGH     0x0a4
+
+/* Configuration atomicity value */
+#define VIRTIO_MMIO_CONFIG_GENERATION   0x0fc
+
 /* The config space is defined by each driver as
  * the per-driver configuration space - Read Write */
 #define VIRTIO_MMIO_CONFIG              0x100
diff --git a/include/net/caif/cfpkt.h b/include/net/caif/cfpkt.h
index 1c1ad46250d5..fe328c52c46b 100644
--- a/include/net/caif/cfpkt.h
+++ b/include/net/caif/cfpkt.h
@@ -171,7 +171,7 @@ struct cfpkt *cfpkt_split(struct cfpkt *pkt, u16 pos);
  * @return    Checksum of buffer.
  */
 
-u16 cfpkt_iterate(struct cfpkt *pkt,
+int cfpkt_iterate(struct cfpkt *pkt,
                 u16 (*iter_func)(u16 chks, void *buf, u16 len),
                 u16 data);
 
diff --git a/include/target/iscsi/iscsi_target_core.h b/include/target/iscsi/iscsi_target_core.h
new file mode 100644
index 000000000000..d3583d3ee193
--- /dev/null
+++ b/include/target/iscsi/iscsi_target_core.h
@@ -0,0 +1,897 @@
+#ifndef ISCSI_TARGET_CORE_H
+#define ISCSI_TARGET_CORE_H
+
+#include <linux/in.h>
+#include <linux/configfs.h>
+#include <net/sock.h>
+#include <net/tcp.h>
+#include <scsi/scsi_cmnd.h>
+#include <scsi/iscsi_proto.h>
+#include <target/target_core_base.h>
+
+#define ISCSIT_VERSION                  "v4.1.0"
+#define ISCSI_MAX_DATASN_MISSING_COUNT  16
+#define ISCSI_TX_THREAD_TCP_TIMEOUT     2
+#define ISCSI_RX_THREAD_TCP_TIMEOUT     2
+#define SECONDS_FOR_ASYNC_LOGOUT        10
+#define SECONDS_FOR_ASYNC_TEXT          10
+#define SECONDS_FOR_LOGOUT_COMP         15
+#define WHITE_SPACE                     " \t\v\f\n\r"
+#define ISCSIT_MIN_TAGS                 16
+#define ISCSIT_EXTRA_TAGS               8
+#define ISCSIT_TCP_BACKLOG              256
+
+/* struct iscsi_node_attrib sanity values */
+#define NA_DATAOUT_TIMEOUT              3
+#define NA_DATAOUT_TIMEOUT_MAX          60
+#define NA_DATAOUT_TIMEOUT_MIX          2
+#define NA_DATAOUT_TIMEOUT_RETRIES      5
+#define NA_DATAOUT_TIMEOUT_RETRIES_MAX  15
+#define NA_DATAOUT_TIMEOUT_RETRIES_MIN  1
+#define NA_NOPIN_TIMEOUT                15
+#define NA_NOPIN_TIMEOUT_MAX            60
+#define NA_NOPIN_TIMEOUT_MIN            3
+#define NA_NOPIN_RESPONSE_TIMEOUT       30
+#define NA_NOPIN_RESPONSE_TIMEOUT_MAX   60
+#define NA_NOPIN_RESPONSE_TIMEOUT_MIN   3
+#define NA_RANDOM_DATAIN_PDU_OFFSETS    0
+#define NA_RANDOM_DATAIN_SEQ_OFFSETS    0
+#define NA_RANDOM_R2T_OFFSETS           0
+
+/* struct iscsi_tpg_attrib sanity values */
+#define TA_AUTHENTICATION               1
+#define TA_LOGIN_TIMEOUT                15
+#define TA_LOGIN_TIMEOUT_MAX            30
+#define TA_LOGIN_TIMEOUT_MIN            5
+#define TA_NETIF_TIMEOUT                2
+#define TA_NETIF_TIMEOUT_MAX            15
+#define TA_NETIF_TIMEOUT_MIN            2
+#define TA_GENERATE_NODE_ACLS           0
+#define TA_DEFAULT_CMDSN_DEPTH          64
+#define TA_DEFAULT_CMDSN_DEPTH_MAX      512
+#define TA_DEFAULT_CMDSN_DEPTH_MIN      1
+#define TA_CACHE_DYNAMIC_ACLS           0
+/* Enabled by default in demo mode (generic_node_acls=1) */
+#define TA_DEMO_MODE_WRITE_PROTECT      1
+/* Disabled by default in production mode w/ explict ACLs */
+#define TA_PROD_MODE_WRITE_PROTECT      0
+#define TA_DEMO_MODE_DISCOVERY          1
+#define TA_DEFAULT_ERL                  0
+#define TA_CACHE_CORE_NPS               0
+/* T10 protection information disabled by default */
+#define TA_DEFAULT_T10_PI               0
+
+#define ISCSI_IOV_DATA_BUFFER           5
+
+enum iscsit_transport_type {
+        ISCSI_TCP                               = 0,
+        ISCSI_SCTP_TCP                          = 1,
+        ISCSI_SCTP_UDP                          = 2,
+        ISCSI_IWARP_TCP                         = 3,
+        ISCSI_IWARP_SCTP                        = 4,
+        ISCSI_INFINIBAND                        = 5,
+};
+
+/* RFC-3720 7.1.4  Standard Connection State Diagram for a Target */
+enum target_conn_state_table {
+        TARG_CONN_STATE_FREE                    = 0x1,
+        TARG_CONN_STATE_XPT_UP                  = 0x3,
+        TARG_CONN_STATE_IN_LOGIN                = 0x4,
+        TARG_CONN_STATE_LOGGED_IN               = 0x5,
+        TARG_CONN_STATE_IN_LOGOUT               = 0x6,
+        TARG_CONN_STATE_LOGOUT_REQUESTED        = 0x7,
+        TARG_CONN_STATE_CLEANUP_WAIT            = 0x8,
+};
+
+/* RFC-3720 7.3.2  Session State Diagram for a Target */
+enum target_sess_state_table {
+        TARG_SESS_STATE_FREE                    = 0x1,
+        TARG_SESS_STATE_ACTIVE                  = 0x2,
+        TARG_SESS_STATE_LOGGED_IN               = 0x3,
+        TARG_SESS_STATE_FAILED                  = 0x4,
+        TARG_SESS_STATE_IN_CONTINUE             = 0x5,
+};
+
+/* struct iscsi_data_count->type */
+enum data_count_type {
+        ISCSI_RX_DATA   = 1,
+        ISCSI_TX_DATA   = 2,
+};
+
+/* struct iscsi_datain_req->dr_complete */
+enum datain_req_comp_table {
+        DATAIN_COMPLETE_NORMAL                  = 1,
+        DATAIN_COMPLETE_WITHIN_COMMAND_RECOVERY = 2,
+        DATAIN_COMPLETE_CONNECTION_RECOVERY     = 3,
+};
+
+/* struct iscsi_datain_req->recovery */
+enum datain_req_rec_table {
+        DATAIN_WITHIN_COMMAND_RECOVERY          = 1,
+        DATAIN_CONNECTION_RECOVERY              = 2,
+};
+
+/* struct iscsi_portal_group->state */
+enum tpg_state_table {
+        TPG_STATE_FREE                          = 0,
+        TPG_STATE_ACTIVE                        = 1,
+        TPG_STATE_INACTIVE                      = 2,
+        TPG_STATE_COLD_RESET                    = 3,
+};
+
+/* struct iscsi_tiqn->tiqn_state */
+enum tiqn_state_table {
+        TIQN_STATE_ACTIVE                       = 1,
+        TIQN_STATE_SHUTDOWN                     = 2,
+};
+
+/* struct iscsi_cmd->cmd_flags */
+enum cmd_flags_table {
+        ICF_GOT_LAST_DATAOUT                    = 0x00000001,
+        ICF_GOT_DATACK_SNACK                    = 0x00000002,
+        ICF_NON_IMMEDIATE_UNSOLICITED_DATA      = 0x00000004,
+        ICF_SENT_LAST_R2T                       = 0x00000008,
+        ICF_WITHIN_COMMAND_RECOVERY             = 0x00000010,
+        ICF_CONTIG_MEMORY                       = 0x00000020,
+        ICF_ATTACHED_TO_RQUEUE                  = 0x00000040,
+        ICF_OOO_CMDSN                           = 0x00000080,
+        ICF_SENDTARGETS_ALL                     = 0x00000100,
+        ICF_SENDTARGETS_SINGLE                  = 0x00000200,
+};
+
+/* struct iscsi_cmd->i_state */
+enum cmd_i_state_table {
+        ISTATE_NO_STATE                 = 0,
+        ISTATE_NEW_CMD                  = 1,
+        ISTATE_DEFERRED_CMD             = 2,
+        ISTATE_UNSOLICITED_DATA         = 3,
+        ISTATE_RECEIVE_DATAOUT          = 4,
+        ISTATE_RECEIVE_DATAOUT_RECOVERY = 5,
+        ISTATE_RECEIVED_LAST_DATAOUT    = 6,
+        ISTATE_WITHIN_DATAOUT_RECOVERY  = 7,
+        ISTATE_IN_CONNECTION_RECOVERY   = 8,
+        ISTATE_RECEIVED_TASKMGT         = 9,
+        ISTATE_SEND_ASYNCMSG            = 10,
+        ISTATE_SENT_ASYNCMSG            = 11,
+        ISTATE_SEND_DATAIN              = 12,
+        ISTATE_SEND_LAST_DATAIN         = 13,
+        ISTATE_SENT_LAST_DATAIN         = 14,
+        ISTATE_SEND_LOGOUTRSP           = 15,
+        ISTATE_SENT_LOGOUTRSP           = 16,
+        ISTATE_SEND_NOPIN               = 17,
+        ISTATE_SENT_NOPIN               = 18,
+        ISTATE_SEND_REJECT              = 19,
+        ISTATE_SENT_REJECT              = 20,
+        ISTATE_SEND_R2T                 = 21,
+        ISTATE_SENT_R2T                 = 22,
+        ISTATE_SEND_R2T_RECOVERY        = 23,
+        ISTATE_SENT_R2T_RECOVERY        = 24,
+        ISTATE_SEND_LAST_R2T            = 25,
+        ISTATE_SENT_LAST_R2T            = 26,
+        ISTATE_SEND_LAST_R2T_RECOVERY   = 27,
+        ISTATE_SENT_LAST_R2T_RECOVERY   = 28,
+        ISTATE_SEND_STATUS              = 29,
+        ISTATE_SEND_STATUS_BROKEN_PC    = 30,
+        ISTATE_SENT_STATUS              = 31,
+        ISTATE_SEND_STATUS_RECOVERY     = 32,
+        ISTATE_SENT_STATUS_RECOVERY     = 33,
+        ISTATE_SEND_TASKMGTRSP          = 34,
+        ISTATE_SENT_TASKMGTRSP          = 35,
+        ISTATE_SEND_TEXTRSP             = 36,
+        ISTATE_SENT_TEXTRSP             = 37,
+        ISTATE_SEND_NOPIN_WANT_RESPONSE = 38,
+        ISTATE_SENT_NOPIN_WANT_RESPONSE = 39,
+        ISTATE_SEND_NOPIN_NO_RESPONSE   = 40,
+        ISTATE_REMOVE                   = 41,
+        ISTATE_FREE                     = 42,
+};
+
+/* Used for iscsi_recover_cmdsn() return values */
+enum recover_cmdsn_ret_table {
+        CMDSN_ERROR_CANNOT_RECOVER      = -1,
+        CMDSN_NORMAL_OPERATION          = 0,
+        CMDSN_LOWER_THAN_EXP            = 1,
+        CMDSN_HIGHER_THAN_EXP           = 2,
+        CMDSN_MAXCMDSN_OVERRUN          = 3,
+};
+
+/* Used for iscsi_handle_immediate_data() return values */
+enum immedate_data_ret_table {
+        IMMEDIATE_DATA_CANNOT_RECOVER   = -1,
+        IMMEDIATE_DATA_NORMAL_OPERATION = 0,
+        IMMEDIATE_DATA_ERL1_CRC_FAILURE = 1,
+};
+
+/* Used for iscsi_decide_dataout_action() return values */
+enum dataout_action_ret_table {
+        DATAOUT_CANNOT_RECOVER          = -1,
+        DATAOUT_NORMAL                  = 0,
+        DATAOUT_SEND_R2T                = 1,
+        DATAOUT_SEND_TO_TRANSPORT       = 2,
+        DATAOUT_WITHIN_COMMAND_RECOVERY = 3,
+};
+
+/* Used for struct iscsi_node_auth->naf_flags */
+enum naf_flags_table {
+        NAF_USERID_SET                  = 0x01,
+        NAF_PASSWORD_SET                = 0x02,
+        NAF_USERID_IN_SET               = 0x04,
+        NAF_PASSWORD_IN_SET             = 0x08,
+};
+
+/* Used by various struct timer_list to manage iSCSI specific state */
+enum iscsi_timer_flags_table {
+        ISCSI_TF_RUNNING                = 0x01,
+        ISCSI_TF_STOP                   = 0x02,
+        ISCSI_TF_EXPIRED                = 0x04,
+};
+
+/* Used for struct iscsi_np->np_flags */
+enum np_flags_table {
+        NPF_IP_NETWORK          = 0x00,
+};
+
+/* Used for struct iscsi_np->np_thread_state */
+enum np_thread_state_table {
+        ISCSI_NP_THREAD_ACTIVE          = 1,
+        ISCSI_NP_THREAD_INACTIVE        = 2,
+        ISCSI_NP_THREAD_RESET           = 3,
+        ISCSI_NP_THREAD_SHUTDOWN        = 4,
+        ISCSI_NP_THREAD_EXIT            = 5,
+};
+
+struct iscsi_conn_ops {
+        u8      HeaderDigest;                   /* [0,1] == [None,CRC32C] */
+        u8      DataDigest;                     /* [0,1] == [None,CRC32C] */
+        u32     MaxRecvDataSegmentLength;       /* [512..2**24-1] */
+        u32     MaxXmitDataSegmentLength;       /* [512..2**24-1] */
+        u8      OFMarker;                       /* [0,1] == [No,Yes] */
+        u8      IFMarker;                       /* [0,1] == [No,Yes] */
+        u32     OFMarkInt;                      /* [1..65535] */
+        u32     IFMarkInt;                      /* [1..65535] */
+        /*
+         * iSER specific connection parameters
+         */
+        u32     InitiatorRecvDataSegmentLength; /* [512..2**24-1] */
+        u32     TargetRecvDataSegmentLength;    /* [512..2**24-1] */
+};
+
+struct iscsi_sess_ops {
+        char    InitiatorName[224];
+        char    InitiatorAlias[256];
+        char    TargetName[224];
+        char    TargetAlias[256];
+        char    TargetAddress[256];
+        u16     TargetPortalGroupTag;           /* [0..65535] */
+        u16     MaxConnections;                 /* [1..65535] */
+        u8      InitialR2T;                     /* [0,1] == [No,Yes] */
+        u8      ImmediateData;                  /* [0,1] == [No,Yes] */
+        u32     MaxBurstLength;                 /* [512..2**24-1] */
+        u32     FirstBurstLength;               /* [512..2**24-1] */
+        u16     DefaultTime2Wait;               /* [0..3600] */
+        u16     DefaultTime2Retain;             /* [0..3600] */
+        u16     MaxOutstandingR2T;              /* [1..65535] */
+        u8      DataPDUInOrder;                 /* [0,1] == [No,Yes] */
+        u8      DataSequenceInOrder;            /* [0,1] == [No,Yes] */
+        u8      ErrorRecoveryLevel;             /* [0..2] */
+        u8      SessionType;                    /* [0,1] == [Normal,Discovery]*/
+        /*
+         * iSER specific session parameters
+         */
+        u8      RDMAExtensions;                 /* [0,1] == [No,Yes] */
+};
+
+struct iscsi_queue_req {
+        int                     state;
+        struct iscsi_cmd        *cmd;
+        struct list_head        qr_list;
+};
+
+struct iscsi_data_count {
+        int                     data_length;
+        int                     sync_and_steering;
+        enum data_count_type    type;
+        u32                     iov_count;
+        u32                     ss_iov_count;
+        u32                     ss_marker_count;
+        struct kvec             *iov;
+};
+
+struct iscsi_param_list {
+        bool                    iser;
+        struct list_head        param_list;
+        struct list_head        extra_response_list;
+};
+
+struct iscsi_datain_req {
+        enum datain_req_comp_table dr_complete;
+        int                     generate_recovery_values;
+        enum datain_req_rec_table recovery;
+        u32                     begrun;
+        u32                     runlength;
+        u32                     data_length;
+        u32                     data_offset;
+        u32                     data_sn;
+        u32                     next_burst_len;
+        u32                     read_data_done;
+        u32                     seq_send_order;
+        struct list_head        cmd_datain_node;
+} ____cacheline_aligned;
+
+struct iscsi_ooo_cmdsn {
+        u16                     cid;
+        u32                     batch_count;
+        u32                     cmdsn;
+        u32                     exp_cmdsn;
+        struct iscsi_cmd        *cmd;
+        struct list_head        ooo_list;
+} ____cacheline_aligned;
+
+struct iscsi_datain {
+        u8                      flags;
+        u32                     data_sn;
+        u32                     length;
+        u32                     offset;
+} ____cacheline_aligned;
+
+struct iscsi_r2t {
+        int                     seq_complete;
+        int                     recovery_r2t;
+        int                     sent_r2t;
+        u32                     r2t_sn;
+        u32                     offset;
+        u32                     targ_xfer_tag;
+        u32                     xfer_len;
+        struct list_head        r2t_list;
+} ____cacheline_aligned;
+
+struct iscsi_cmd {
+        enum iscsi_timer_flags_table dataout_timer_flags;
+        /* DataOUT timeout retries */
+        u8                      dataout_timeout_retries;
+        /* Within command recovery count */
+        u8                      error_recovery_count;
+        /* iSCSI dependent state for out or order CmdSNs */
+        enum cmd_i_state_table  deferred_i_state;
+        /* iSCSI dependent state */
+        enum cmd_i_state_table  i_state;
+        /* Command is an immediate command (ISCSI_OP_IMMEDIATE set) */
+        u8                      immediate_cmd;
+        /* Immediate data present */
+        u8                      immediate_data;
+        /* iSCSI Opcode */
+        u8                      iscsi_opcode;
+        /* iSCSI Response Code */
+        u8                      iscsi_response;
+        /* Logout reason when iscsi_opcode == ISCSI_INIT_LOGOUT_CMND */
+        u8                      logout_reason;
+        /* Logout response code when iscsi_opcode == ISCSI_INIT_LOGOUT_CMND */
+        u8                      logout_response;
+        /* MaxCmdSN has been incremented */
+        u8                      maxcmdsn_inc;
+        /* Immediate Unsolicited Dataout */
+        u8                      unsolicited_data;
+        /* Reject reason code */
+        u8                      reject_reason;
+        /* CID contained in logout PDU when opcode == ISCSI_INIT_LOGOUT_CMND */
+        u16                     logout_cid;
+        /* Command flags */
+        enum cmd_flags_table    cmd_flags;
+        /* Initiator Task Tag assigned from Initiator */
+        itt_t                   init_task_tag;
+        /* Target Transfer Tag assigned from Target */
+        u32                     targ_xfer_tag;
+        /* CmdSN assigned from Initiator */
+        u32                     cmd_sn;
+        /* ExpStatSN assigned from Initiator */
+        u32                     exp_stat_sn;
+        /* StatSN assigned to this ITT */
+        u32                     stat_sn;
+        /* DataSN Counter */
+        u32                     data_sn;
+        /* R2TSN Counter */
+        u32                     r2t_sn;
+        /* Last DataSN acknowledged via DataAck SNACK */
+        u32                     acked_data_sn;
+        /* Used for echoing NOPOUT ping data */
+        u32                     buf_ptr_size;
+        /* Used to store DataDigest */
+        u32                     data_crc;
+        /* Counter for MaxOutstandingR2T */
+        u32                     outstanding_r2ts;
+        /* Next R2T Offset when DataSequenceInOrder=Yes */
+        u32                     r2t_offset;
+        /* Iovec current and orig count for iscsi_cmd->iov_data */
+        u32                     iov_data_count;
+        u32                     orig_iov_data_count;
+        /* Number of miscellaneous iovecs used for IP stack calls */
+        u32                     iov_misc_count;
+        /* Number of struct iscsi_pdu in struct iscsi_cmd->pdu_list */
+        u32                     pdu_count;
+        /* Next struct iscsi_pdu to send in struct iscsi_cmd->pdu_list */
+        u32                     pdu_send_order;
+        /* Current struct iscsi_pdu in struct iscsi_cmd->pdu_list */
+        u32                     pdu_start;
+        /* Next struct iscsi_seq to send in struct iscsi_cmd->seq_list */
+        u32                     seq_send_order;
+        /* Number of struct iscsi_seq in struct iscsi_cmd->seq_list */
+        u32                     seq_count;
+        /* Current struct iscsi_seq in struct iscsi_cmd->seq_list */
+        u32                     seq_no;
+        /* Lowest offset in current DataOUT sequence */
+        u32                     seq_start_offset;
+        /* Highest offset in current DataOUT sequence */
+        u32                     seq_end_offset;
+        /* Total size in bytes received so far of READ data */
+        u32                     read_data_done;
+        /* Total size in bytes received so far of WRITE data */
+        u32                     write_data_done;
+        /* Counter for FirstBurstLength key */
+        u32                     first_burst_len;
+        /* Counter for MaxBurstLength key */
+        u32                     next_burst_len;
+        /* Transfer size used for IP stack calls */
+        u32                     tx_size;
+        /* Buffer used for various purposes */
+        void                    *buf_ptr;
+        /* Used by SendTargets=[iqn.,eui.] discovery */
+        void                    *text_in_ptr;
+        /* See include/linux/dma-mapping.h */
+        enum dma_data_direction data_direction;
+        /* iSCSI PDU Header + CRC */
+        unsigned char           pdu[ISCSI_HDR_LEN + ISCSI_CRC_LEN];
+        /* Number of times struct iscsi_cmd is present in immediate queue */
+        atomic_t                immed_queue_count;
+        atomic_t                response_queue_count;
+        spinlock_t              datain_lock;
+        spinlock_t              dataout_timeout_lock;
+        /* spinlock for protecting struct iscsi_cmd->i_state */
+        spinlock_t              istate_lock;
+        /* spinlock for adding within command recovery entries */
+        spinlock_t              error_lock;
+        /* spinlock for adding R2Ts */
+        spinlock_t              r2t_lock;
+        /* DataIN List */
+        struct list_head        datain_list;
+        /* R2T List */
+        struct list_head        cmd_r2t_list;
+        /* Timer for DataOUT */
+        struct timer_list       dataout_timer;
+        /* Iovecs for SCSI data payload RX/TX w/ kernel level sockets */
+        struct kvec             *iov_data;
+        /* Iovecs for miscellaneous purposes */
+#define ISCSI_MISC_IOVECS                       5
+        struct kvec             iov_misc[ISCSI_MISC_IOVECS];
+        /* Array of struct iscsi_pdu used for DataPDUInOrder=No */
+        struct iscsi_pdu        *pdu_list;
+        /* Current struct iscsi_pdu used for DataPDUInOrder=No */
+        struct iscsi_pdu        *pdu_ptr;
+        /* Array of struct iscsi_seq used for DataSequenceInOrder=No */
+        struct iscsi_seq        *seq_list;
+        /* Current struct iscsi_seq used for DataSequenceInOrder=No */
+        struct iscsi_seq        *seq_ptr;
+        /* TMR Request when iscsi_opcode == ISCSI_OP_SCSI_TMFUNC */
+        struct iscsi_tmr_req    *tmr_req;
+        /* Connection this command is alligient to */
+        struct iscsi_conn       *conn;
+        /* Pointer to connection recovery entry */
+        struct iscsi_conn_recovery *cr;
+        /* Session the command is part of,  used for connection recovery */
+        struct iscsi_session    *sess;
+        /* list_head for connection list */
+        struct list_head        i_conn_node;
+        /* The TCM I/O descriptor that is accessed via container_of() */
+        struct se_cmd           se_cmd;
+        /* Sense buffer that will be mapped into outgoing status */
+#define ISCSI_SENSE_BUFFER_LEN          (TRANSPORT_SENSE_BUFFER + 2)
+        unsigned char           sense_buffer[ISCSI_SENSE_BUFFER_LEN];
+
+        u32                     padding;
+        u8                      pad_bytes[4];
+
+        struct scatterlist      *first_data_sg;
+        u32                     first_data_sg_off;
+        u32                     kmapped_nents;
+        sense_reason_t          sense_reason;
+}  ____cacheline_aligned;
+
+struct iscsi_tmr_req {
+        bool                    task_reassign:1;
+        u32                     exp_data_sn;
+        struct iscsi_cmd        *ref_cmd;
+        struct iscsi_conn_recovery *conn_recovery;
+        struct se_tmr_req       *se_tmr_req;
+};
+
+struct iscsi_conn {
+        wait_queue_head_t       queues_wq;
+        /* Authentication Successful for this connection */
+        u8                      auth_complete;
+        /* State connection is currently in */
+        u8                      conn_state;
+        u8                      conn_logout_reason;
+        u8                      network_transport;
+        enum iscsi_timer_flags_table nopin_timer_flags;
+        enum iscsi_timer_flags_table nopin_response_timer_flags;
+        /* Used to know what thread encountered a transport failure */
+        u8                      which_thread;
+        /* connection id assigned by the Initiator */
+        u16                     cid;
+        /* Remote TCP Port */
+        u16                     login_port;
+        u16                     local_port;
+        int                     net_size;
+        int                     login_family;
+        u32                     auth_id;
+        u32                     conn_flags;
+        /* Used for iscsi_tx_login_rsp() */
+        itt_t                   login_itt;
+        u32                     exp_statsn;
+        /* Per connection status sequence number */
+        u32                     stat_sn;
+        /* IFMarkInt's Current Value */
+        u32                     if_marker;
+        /* OFMarkInt's Current Value */
+        u32                     of_marker;
+        /* Used for calculating OFMarker offset to next PDU */
+        u32                     of_marker_offset;
+#define IPV6_ADDRESS_SPACE                              48
+        unsigned char           login_ip[IPV6_ADDRESS_SPACE];
+        unsigned char           local_ip[IPV6_ADDRESS_SPACE];
+        int                     conn_usage_count;
+        int                     conn_waiting_on_uc;
+        atomic_t                check_immediate_queue;
+        atomic_t                conn_logout_remove;
+        atomic_t                connection_exit;
+        atomic_t                connection_recovery;
+        atomic_t                connection_reinstatement;
+        atomic_t                connection_wait_rcfr;
+        atomic_t                sleep_on_conn_wait_comp;
+        atomic_t                transport_failed;
+        struct completion       conn_post_wait_comp;
+        struct completion       conn_wait_comp;
+        struct completion       conn_wait_rcfr_comp;
+        struct completion       conn_waiting_on_uc_comp;
+        struct completion       conn_logout_comp;
+        struct completion       tx_half_close_comp;
+        struct completion       rx_half_close_comp;
+        /* socket used by this connection */
+        struct socket           *sock;
+        void                    (*orig_data_ready)(struct sock *);
+        void                    (*orig_state_change)(struct sock *);
+#define LOGIN_FLAGS_READ_ACTIVE         1
+#define LOGIN_FLAGS_CLOSED              2
+#define LOGIN_FLAGS_READY               4
+        unsigned long           login_flags;
+        struct delayed_work     login_work;
+        struct delayed_work     login_cleanup_work;
+        struct iscsi_login      *login;
+        struct timer_list       nopin_timer;
+        struct timer_list       nopin_response_timer;
+        struct timer_list       transport_timer;
+        struct task_struct      *login_kworker;
+        /* Spinlock used for add/deleting cmd's from conn_cmd_list */
+        spinlock_t              cmd_lock;
+        spinlock_t              conn_usage_lock;
+        spinlock_t              immed_queue_lock;
+        spinlock_t              nopin_timer_lock;
+        spinlock_t              response_queue_lock;
+        spinlock_t              state_lock;
+        /* libcrypto RX and TX contexts for crc32c */
+        struct hash_desc        conn_rx_hash;
+        struct hash_desc        conn_tx_hash;
+        /* Used for scheduling TX and RX connection kthreads */
+        cpumask_var_t           conn_cpumask;
+        unsigned int            conn_rx_reset_cpumask:1;
+        unsigned int            conn_tx_reset_cpumask:1;
+        /* list_head of struct iscsi_cmd for this connection */
+        struct list_head        conn_cmd_list;
+        struct list_head        immed_queue_list;
+        struct list_head        response_queue_list;
+        struct iscsi_conn_ops   *conn_ops;
+        struct iscsi_login      *conn_login;
+        struct iscsit_transport *conn_transport;
+        struct iscsi_param_list *param_list;
+        /* Used for per connection auth state machine */
+        void                    *auth_protocol;
+        void                    *context;
+        struct iscsi_login_thread_s *login_thread;
+        struct iscsi_portal_group *tpg;
+        struct iscsi_tpg_np     *tpg_np;
+        /* Pointer to parent session */
+        struct iscsi_session    *sess;
+        /* Pointer to thread_set in use for this conn's threads */
+        struct iscsi_thread_set *thread_set;
+        /* list_head for session connection list */
+        struct list_head        conn_list;
+} ____cacheline_aligned;
+
+struct iscsi_conn_recovery {
+        u16                     cid;
+        u32                     cmd_count;
+        u32                     maxrecvdatasegmentlength;
+        u32                     maxxmitdatasegmentlength;
+        int                     ready_for_reallegiance;
+        struct list_head        conn_recovery_cmd_list;
+        spinlock_t              conn_recovery_cmd_lock;
+        struct timer_list       time2retain_timer;
+        struct iscsi_session    *sess;
+        struct list_head        cr_list;
+}  ____cacheline_aligned;
+
+struct iscsi_session {
+        u8                      initiator_vendor;
+        u8                      isid[6];
+        enum iscsi_timer_flags_table time2retain_timer_flags;
+        u8                      version_active;
+        u16                     cid_called;
+        u16                     conn_recovery_count;
+        u16                     tsih;
+        /* state session is currently in */
+        u32                     session_state;
+        /* session wide counter: initiator assigned task tag */
+        itt_t                   init_task_tag;
+        /* session wide counter: target assigned task tag */
+        u32                     targ_xfer_tag;
+        u32                     cmdsn_window;
+
+        /* protects cmdsn values */
+        struct mutex            cmdsn_mutex;
+        /* session wide counter: expected command sequence number */
+        u32                     exp_cmd_sn;
+        /* session wide counter: maximum allowed command sequence number */
+        u32                     max_cmd_sn;
+        struct list_head        sess_ooo_cmdsn_list;
+
+        /* LIO specific session ID */
+        u32                     sid;
+        char                    auth_type[8];
+        /* unique within the target */
+        int                     session_index;
+        /* Used for session reference counting */
+        int                     session_usage_count;
+        int                     session_waiting_on_uc;
+        atomic_long_t           cmd_pdus;
+        atomic_long_t           rsp_pdus;
+        atomic_long_t           tx_data_octets;
+        atomic_long_t           rx_data_octets;
+        atomic_long_t           conn_digest_errors;
+        atomic_long_t           conn_timeout_errors;
+        u64                     creation_time;
+        /* Number of active connections */
+        atomic_t                nconn;
+        atomic_t                session_continuation;
+        atomic_t                session_fall_back_to_erl0;
+        atomic_t                session_logout;
+        atomic_t                session_reinstatement;
+        atomic_t                session_stop_active;
+        atomic_t                sleep_on_sess_wait_comp;
+        /* connection list */
+        struct list_head        sess_conn_list;
+        struct list_head        cr_active_list;
+        struct list_head        cr_inactive_list;
+        spinlock_t              conn_lock;
+        spinlock_t              cr_a_lock;
+        spinlock_t              cr_i_lock;
+        spinlock_t              session_usage_lock;
+        spinlock_t              ttt_lock;
+        struct completion       async_msg_comp;
+        struct completion       reinstatement_comp;
+        struct completion       session_wait_comp;
+        struct completion       session_waiting_on_uc_comp;
+        struct timer_list       time2retain_timer;
+        struct iscsi_sess_ops   *sess_ops;
+        struct se_session       *se_sess;
+        struct iscsi_portal_group *tpg;
+} ____cacheline_aligned;
+
+struct iscsi_login {
+        u8 auth_complete;
+        u8 checked_for_existing;
+        u8 current_stage;
+        u8 leading_connection;
+        u8 first_request;
+        u8 version_min;
+        u8 version_max;
+        u8 login_complete;
+        u8 login_failed;
+        bool zero_tsih;
+        char isid[6];
+        u32 cmd_sn;
+        itt_t init_task_tag;
+        u32 initial_exp_statsn;
+        u32 rsp_length;
+        u16 cid;
+        u16 tsih;
+        char req[ISCSI_HDR_LEN];
+        char rsp[ISCSI_HDR_LEN];
+        char *req_buf;
+        char *rsp_buf;
+        struct iscsi_conn *conn;
+        struct iscsi_np *np;
+} ____cacheline_aligned;
+
+struct iscsi_node_attrib {
+        u32                     dataout_timeout;
+        u32                     dataout_timeout_retries;
+        u32                     default_erl;
+        u32                     nopin_timeout;
+        u32                     nopin_response_timeout;
+        u32                     random_datain_pdu_offsets;
+        u32                     random_datain_seq_offsets;
+        u32                     random_r2t_offsets;
+        u32                     tmr_cold_reset;
+        u32                     tmr_warm_reset;
+        struct iscsi_node_acl *nacl;
+};
+
+struct se_dev_entry_s;
+
+struct iscsi_node_auth {
+        enum naf_flags_table    naf_flags;
+        int                     authenticate_target;
+        /* Used for iscsit_global->discovery_auth,
+         * set to zero (auth disabled) by default */
+        int                     enforce_discovery_auth;
+#define MAX_USER_LEN                            256
+#define MAX_PASS_LEN                            256
+        char                    userid[MAX_USER_LEN];
+        char                    password[MAX_PASS_LEN];
+        char                    userid_mutual[MAX_USER_LEN];
+        char                    password_mutual[MAX_PASS_LEN];
+};
+
+#include "iscsi_target_stat.h"
+
+struct iscsi_node_stat_grps {
+        struct config_group     iscsi_sess_stats_group;
+        struct config_group     iscsi_conn_stats_group;
+};
+
+struct iscsi_node_acl {
+        struct iscsi_node_attrib node_attrib;
+        struct iscsi_node_auth  node_auth;
+        struct iscsi_node_stat_grps node_stat_grps;
+        struct se_node_acl      se_node_acl;
+};
+
+struct iscsi_tpg_attrib {
+        u32                     authentication;
+        u32                     login_timeout;
+        u32                     netif_timeout;
+        u32                     generate_node_acls;
+        u32                     cache_dynamic_acls;
+        u32                     default_cmdsn_depth;
+        u32                     demo_mode_write_protect;
+        u32                     prod_mode_write_protect;
+        u32                     demo_mode_discovery;
+        u32                     default_erl;
+        u8                      t10_pi;
+        struct iscsi_portal_group *tpg;
+};
+
+struct iscsi_np {
+        int                     np_network_transport;
+        int                     np_ip_proto;
+        int                     np_sock_type;
+        enum np_thread_state_table np_thread_state;
+        bool                    enabled;
+        enum iscsi_timer_flags_table np_login_timer_flags;
+        u32                     np_exports;
+        enum np_flags_table     np_flags;
+        unsigned char           np_ip[IPV6_ADDRESS_SPACE];
+        u16                     np_port;
+        spinlock_t              np_thread_lock;
+        struct completion       np_restart_comp;
+        struct socket           *np_socket;
+        struct __kernel_sockaddr_storage np_sockaddr;
+        struct task_struct      *np_thread;
+        struct timer_list       np_login_timer;
+        void                    *np_context;
+        struct iscsit_transport *np_transport;
+        struct list_head        np_list;
+} ____cacheline_aligned;
+
+struct iscsi_tpg_np {
+        struct iscsi_np         *tpg_np;
+        struct iscsi_portal_group *tpg;
+        struct iscsi_tpg_np     *tpg_np_parent;
+        struct list_head        tpg_np_list;
+        struct list_head        tpg_np_child_list;
+        struct list_head        tpg_np_parent_list;
+        struct se_tpg_np        se_tpg_np;
+        spinlock_t              tpg_np_parent_lock;
+        struct completion       tpg_np_comp;
+        struct kref             tpg_np_kref;
+};
+
+struct iscsi_portal_group {
+        unsigned char           tpg_chap_id;
+        /* TPG State */
+        enum tpg_state_table    tpg_state;
+        /* Target Portal Group Tag */
+        u16                     tpgt;
+        /* Id assigned to target sessions */
+        u16                     ntsih;
+        /* Number of active sessions */
+        u32                     nsessions;
+        /* Number of Network Portals available for this TPG */
+        u32                     num_tpg_nps;
+        /* Per TPG LIO specific session ID. */
+        u32                     sid;
+        /* Spinlock for adding/removing Network Portals */
+        spinlock_t              tpg_np_lock;
+        spinlock_t              tpg_state_lock;
+        struct se_portal_group tpg_se_tpg;
+        struct mutex            tpg_access_lock;
+        struct semaphore        np_login_sem;
+        struct iscsi_tpg_attrib tpg_attrib;
+        struct iscsi_node_auth  tpg_demo_auth;
+        /* Pointer to default list of iSCSI parameters for TPG */
+        struct iscsi_param_list *param_list;
+        struct iscsi_tiqn       *tpg_tiqn;
+        struct list_head        tpg_gnp_list;
+        struct list_head        tpg_list;
+} ____cacheline_aligned;
+
+struct iscsi_wwn_stat_grps {
+        struct config_group     iscsi_stat_group;
+        struct config_group     iscsi_instance_group;
+        struct config_group     iscsi_sess_err_group;
+        struct config_group     iscsi_tgt_attr_group;
+        struct config_group     iscsi_login_stats_group;
+        struct config_group     iscsi_logout_stats_group;
+};
+
+struct iscsi_tiqn {
+#define ISCSI_IQN_LEN                           224
+        unsigned char           tiqn[ISCSI_IQN_LEN];
+        enum tiqn_state_table   tiqn_state;
+        int                     tiqn_access_count;
+        u32                     tiqn_active_tpgs;
+        u32                     tiqn_ntpgs;
+        u32                     tiqn_num_tpg_nps;
+        u32                     tiqn_nsessions;
+        struct list_head        tiqn_list;
+        struct list_head        tiqn_tpg_list;
+        spinlock_t              tiqn_state_lock;
+        spinlock_t              tiqn_tpg_lock;
+        struct se_wwn           tiqn_wwn;
+        struct iscsi_wwn_stat_grps tiqn_stat_grps;
+        int                     tiqn_index;
+        struct iscsi_sess_err_stats  sess_err_stats;
+        struct iscsi_login_stats     login_stats;
+        struct iscsi_logout_stats    logout_stats;
+} ____cacheline_aligned;
+
+struct iscsit_global {
+        /* In core shutdown */
+        u32                     in_shutdown;
+        u32                     active_ts;
+        /* Unique identifier used for the authentication daemon */
+        u32                     auth_id;
+        u32                     inactive_ts;
+        /* Thread Set bitmap count */
+        int                     ts_bitmap_count;
+        /* Thread Set bitmap pointer */
+        unsigned long           *ts_bitmap;
+        /* Used for iSCSI discovery session authentication */
+        struct iscsi_node_acl   discovery_acl;
+        struct iscsi_portal_group       *discovery_tpg;
+};
+
+static inline u32 session_get_next_ttt(struct iscsi_session *session)
+{
+        u32 ttt;
+
+        spin_lock_bh(&session->ttt_lock);
+        ttt = session->targ_xfer_tag++;
+        if (ttt == 0xFFFFFFFF)
+                ttt = session->targ_xfer_tag++;
+        spin_unlock_bh(&session->ttt_lock);
+
+        return ttt;
+}
+
+extern struct iscsi_cmd *iscsit_find_cmd_from_itt(struct iscsi_conn *, itt_t);
+#endif /* ISCSI_TARGET_CORE_H */
diff --git a/include/target/iscsi/iscsi_target_stat.h b/include/target/iscsi/iscsi_target_stat.h
new file mode 100644
index 000000000000..3ff76b4faad3
--- /dev/null
+++ b/include/target/iscsi/iscsi_target_stat.h
@@ -0,0 +1,64 @@
+#ifndef ISCSI_TARGET_STAT_H
+#define ISCSI_TARGET_STAT_H
+
+/*
+ * For struct iscsi_tiqn->tiqn_wwn default groups
+ */
+extern struct config_item_type iscsi_stat_instance_cit;
+extern struct config_item_type iscsi_stat_sess_err_cit;
+extern struct config_item_type iscsi_stat_tgt_attr_cit;
+extern struct config_item_type iscsi_stat_login_cit;
+extern struct config_item_type iscsi_stat_logout_cit;
+
+/*
+ * For struct iscsi_session->se_sess default groups
+ */
+extern struct config_item_type iscsi_stat_sess_cit;
+
+/* iSCSI session error types */
+#define ISCSI_SESS_ERR_UNKNOWN          0
+#define ISCSI_SESS_ERR_DIGEST           1
+#define ISCSI_SESS_ERR_CXN_TIMEOUT      2
+#define ISCSI_SESS_ERR_PDU_FORMAT       3
+
+/* iSCSI session error stats */
+struct iscsi_sess_err_stats {
+        spinlock_t      lock;
+        u32             digest_errors;
+        u32             cxn_timeout_errors;
+        u32             pdu_format_errors;
+        u32             last_sess_failure_type;
+        char            last_sess_fail_rem_name[224];
+} ____cacheline_aligned;
+
+/* iSCSI login failure types (sub oids) */
+#define ISCSI_LOGIN_FAIL_OTHER          2
+#define ISCSI_LOGIN_FAIL_REDIRECT       3
+#define ISCSI_LOGIN_FAIL_AUTHORIZE      4
+#define ISCSI_LOGIN_FAIL_AUTHENTICATE   5
+#define ISCSI_LOGIN_FAIL_NEGOTIATE      6
+
+/* iSCSI login stats */
+struct iscsi_login_stats {
+        spinlock_t      lock;
+        u32             accepts;
+        u32             other_fails;
+        u32             redirects;
+        u32             authorize_fails;
+        u32             authenticate_fails;
+        u32             negotiate_fails;        /* used for notifications */
+        u64             last_fail_time;         /* time stamp (jiffies) */
+        u32             last_fail_type;
+        int             last_intr_fail_ip_family;
+        unsigned char   last_intr_fail_ip_addr[IPV6_ADDRESS_SPACE];
+        char            last_intr_fail_name[224];
+} ____cacheline_aligned;
+
+/* iSCSI logout stats */
+struct iscsi_logout_stats {
+        spinlock_t      lock;
+        u32             normal_logouts;
+        u32             abnormal_logouts;
+} ____cacheline_aligned;
+
+#endif   /*** ISCSI_TARGET_STAT_H ***/
diff --git a/include/target/iscsi/iscsi_transport.h b/include/target/iscsi/iscsi_transport.h
index daef9daa500c..e6bb166f12c2 100644
--- a/include/target/iscsi/iscsi_transport.h
+++ b/include/target/iscsi/iscsi_transport.h
@@ -1,6 +1,6 @@
 #include <linux/module.h>
 #include <linux/list.h>
-#include "../../../drivers/target/iscsi/iscsi_target_core.h"
+#include "iscsi_target_core.h"
 
 struct iscsit_transport {
 #define ISCSIT_TRANSPORT_NAME   16
diff --git a/include/target/target_core_base.h b/include/target/target_core_base.h
index 4a8795a87b9e..672150b6aaf5 100644
--- a/include/target/target_core_base.h
+++ b/include/target/target_core_base.h
@@ -407,7 +407,7 @@ struct t10_reservation {
         /* Activate Persistence across Target Power Loss enabled
          * for SCSI device */
         int pr_aptpl_active;
-#define PR_APTPL_BUF_LEN                        8192
+#define PR_APTPL_BUF_LEN                        262144
         u32 pr_generation;
         spinlock_t registration_lock;
         spinlock_t aptpl_reg_lock;
diff --git a/include/uapi/linux/btrfs.h b/include/uapi/linux/btrfs.h
index 611e1c5893b4..b6dec05c7196 100644
--- a/include/uapi/linux/btrfs.h
+++ b/include/uapi/linux/btrfs.h
@@ -495,8 +495,7 @@ struct btrfs_ioctl_send_args {
 
 /* Error codes as returned by the kernel */
 enum btrfs_err_code {
-        notused,
-        BTRFS_ERROR_DEV_RAID1_MIN_NOT_MET,
+        BTRFS_ERROR_DEV_RAID1_MIN_NOT_MET = 1,
         BTRFS_ERROR_DEV_RAID10_MIN_NOT_MET,
         BTRFS_ERROR_DEV_RAID5_MIN_NOT_MET,
         BTRFS_ERROR_DEV_RAID6_MIN_NOT_MET,
diff --git a/include/uapi/linux/nvme.h b/include/uapi/linux/nvme.h
index 26386cf3db44..aef9a81b2d75 100644
--- a/include/uapi/linux/nvme.h
+++ b/include/uapi/linux/nvme.h
@@ -115,7 +115,13 @@ struct nvme_id_ns {
         __le16                  nawun;
         __le16                  nawupf;
         __le16                  nacwu;
-        __u8                    rsvd40[80];
+        __le16                  nabsn;
+        __le16                  nabo;
+        __le16                  nabspf;
+        __u16                   rsvd46;
+        __le64                  nvmcap[2];
+        __u8                    rsvd64[40];
+        __u8                    nguid[16];
         __u8                    eui64[8];
         struct nvme_lbaf        lbaf[16];
         __u8                    rsvd192[192];
@@ -124,10 +130,22 @@ struct nvme_id_ns {
 
 enum {
         NVME_NS_FEAT_THIN       = 1 << 0,
+        NVME_NS_FLBAS_LBA_MASK  = 0xf,
+        NVME_NS_FLBAS_META_EXT  = 0x10,
         NVME_LBAF_RP_BEST       = 0,
         NVME_LBAF_RP_BETTER     = 1,
         NVME_LBAF_RP_GOOD       = 2,
         NVME_LBAF_RP_DEGRADED   = 3,
+        NVME_NS_DPC_PI_LAST     = 1 << 4,
+        NVME_NS_DPC_PI_FIRST    = 1 << 3,
+        NVME_NS_DPC_PI_TYPE3    = 1 << 2,
+        NVME_NS_DPC_PI_TYPE2    = 1 << 1,
+        NVME_NS_DPC_PI_TYPE1    = 1 << 0,
+        NVME_NS_DPS_PI_FIRST    = 1 << 3,
+        NVME_NS_DPS_PI_MASK     = 0x7,
+        NVME_NS_DPS_PI_TYPE1    = 1,
+        NVME_NS_DPS_PI_TYPE2    = 2,
+        NVME_NS_DPS_PI_TYPE3    = 3,
 };
 
 struct nvme_smart_log {
@@ -261,6 +279,10 @@ enum {
         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
         NVME_RW_DSM_COMPRESSED          = 1 << 7,
+        NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
+        NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
+        NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
+        NVME_RW_PRINFO_PRACT            = 1 << 13,
 };
 
 struct nvme_dsm_cmd {
@@ -549,6 +571,8 @@ struct nvme_passthru_cmd {
         __u32   result;
 };
 
+#define NVME_VS(major, minor) (((major) << 16) | ((minor) << 8))
+
 #define nvme_admin_cmd nvme_passthru_cmd
 
 #define NVME_IOCTL_ID           _IO('N', 0x40)
diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h
index 89f63503f903..31891d9535e2 100644
--- a/include/uapi/linux/prctl.h
+++ b/include/uapi/linux/prctl.h
@@ -185,4 +185,9 @@ struct prctl_mm_map {
 #define PR_MPX_ENABLE_MANAGEMENT  43
 #define PR_MPX_DISABLE_MANAGEMENT 44
 
+#define PR_SET_FP_MODE          45
+#define PR_GET_FP_MODE          46
+# define PR_FP_MODE_FR          (1 << 0)        /* 64b FP registers */
+# define PR_FP_MODE_FRE         (1 << 1)        /* 32b compatibility */
+
 #endif /* _LINUX_PRCTL_H */
diff --git a/include/uapi/linux/tc_act/Kbuild b/include/uapi/linux/tc_act/Kbuild
index 19d5219b0b99..242cf0c6e33d 100644
--- a/include/uapi/linux/tc_act/Kbuild
+++ b/include/uapi/linux/tc_act/Kbuild
@@ -9,3 +9,4 @@ header-y += tc_pedit.h
 header-y += tc_skbedit.h
 header-y += tc_vlan.h
 header-y += tc_bpf.h
+header-y += tc_connmark.h
diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h
index 29715d27548f..82889c30f4f5 100644
--- a/include/uapi/linux/vfio.h
+++ b/include/uapi/linux/vfio.h
@@ -333,6 +333,7 @@ enum {
         VFIO_PCI_MSI_IRQ_INDEX,
         VFIO_PCI_MSIX_IRQ_INDEX,
         VFIO_PCI_ERR_IRQ_INDEX,
+        VFIO_PCI_REQ_IRQ_INDEX,
         VFIO_PCI_NUM_IRQS
 };
 
diff --git a/include/uapi/linux/virtio_balloon.h b/include/uapi/linux/virtio_balloon.h
index be40f7059e93..4b0488f20b2e 100644
--- a/include/uapi/linux/virtio_balloon.h
+++ b/include/uapi/linux/virtio_balloon.h
@@ -36,8 +36,7 @@
 /* Size of a PFN in the balloon interface. */
 #define VIRTIO_BALLOON_PFN_SHIFT 12
 
-struct virtio_balloon_config
-{
+struct virtio_balloon_config {
         /* Number of pages host wants Guest to give up. */
         __le32 num_pages;
         /* Number of pages we've actually got in balloon. */
diff --git a/include/uapi/linux/virtio_blk.h b/include/uapi/linux/virtio_blk.h
index 247c8ba8544a..3c53eec4ae22 100644
--- a/include/uapi/linux/virtio_blk.h
+++ b/include/uapi/linux/virtio_blk.h
@@ -31,22 +31,25 @@
 #include <linux/virtio_types.h>
 
 /* Feature bits */
-#define VIRTIO_BLK_F_BARRIER    0       /* Does host support barriers? */
 #define VIRTIO_BLK_F_SIZE_MAX   1       /* Indicates maximum segment size */
 #define VIRTIO_BLK_F_SEG_MAX    2       /* Indicates maximum # of segments */
 #define VIRTIO_BLK_F_GEOMETRY   4       /* Legacy geometry available  */
 #define VIRTIO_BLK_F_RO         5       /* Disk is read-only */
 #define VIRTIO_BLK_F_BLK_SIZE   6       /* Block size of disk is available*/
-#define VIRTIO_BLK_F_SCSI       7       /* Supports scsi command passthru */
-#define VIRTIO_BLK_F_WCE        9       /* Writeback mode enabled after reset */
 #define VIRTIO_BLK_F_TOPOLOGY   10      /* Topology information is available */
-#define VIRTIO_BLK_F_CONFIG_WCE 11      /* Writeback mode available in config */
 #define VIRTIO_BLK_F_MQ         12      /* support more than one vq */
 
+/* Legacy feature bits */
+#ifndef VIRTIO_BLK_NO_LEGACY
+#define VIRTIO_BLK_F_BARRIER    0       /* Does host support barriers? */
+#define VIRTIO_BLK_F_SCSI       7       /* Supports scsi command passthru */
+#define VIRTIO_BLK_F_WCE        9       /* Writeback mode enabled after reset */
+#define VIRTIO_BLK_F_CONFIG_WCE 11      /* Writeback mode available in config */
 #ifndef __KERNEL__
 /* Old (deprecated) name for VIRTIO_BLK_F_WCE. */
 #define VIRTIO_BLK_F_FLUSH VIRTIO_BLK_F_WCE
 #endif
+#endif /* !VIRTIO_BLK_NO_LEGACY */
 
 #define VIRTIO_BLK_ID_BYTES     20      /* ID string length */
 
@@ -100,8 +103,10 @@ struct virtio_blk_config {
 #define VIRTIO_BLK_T_IN         0
 #define VIRTIO_BLK_T_OUT        1
 
+#ifndef VIRTIO_BLK_NO_LEGACY
 /* This bit says it's a scsi command, not an actual read or write. */
 #define VIRTIO_BLK_T_SCSI_CMD   2
+#endif /* VIRTIO_BLK_NO_LEGACY */
 
 /* Cache flush command */
 #define VIRTIO_BLK_T_FLUSH      4
@@ -109,8 +114,10 @@ struct virtio_blk_config {
 /* Get device ID command */
 #define VIRTIO_BLK_T_GET_ID    8
 
+#ifndef VIRTIO_BLK_NO_LEGACY
 /* Barrier before this op. */
 #define VIRTIO_BLK_T_BARRIER    0x80000000
+#endif /* !VIRTIO_BLK_NO_LEGACY */
 
 /* This is the first element of the read scatter-gather list. */
 struct virtio_blk_outhdr {
@@ -122,12 +129,14 @@ struct virtio_blk_outhdr {
         __virtio64 sector;
 };
 
+#ifndef VIRTIO_BLK_NO_LEGACY
 struct virtio_scsi_inhdr {
         __virtio32 errors;
         __virtio32 data_len;
         __virtio32 sense_len;
         __virtio32 residual;
 };
+#endif /* !VIRTIO_BLK_NO_LEGACY */
 
 /* And this is the final byte of the write scatter-gather list. */
 #define VIRTIO_BLK_S_OK         0
diff --git a/include/uapi/linux/virtio_config.h b/include/uapi/linux/virtio_config.h
index a6d0cdeaacd4..c18264df9504 100644
--- a/include/uapi/linux/virtio_config.h
+++ b/include/uapi/linux/virtio_config.h
@@ -49,12 +49,14 @@
 #define VIRTIO_TRANSPORT_F_START        28
 #define VIRTIO_TRANSPORT_F_END          33
 
+#ifndef VIRTIO_CONFIG_NO_LEGACY
 /* Do we get callbacks when the ring is completely used, even if we've
  * suppressed them? */
 #define VIRTIO_F_NOTIFY_ON_EMPTY        24
 
 /* Can the device handle any descriptor layout? */
 #define VIRTIO_F_ANY_LAYOUT             27
+#endif /* VIRTIO_CONFIG_NO_LEGACY */
 
 /* v1.0 compliant. */
 #define VIRTIO_F_VERSION_1              32
diff --git a/include/uapi/linux/virtio_net.h b/include/uapi/linux/virtio_net.h
index b5f1677b291c..7bbee79ca293 100644
--- a/include/uapi/linux/virtio_net.h
+++ b/include/uapi/linux/virtio_net.h
@@ -35,7 +35,6 @@
 #define VIRTIO_NET_F_CSUM       0       /* Host handles pkts w/ partial csum */
 #define VIRTIO_NET_F_GUEST_CSUM 1       /* Guest handles pkts w/ partial csum */
 #define VIRTIO_NET_F_MAC        5       /* Host has given MAC address. */
-#define VIRTIO_NET_F_GSO        6       /* Host handles pkts w/ any GSO type */
 #define VIRTIO_NET_F_GUEST_TSO4 7       /* Guest can handle TSOv4 in. */
 #define VIRTIO_NET_F_GUEST_TSO6 8       /* Guest can handle TSOv6 in. */
 #define VIRTIO_NET_F_GUEST_ECN  9       /* Guest can handle TSO[6] w/ ECN in. */
@@ -56,6 +55,10 @@
                                          * Steering */
 #define VIRTIO_NET_F_CTRL_MAC_ADDR 23   /* Set MAC address */
 
+#ifndef VIRTIO_NET_NO_LEGACY
+#define VIRTIO_NET_F_GSO        6       /* Host handles pkts w/ any GSO type */
+#endif /* VIRTIO_NET_NO_LEGACY */
+
 #define VIRTIO_NET_S_LINK_UP    1       /* Link is up */
 #define VIRTIO_NET_S_ANNOUNCE   2       /* Announcement is needed */
 
@@ -71,19 +74,39 @@ struct virtio_net_config {
         __u16 max_virtqueue_pairs;
 } __attribute__((packed));
 
+/*
+ * This header comes first in the scatter-gather list.  If you don't
+ * specify GSO or CSUM features, you can simply ignore the header.
+ *
+ * This is bitwise-equivalent to the legacy struct virtio_net_hdr_mrg_rxbuf,
+ * only flattened.
+ */
+struct virtio_net_hdr_v1 {
+#define VIRTIO_NET_HDR_F_NEEDS_CSUM     1       /* Use csum_start, csum_offset */
+#define VIRTIO_NET_HDR_F_DATA_VALID     2       /* Csum is valid */
+        __u8 flags;
+#define VIRTIO_NET_HDR_GSO_NONE         0       /* Not a GSO frame */
+#define VIRTIO_NET_HDR_GSO_TCPV4        1       /* GSO frame, IPv4 TCP (TSO) */
+#define VIRTIO_NET_HDR_GSO_UDP          3       /* GSO frame, IPv4 UDP (UFO) */
+#define VIRTIO_NET_HDR_GSO_TCPV6        4       /* GSO frame, IPv6 TCP */
+#define VIRTIO_NET_HDR_GSO_ECN          0x80    /* TCP has ECN set */
+        __u8 gso_type;
+        __virtio16 hdr_len;     /* Ethernet + IP + tcp/udp hdrs */
+        __virtio16 gso_size;    /* Bytes to append to hdr_len per frame */
+        __virtio16 csum_start;  /* Position to start checksumming from */
+        __virtio16 csum_offset; /* Offset after that to place checksum */
+        __virtio16 num_buffers; /* Number of merged rx buffers */
+};
+
+#ifndef VIRTIO_NET_NO_LEGACY
 /* This header comes first in the scatter-gather list.
- * If VIRTIO_F_ANY_LAYOUT is not negotiated, it must
+ * For legacy virtio, if VIRTIO_F_ANY_LAYOUT is not negotiated, it must
  * be the first element of the scatter-gather list.  If you don't
  * specify GSO or CSUM features, you can simply ignore the header. */
 struct virtio_net_hdr {
-#define VIRTIO_NET_HDR_F_NEEDS_CSUM     1       // Use csum_start, csum_offset
-#define VIRTIO_NET_HDR_F_DATA_VALID     2       // Csum is valid
+        /* See VIRTIO_NET_HDR_F_* */
         __u8 flags;
-#define VIRTIO_NET_HDR_GSO_NONE         0       // Not a GSO frame
-#define VIRTIO_NET_HDR_GSO_TCPV4        1       // GSO frame, IPv4 TCP (TSO)
-#define VIRTIO_NET_HDR_GSO_UDP          3       // GSO frame, IPv4 UDP (UFO)
-#define VIRTIO_NET_HDR_GSO_TCPV6        4       // GSO frame, IPv6 TCP
-#define VIRTIO_NET_HDR_GSO_ECN          0x80    // TCP has ECN set
+        /* See VIRTIO_NET_HDR_GSO_* */
         __u8 gso_type;
         __virtio16 hdr_len;             /* Ethernet + IP + tcp/udp hdrs */
         __virtio16 gso_size;            /* Bytes to append to hdr_len per frame */
@@ -97,6 +120,7 @@ struct virtio_net_hdr_mrg_rxbuf {
         struct virtio_net_hdr hdr;
         __virtio16 num_buffers; /* Number of merged rx buffers */
 };
+#endif /* ...VIRTIO_NET_NO_LEGACY */
 
 /*
  * Control virtqueue data structures
diff --git a/include/uapi/linux/virtio_pci.h b/include/uapi/linux/virtio_pci.h
index 35b552c7f330..75301468359f 100644
--- a/include/uapi/linux/virtio_pci.h
+++ b/include/uapi/linux/virtio_pci.h
@@ -39,7 +39,7 @@
 #ifndef _LINUX_VIRTIO_PCI_H
 #define _LINUX_VIRTIO_PCI_H
 
-#include <linux/virtio_config.h>
+#include <linux/types.h>
 
 #ifndef VIRTIO_PCI_NO_LEGACY
 
@@ -99,4 +99,95 @@
 /* Vector value used to disable MSI for queue */
 #define VIRTIO_MSI_NO_VECTOR            0xffff
 
+#ifndef VIRTIO_PCI_NO_MODERN
+
+/* IDs for different capabilities.  Must all exist. */
+
+/* Common configuration */
+#define VIRTIO_PCI_CAP_COMMON_CFG       1
+/* Notifications */
+#define VIRTIO_PCI_CAP_NOTIFY_CFG       2
+/* ISR access */
+#define VIRTIO_PCI_CAP_ISR_CFG          3
+/* Device specific configuration */
+#define VIRTIO_PCI_CAP_DEVICE_CFG       4
+/* PCI configuration access */
+#define VIRTIO_PCI_CAP_PCI_CFG          5
+
+/* This is the PCI capability header: */
+struct virtio_pci_cap {
+        __u8 cap_vndr;          /* Generic PCI field: PCI_CAP_ID_VNDR */
+        __u8 cap_next;          /* Generic PCI field: next ptr. */
+        __u8 cap_len;           /* Generic PCI field: capability length */
+        __u8 cfg_type;          /* Identifies the structure. */
+        __u8 bar;               /* Where to find it. */
+        __u8 padding[3];        /* Pad to full dword. */
+        __le32 offset;          /* Offset within bar. */
+        __le32 length;          /* Length of the structure, in bytes. */
+};
+
+struct virtio_pci_notify_cap {
+        struct virtio_pci_cap cap;
+        __le32 notify_off_multiplier;   /* Multiplier for queue_notify_off. */
+};
+
+/* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */
+struct virtio_pci_common_cfg {
+        /* About the whole device. */
+        __le32 device_feature_select;   /* read-write */
+        __le32 device_feature;          /* read-only */
+        __le32 guest_feature_select;    /* read-write */
+        __le32 guest_feature;           /* read-write */
+        __le16 msix_config;             /* read-write */
+        __le16 num_queues;              /* read-only */
+        __u8 device_status;             /* read-write */
+        __u8 config_generation;         /* read-only */
+
+        /* About a specific virtqueue. */
+        __le16 queue_select;            /* read-write */
+        __le16 queue_size;              /* read-write, power of 2. */
+        __le16 queue_msix_vector;       /* read-write */
+        __le16 queue_enable;            /* read-write */
+        __le16 queue_notify_off;        /* read-only */
+        __le32 queue_desc_lo;           /* read-write */
+        __le32 queue_desc_hi;           /* read-write */
+        __le32 queue_avail_lo;          /* read-write */
+        __le32 queue_avail_hi;          /* read-write */
+        __le32 queue_used_lo;           /* read-write */
+        __le32 queue_used_hi;           /* read-write */
+};
+
+/* Macro versions of offsets for the Old Timers! */
+#define VIRTIO_PCI_CAP_VNDR             0
+#define VIRTIO_PCI_CAP_NEXT             1
+#define VIRTIO_PCI_CAP_LEN              2
+#define VIRTIO_PCI_CAP_CFG_TYPE         3
+#define VIRTIO_PCI_CAP_BAR              4
+#define VIRTIO_PCI_CAP_OFFSET           8
+#define VIRTIO_PCI_CAP_LENGTH           12
+
+#define VIRTIO_PCI_NOTIFY_CAP_MULT      16
+
+#define VIRTIO_PCI_COMMON_DFSELECT      0
+#define VIRTIO_PCI_COMMON_DF            4
+#define VIRTIO_PCI_COMMON_GFSELECT      8
+#define VIRTIO_PCI_COMMON_GF            12
+#define VIRTIO_PCI_COMMON_MSIX          16
+#define VIRTIO_PCI_COMMON_NUMQ          18
+#define VIRTIO_PCI_COMMON_STATUS        20
+#define VIRTIO_PCI_COMMON_CFGGENERATION 21
+#define VIRTIO_PCI_COMMON_Q_SELECT      22
+#define VIRTIO_PCI_COMMON_Q_SIZE        24
+#define VIRTIO_PCI_COMMON_Q_MSIX        26
+#define VIRTIO_PCI_COMMON_Q_ENABLE      28
+#define VIRTIO_PCI_COMMON_Q_NOFF        30
+#define VIRTIO_PCI_COMMON_Q_DESCLO      32
+#define VIRTIO_PCI_COMMON_Q_DESCHI      36
+#define VIRTIO_PCI_COMMON_Q_AVAILLO     40
+#define VIRTIO_PCI_COMMON_Q_AVAILHI     44
+#define VIRTIO_PCI_COMMON_Q_USEDLO      48
+#define VIRTIO_PCI_COMMON_Q_USEDHI      52
+
+#endif /* VIRTIO_PCI_NO_MODERN */
+
 #endif
diff --git a/include/uapi/rdma/ib_user_verbs.h b/include/uapi/rdma/ib_user_verbs.h
index 867cc5084afb..b513e662d8e4 100644
--- a/include/uapi/rdma/ib_user_verbs.h
+++ b/include/uapi/rdma/ib_user_verbs.h
@@ -90,6 +90,7 @@ enum {
 };
 
 enum {
+        IB_USER_VERBS_EX_CMD_QUERY_DEVICE = IB_USER_VERBS_CMD_QUERY_DEVICE,
         IB_USER_VERBS_EX_CMD_CREATE_FLOW = IB_USER_VERBS_CMD_THRESHOLD,
         IB_USER_VERBS_EX_CMD_DESTROY_FLOW,
 };
@@ -201,6 +202,28 @@ struct ib_uverbs_query_device_resp {
         __u8  reserved[4];
 };
 
+struct ib_uverbs_ex_query_device {
+        __u32 comp_mask;
+        __u32 reserved;
+};
+
+struct ib_uverbs_odp_caps {
+        __u64 general_caps;
+        struct {
+                __u32 rc_odp_caps;
+                __u32 uc_odp_caps;
+                __u32 ud_odp_caps;
+        } per_transport_caps;
+        __u32 reserved;
+};
+
+struct ib_uverbs_ex_query_device_resp {
+        struct ib_uverbs_query_device_resp base;
+        __u32 comp_mask;
+        __u32 response_length;
+        struct ib_uverbs_odp_caps odp_caps;
+};
+
 struct ib_uverbs_query_port {
         __u64 response;
         __u8  port_num;
diff --git a/include/xen/xen-ops.h b/include/xen/xen-ops.h
index 7491ee5d8164..83338210ee04 100644
--- a/include/xen/xen-ops.h
+++ b/include/xen/xen-ops.h
@@ -46,4 +46,30 @@ static inline efi_system_table_t __init *xen_efi_probe(void)
 }
 #endif
 
+#ifdef CONFIG_PREEMPT
+
+static inline void xen_preemptible_hcall_begin(void)
+{
+}
+
+static inline void xen_preemptible_hcall_end(void)
+{
+}
+
+#else
+
+DECLARE_PER_CPU(bool, xen_in_preemptible_hcall);
+
+static inline void xen_preemptible_hcall_begin(void)
+{
+        __this_cpu_write(xen_in_preemptible_hcall, true);
+}
+
+static inline void xen_preemptible_hcall_end(void)
+{
+        __this_cpu_write(xen_in_preemptible_hcall, false);
+}
+
+#endif /* CONFIG_PREEMPT */
+
 #endif /* INCLUDE_XEN_OPS_H */