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authorLinus Torvalds <torvalds@linux-foundation.org>2011-07-31 20:31:44 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-07-31 20:31:44 -0400
commit3da3f872aa175f59e20766ed30aaea67fd4fa7d1 (patch)
treea44697edf5eebd02b6f159a7ab824a45730134b4 /include/linux
parent968e75fc13b6d582f42ce44172e13ba58157e11f (diff)
parente178ccb33569da17dc897a08a3865441b813bdfb (diff)
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (46 commits) mfd: Fix mismatch in twl4030 mutex lock-unlock mfd: twl6030-pwm.c needs MODULE_LICENSE mfd: Fix the omap-usb-host clock API usage on usbhs_disable() mfd: Acknowledge WM8994 IRQs before reporting mfd: Acknowlege all WM831x IRQs before we handle them mfd: Avoid two assignments if failures happen in tps65910_i2c_probe regulator: Storing tps65912 error codes in u8 mfd: Don't leak init_data in tps65910_i2c_probe regulator: aat2870: Add AAT2870 regulator driver backlight: Add AAT2870 backlight driver mfd: Add AAT2870 mfd driver mfd: Remove dead code from max8997-irq mfd: Move TPS55910 Kconfig option mfd: Fix missing stmpe kerneldoc mfd: Fix off-by-one value range checking for tps65912_i2c_write mfd: Add devices for WM831x clocking module mfd: Remove comp{1,2}_threshold sysfs entries in tps65911_comparator_remove mfd: Don't ask about the TPS65912 core driver in Kconfig mfd: Fix off by one in WM831x IRQ code mfd: Add tps65921 support from twl-core ...
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/mfd/aat2870.h181
-rw-r--r--include/linux/mfd/ab8500.h8
-rw-r--r--include/linux/mfd/stmpe.h3
-rw-r--r--include/linux/mfd/tps65910.h1
-rw-r--r--include/linux/mfd/tps65912.h327
-rw-r--r--include/linux/mfd/wm831x/core.h119
-rw-r--r--include/linux/mfd/wm831x/pdata.h3
7 files changed, 633 insertions, 9 deletions
diff --git a/include/linux/mfd/aat2870.h b/include/linux/mfd/aat2870.h
new file mode 100644
index 000000000000..89212df05622
--- /dev/null
+++ b/include/linux/mfd/aat2870.h
@@ -0,0 +1,181 @@
1/*
2 * linux/include/linux/mfd/aat2870.h
3 *
4 * Copyright (c) 2011, NVIDIA Corporation.
5 * Author: Jin Park <jinyoungp@nvidia.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 */
21
22#ifndef __LINUX_MFD_AAT2870_H
23#define __LINUX_MFD_AAT2870_H
24
25#include <linux/debugfs.h>
26#include <linux/i2c.h>
27
28/* Register offsets */
29#define AAT2870_BL_CH_EN 0x00
30#define AAT2870_BLM 0x01
31#define AAT2870_BLS 0x02
32#define AAT2870_BL1 0x03
33#define AAT2870_BL2 0x04
34#define AAT2870_BL3 0x05
35#define AAT2870_BL4 0x06
36#define AAT2870_BL5 0x07
37#define AAT2870_BL6 0x08
38#define AAT2870_BL7 0x09
39#define AAT2870_BL8 0x0A
40#define AAT2870_FLR 0x0B
41#define AAT2870_FM 0x0C
42#define AAT2870_FS 0x0D
43#define AAT2870_ALS_CFG0 0x0E
44#define AAT2870_ALS_CFG1 0x0F
45#define AAT2870_ALS_CFG2 0x10
46#define AAT2870_AMB 0x11
47#define AAT2870_ALS0 0x12
48#define AAT2870_ALS1 0x13
49#define AAT2870_ALS2 0x14
50#define AAT2870_ALS3 0x15
51#define AAT2870_ALS4 0x16
52#define AAT2870_ALS5 0x17
53#define AAT2870_ALS6 0x18
54#define AAT2870_ALS7 0x19
55#define AAT2870_ALS8 0x1A
56#define AAT2870_ALS9 0x1B
57#define AAT2870_ALSA 0x1C
58#define AAT2870_ALSB 0x1D
59#define AAT2870_ALSC 0x1E
60#define AAT2870_ALSD 0x1F
61#define AAT2870_ALSE 0x20
62#define AAT2870_ALSF 0x21
63#define AAT2870_SUB_SET 0x22
64#define AAT2870_SUB_CTRL 0x23
65#define AAT2870_LDO_AB 0x24
66#define AAT2870_LDO_CD 0x25
67#define AAT2870_LDO_EN 0x26
68#define AAT2870_REG_NUM 0x27
69
70/* Device IDs */
71enum aat2870_id {
72 AAT2870_ID_BL,
73 AAT2870_ID_LDOA,
74 AAT2870_ID_LDOB,
75 AAT2870_ID_LDOC,
76 AAT2870_ID_LDOD
77};
78
79/* Backlight channels */
80#define AAT2870_BL_CH1 0x01
81#define AAT2870_BL_CH2 0x02
82#define AAT2870_BL_CH3 0x04
83#define AAT2870_BL_CH4 0x08
84#define AAT2870_BL_CH5 0x10
85#define AAT2870_BL_CH6 0x20
86#define AAT2870_BL_CH7 0x40
87#define AAT2870_BL_CH8 0x80
88#define AAT2870_BL_CH_ALL 0xFF
89
90/* Backlight current magnitude (mA) */
91enum aat2870_current {
92 AAT2870_CURRENT_0_45,
93 AAT2870_CURRENT_0_90,
94 AAT2870_CURRENT_1_80,
95 AAT2870_CURRENT_2_70,
96 AAT2870_CURRENT_3_60,
97 AAT2870_CURRENT_4_50,
98 AAT2870_CURRENT_5_40,
99 AAT2870_CURRENT_6_30,
100 AAT2870_CURRENT_7_20,
101 AAT2870_CURRENT_8_10,
102 AAT2870_CURRENT_9_00,
103 AAT2870_CURRENT_9_90,
104 AAT2870_CURRENT_10_8,
105 AAT2870_CURRENT_11_7,
106 AAT2870_CURRENT_12_6,
107 AAT2870_CURRENT_13_5,
108 AAT2870_CURRENT_14_4,
109 AAT2870_CURRENT_15_3,
110 AAT2870_CURRENT_16_2,
111 AAT2870_CURRENT_17_1,
112 AAT2870_CURRENT_18_0,
113 AAT2870_CURRENT_18_9,
114 AAT2870_CURRENT_19_8,
115 AAT2870_CURRENT_20_7,
116 AAT2870_CURRENT_21_6,
117 AAT2870_CURRENT_22_5,
118 AAT2870_CURRENT_23_4,
119 AAT2870_CURRENT_24_3,
120 AAT2870_CURRENT_25_2,
121 AAT2870_CURRENT_26_1,
122 AAT2870_CURRENT_27_0,
123 AAT2870_CURRENT_27_9
124};
125
126struct aat2870_register {
127 bool readable;
128 bool writeable;
129 u8 value;
130};
131
132struct aat2870_data {
133 struct device *dev;
134 struct i2c_client *client;
135
136 struct mutex io_lock;
137 struct aat2870_register *reg_cache; /* register cache */
138 int en_pin; /* enable GPIO pin (if < 0, ignore this value) */
139 bool is_enable;
140
141 /* init and uninit for platform specified */
142 int (*init)(struct aat2870_data *aat2870);
143 void (*uninit)(struct aat2870_data *aat2870);
144
145 /* i2c io funcntions */
146 int (*read)(struct aat2870_data *aat2870, u8 addr, u8 *val);
147 int (*write)(struct aat2870_data *aat2870, u8 addr, u8 val);
148 int (*update)(struct aat2870_data *aat2870, u8 addr, u8 mask, u8 val);
149
150 /* for debugfs */
151 struct dentry *dentry_root;
152 struct dentry *dentry_reg;
153};
154
155struct aat2870_subdev_info {
156 int id;
157 const char *name;
158 void *platform_data;
159};
160
161struct aat2870_platform_data {
162 int en_pin; /* enable GPIO pin (if < 0, ignore this value) */
163
164 struct aat2870_subdev_info *subdevs;
165 int num_subdevs;
166
167 /* init and uninit for platform specified */
168 int (*init)(struct aat2870_data *aat2870);
169 void (*uninit)(struct aat2870_data *aat2870);
170};
171
172struct aat2870_bl_platform_data {
173 /* backlight channels, default is AAT2870_BL_CH_ALL */
174 int channels;
175 /* backlight current magnitude, default is AAT2870_CURRENT_27_9 */
176 int max_current;
177 /* maximum brightness, default is 255 */
178 int max_brightness;
179};
180
181#endif /* __LINUX_MFD_AAT2870_H */
diff --git a/include/linux/mfd/ab8500.h b/include/linux/mfd/ab8500.h
index b31843075198..838c6b487cc5 100644
--- a/include/linux/mfd/ab8500.h
+++ b/include/linux/mfd/ab8500.h
@@ -28,6 +28,7 @@
28#define AB8500_INTERRUPT 0xE 28#define AB8500_INTERRUPT 0xE
29#define AB8500_RTC 0xF 29#define AB8500_RTC 0xF
30#define AB8500_MISC 0x10 30#define AB8500_MISC 0x10
31#define AB8500_DEVELOPMENT 0x11
31#define AB8500_DEBUG 0x12 32#define AB8500_DEBUG 0x12
32#define AB8500_PROD_TEST 0x13 33#define AB8500_PROD_TEST 0x13
33#define AB8500_OTP_EMUL 0x15 34#define AB8500_OTP_EMUL 0x15
@@ -74,13 +75,6 @@
74#define AB8500_INT_ACC_DETECT_21DB_F 37 75#define AB8500_INT_ACC_DETECT_21DB_F 37
75#define AB8500_INT_ACC_DETECT_21DB_R 38 76#define AB8500_INT_ACC_DETECT_21DB_R 38
76#define AB8500_INT_GP_SW_ADC_CONV_END 39 77#define AB8500_INT_GP_SW_ADC_CONV_END 39
77#define AB8500_INT_ACC_DETECT_1DB_F 33
78#define AB8500_INT_ACC_DETECT_1DB_R 34
79#define AB8500_INT_ACC_DETECT_22DB_F 35
80#define AB8500_INT_ACC_DETECT_22DB_R 36
81#define AB8500_INT_ACC_DETECT_21DB_F 37
82#define AB8500_INT_ACC_DETECT_21DB_R 38
83#define AB8500_INT_GP_SW_ADC_CONV_END 39
84#define AB8500_INT_GPIO6R 40 78#define AB8500_INT_GPIO6R 40
85#define AB8500_INT_GPIO7R 41 79#define AB8500_INT_GPIO7R 41
86#define AB8500_INT_GPIO8R 42 80#define AB8500_INT_GPIO8R 42
diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h
index e762c270d8d4..be1af7c42e57 100644
--- a/include/linux/mfd/stmpe.h
+++ b/include/linux/mfd/stmpe.h
@@ -57,6 +57,7 @@ struct stmpe_variant_info;
57 * @irq_lock: IRQ bus lock 57 * @irq_lock: IRQ bus lock
58 * @dev: device, mostly for dev_dbg() 58 * @dev: device, mostly for dev_dbg()
59 * @i2c: i2c client 59 * @i2c: i2c client
60 * @partnum: part number
60 * @variant: the detected STMPE model number 61 * @variant: the detected STMPE model number
61 * @regs: list of addresses of registers which are at different addresses on 62 * @regs: list of addresses of registers which are at different addresses on
62 * different variants. Indexed by one of STMPE_IDX_*. 63 * different variants. Indexed by one of STMPE_IDX_*.
@@ -121,6 +122,8 @@ struct stmpe_keypad_platform_data {
121 * @norequest_mask: bitmask specifying which GPIOs should _not_ be 122 * @norequest_mask: bitmask specifying which GPIOs should _not_ be
122 * requestable due to different usage (e.g. touch, keypad) 123 * requestable due to different usage (e.g. touch, keypad)
123 * STMPE_GPIO_NOREQ_* macros can be used here. 124 * STMPE_GPIO_NOREQ_* macros can be used here.
125 * @setup: board specific setup callback.
126 * @remove: board specific remove callback
124 */ 127 */
125struct stmpe_gpio_platform_data { 128struct stmpe_gpio_platform_data {
126 int gpio_base; 129 int gpio_base;
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
index 73572c65d04f..82b4c8801a4f 100644
--- a/include/linux/mfd/tps65910.h
+++ b/include/linux/mfd/tps65910.h
@@ -791,6 +791,7 @@ int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
791void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base); 791void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
792int tps65910_irq_init(struct tps65910 *tps65910, int irq, 792int tps65910_irq_init(struct tps65910 *tps65910, int irq,
793 struct tps65910_platform_data *pdata); 793 struct tps65910_platform_data *pdata);
794int tps65910_irq_exit(struct tps65910 *tps65910);
794 795
795static inline int tps65910_chip_id(struct tps65910 *tps65910) 796static inline int tps65910_chip_id(struct tps65910 *tps65910)
796{ 797{
diff --git a/include/linux/mfd/tps65912.h b/include/linux/mfd/tps65912.h
new file mode 100644
index 000000000000..aaceab402ec5
--- /dev/null
+++ b/include/linux/mfd/tps65912.h
@@ -0,0 +1,327 @@
1/*
2 * tps65912.h -- TI TPS6591x
3 *
4 * Copyright 2011 Texas Instruments Inc.
5 *
6 * Author: Margarita Olaya <magi@slimlogic.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __LINUX_MFD_TPS65912_H
16#define __LINUX_MFD_TPS65912_H
17
18/* TPS regulator type list */
19#define REGULATOR_LDO 0
20#define REGULATOR_DCDC 1
21
22/*
23 * List of registers for TPS65912
24 */
25
26#define TPS65912_DCDC1_CTRL 0x00
27#define TPS65912_DCDC2_CTRL 0x01
28#define TPS65912_DCDC3_CTRL 0x02
29#define TPS65912_DCDC4_CTRL 0x03
30#define TPS65912_DCDC1_OP 0x04
31#define TPS65912_DCDC1_AVS 0x05
32#define TPS65912_DCDC1_LIMIT 0x06
33#define TPS65912_DCDC2_OP 0x07
34#define TPS65912_DCDC2_AVS 0x08
35#define TPS65912_DCDC2_LIMIT 0x09
36#define TPS65912_DCDC3_OP 0x0A
37#define TPS65912_DCDC3_AVS 0x0B
38#define TPS65912_DCDC3_LIMIT 0x0C
39#define TPS65912_DCDC4_OP 0x0D
40#define TPS65912_DCDC4_AVS 0x0E
41#define TPS65912_DCDC4_LIMIT 0x0F
42#define TPS65912_LDO1_OP 0x10
43#define TPS65912_LDO1_AVS 0x11
44#define TPS65912_LDO1_LIMIT 0x12
45#define TPS65912_LDO2_OP 0x13
46#define TPS65912_LDO2_AVS 0x14
47#define TPS65912_LDO2_LIMIT 0x15
48#define TPS65912_LDO3_OP 0x16
49#define TPS65912_LDO3_AVS 0x17
50#define TPS65912_LDO3_LIMIT 0x18
51#define TPS65912_LDO4_OP 0x19
52#define TPS65912_LDO4_AVS 0x1A
53#define TPS65912_LDO4_LIMIT 0x1B
54#define TPS65912_LDO5 0x1C
55#define TPS65912_LDO6 0x1D
56#define TPS65912_LDO7 0x1E
57#define TPS65912_LDO8 0x1F
58#define TPS65912_LDO9 0x20
59#define TPS65912_LDO10 0x21
60#define TPS65912_THRM 0x22
61#define TPS65912_CLK32OUT 0x23
62#define TPS65912_DEVCTRL 0x24
63#define TPS65912_DEVCTRL2 0x25
64#define TPS65912_I2C_SPI_CFG 0x26
65#define TPS65912_KEEP_ON 0x27
66#define TPS65912_KEEP_ON2 0x28
67#define TPS65912_SET_OFF1 0x29
68#define TPS65912_SET_OFF2 0x2A
69#define TPS65912_DEF_VOLT 0x2B
70#define TPS65912_DEF_VOLT_MAPPING 0x2C
71#define TPS65912_DISCHARGE 0x2D
72#define TPS65912_DISCHARGE2 0x2E
73#define TPS65912_EN1_SET1 0x2F
74#define TPS65912_EN1_SET2 0x30
75#define TPS65912_EN2_SET1 0x31
76#define TPS65912_EN2_SET2 0x32
77#define TPS65912_EN3_SET1 0x33
78#define TPS65912_EN3_SET2 0x34
79#define TPS65912_EN4_SET1 0x35
80#define TPS65912_EN4_SET2 0x36
81#define TPS65912_PGOOD 0x37
82#define TPS65912_PGOOD2 0x38
83#define TPS65912_INT_STS 0x39
84#define TPS65912_INT_MSK 0x3A
85#define TPS65912_INT_STS2 0x3B
86#define TPS65912_INT_MSK2 0x3C
87#define TPS65912_INT_STS3 0x3D
88#define TPS65912_INT_MSK3 0x3E
89#define TPS65912_INT_STS4 0x3F
90#define TPS65912_INT_MSK4 0x40
91#define TPS65912_GPIO1 0x41
92#define TPS65912_GPIO2 0x42
93#define TPS65912_GPIO3 0x43
94#define TPS65912_GPIO4 0x44
95#define TPS65912_GPIO5 0x45
96#define TPS65912_VMON 0x46
97#define TPS65912_LEDA_CTRL1 0x47
98#define TPS65912_LEDA_CTRL2 0x48
99#define TPS65912_LEDA_CTRL3 0x49
100#define TPS65912_LEDA_CTRL4 0x4A
101#define TPS65912_LEDA_CTRL5 0x4B
102#define TPS65912_LEDA_CTRL6 0x4C
103#define TPS65912_LEDA_CTRL7 0x4D
104#define TPS65912_LEDA_CTRL8 0x4E
105#define TPS65912_LEDB_CTRL1 0x4F
106#define TPS65912_LEDB_CTRL2 0x50
107#define TPS65912_LEDB_CTRL3 0x51
108#define TPS65912_LEDB_CTRL4 0x52
109#define TPS65912_LEDB_CTRL5 0x53
110#define TPS65912_LEDB_CTRL6 0x54
111#define TPS65912_LEDB_CTRL7 0x55
112#define TPS65912_LEDB_CTRL8 0x56
113#define TPS65912_LEDC_CTRL1 0x57
114#define TPS65912_LEDC_CTRL2 0x58
115#define TPS65912_LEDC_CTRL3 0x59
116#define TPS65912_LEDC_CTRL4 0x5A
117#define TPS65912_LEDC_CTRL5 0x5B
118#define TPS65912_LEDC_CTRL6 0x5C
119#define TPS65912_LEDC_CTRL7 0x5D
120#define TPS65912_LEDC_CTRL8 0x5E
121#define TPS65912_LED_RAMP_UP_TIME 0x5F
122#define TPS65912_LED_RAMP_DOWN_TIME 0x60
123#define TPS65912_LED_SEQ_EN 0x61
124#define TPS65912_LOADSWITCH 0x62
125#define TPS65912_SPARE 0x63
126#define TPS65912_VERNUM 0x64
127#define TPS6591X_MAX_REGISTER 0x64
128
129/* IRQ Definitions */
130#define TPS65912_IRQ_PWRHOLD_F 0
131#define TPS65912_IRQ_VMON 1
132#define TPS65912_IRQ_PWRON 2
133#define TPS65912_IRQ_PWRON_LP 3
134#define TPS65912_IRQ_PWRHOLD_R 4
135#define TPS65912_IRQ_HOTDIE 5
136#define TPS65912_IRQ_GPIO1_R 6
137#define TPS65912_IRQ_GPIO1_F 7
138#define TPS65912_IRQ_GPIO2_R 8
139#define TPS65912_IRQ_GPIO2_F 9
140#define TPS65912_IRQ_GPIO3_R 10
141#define TPS65912_IRQ_GPIO3_F 11
142#define TPS65912_IRQ_GPIO4_R 12
143#define TPS65912_IRQ_GPIO4_F 13
144#define TPS65912_IRQ_GPIO5_R 14
145#define TPS65912_IRQ_GPIO5_F 15
146#define TPS65912_IRQ_PGOOD_DCDC1 16
147#define TPS65912_IRQ_PGOOD_DCDC2 17
148#define TPS65912_IRQ_PGOOD_DCDC3 18
149#define TPS65912_IRQ_PGOOD_DCDC4 19
150#define TPS65912_IRQ_PGOOD_LDO1 20
151#define TPS65912_IRQ_PGOOD_LDO2 21
152#define TPS65912_IRQ_PGOOD_LDO3 22
153#define TPS65912_IRQ_PGOOD_LDO4 23
154#define TPS65912_IRQ_PGOOD_LDO5 24
155#define TPS65912_IRQ_PGOOD_LDO6 25
156#define TPS65912_IRQ_PGOOD_LDO7 26
157#define TPS65912_IRQ_PGOOD_LD08 27
158#define TPS65912_IRQ_PGOOD_LDO9 28
159#define TPS65912_IRQ_PGOOD_LDO10 29
160
161#define TPS65912_NUM_IRQ 30
162
163/* GPIO 1 and 2 Register Definitions */
164#define GPIO_SLEEP_MASK 0x80
165#define GPIO_SLEEP_SHIFT 7
166#define GPIO_DEB_MASK 0x10
167#define GPIO_DEB_SHIFT 4
168#define GPIO_CFG_MASK 0x04
169#define GPIO_CFG_SHIFT 2
170#define GPIO_STS_MASK 0x02
171#define GPIO_STS_SHIFT 1
172#define GPIO_SET_MASK 0x01
173#define GPIO_SET_SHIFT 0
174
175/* GPIO 3 Register Definitions */
176#define GPIO3_SLEEP_MASK 0x80
177#define GPIO3_SLEEP_SHIFT 7
178#define GPIO3_SEL_MASK 0x40
179#define GPIO3_SEL_SHIFT 6
180#define GPIO3_ODEN_MASK 0x20
181#define GPIO3_ODEN_SHIFT 5
182#define GPIO3_DEB_MASK 0x10
183#define GPIO3_DEB_SHIFT 4
184#define GPIO3_PDEN_MASK 0x08
185#define GPIO3_PDEN_SHIFT 3
186#define GPIO3_CFG_MASK 0x04
187#define GPIO3_CFG_SHIFT 2
188#define GPIO3_STS_MASK 0x02
189#define GPIO3_STS_SHIFT 1
190#define GPIO3_SET_MASK 0x01
191#define GPIO3_SET_SHIFT 0
192
193/* GPIO 4 Register Definitions */
194#define GPIO4_SLEEP_MASK 0x80
195#define GPIO4_SLEEP_SHIFT 7
196#define GPIO4_SEL_MASK 0x40
197#define GPIO4_SEL_SHIFT 6
198#define GPIO4_ODEN_MASK 0x20
199#define GPIO4_ODEN_SHIFT 5
200#define GPIO4_DEB_MASK 0x10
201#define GPIO4_DEB_SHIFT 4
202#define GPIO4_PDEN_MASK 0x08
203#define GPIO4_PDEN_SHIFT 3
204#define GPIO4_CFG_MASK 0x04
205#define GPIO4_CFG_SHIFT 2
206#define GPIO4_STS_MASK 0x02
207#define GPIO4_STS_SHIFT 1
208#define GPIO4_SET_MASK 0x01
209#define GPIO4_SET_SHIFT 0
210
211/* Register THERM (0x80) register.RegisterDescription */
212#define THERM_THERM_HD_MASK 0x20
213#define THERM_THERM_HD_SHIFT 5
214#define THERM_THERM_TS_MASK 0x10
215#define THERM_THERM_TS_SHIFT 4
216#define THERM_THERM_HDSEL_MASK 0x0C
217#define THERM_THERM_HDSEL_SHIFT 2
218#define THERM_RSVD1_MASK 0x02
219#define THERM_RSVD1_SHIFT 1
220#define THERM_THERM_STATE_MASK 0x01
221#define THERM_THERM_STATE_SHIFT 0
222
223/* Register DCDCCTRL1 register.RegisterDescription */
224#define DCDCCTRL_VCON_ENABLE_MASK 0x80
225#define DCDCCTRL_VCON_ENABLE_SHIFT 7
226#define DCDCCTRL_VCON_RANGE1_MASK 0x40
227#define DCDCCTRL_VCON_RANGE1_SHIFT 6
228#define DCDCCTRL_VCON_RANGE0_MASK 0x20
229#define DCDCCTRL_VCON_RANGE0_SHIFT 5
230#define DCDCCTRL_TSTEP2_MASK 0x10
231#define DCDCCTRL_TSTEP2_SHIFT 4
232#define DCDCCTRL_TSTEP1_MASK 0x08
233#define DCDCCTRL_TSTEP1_SHIFT 3
234#define DCDCCTRL_TSTEP0_MASK 0x04
235#define DCDCCTRL_TSTEP0_SHIFT 2
236#define DCDCCTRL_DCDC1_MODE_MASK 0x02
237#define DCDCCTRL_DCDC1_MODE_SHIFT 1
238
239/* Register DCDCCTRL2 and DCDCCTRL3 register.RegisterDescription */
240#define DCDCCTRL_TSTEP2_MASK 0x10
241#define DCDCCTRL_TSTEP2_SHIFT 4
242#define DCDCCTRL_TSTEP1_MASK 0x08
243#define DCDCCTRL_TSTEP1_SHIFT 3
244#define DCDCCTRL_TSTEP0_MASK 0x04
245#define DCDCCTRL_TSTEP0_SHIFT 2
246#define DCDCCTRL_DCDC_MODE_MASK 0x02
247#define DCDCCTRL_DCDC_MODE_SHIFT 1
248#define DCDCCTRL_RSVD0_MASK 0x01
249#define DCDCCTRL_RSVD0_SHIFT 0
250
251/* Register DCDCCTRL4 register.RegisterDescription */
252#define DCDCCTRL_RAMP_TIME_MASK 0x01
253#define DCDCCTRL_RAMP_TIME_SHIFT 0
254
255/* Register DCDCx_AVS */
256#define DCDC_AVS_ENABLE_MASK 0x80
257#define DCDC_AVS_ENABLE_SHIFT 7
258#define DCDC_AVS_ECO_MASK 0x40
259#define DCDC_AVS_ECO_SHIFT 6
260
261/* Register DCDCx_LIMIT */
262#define DCDC_LIMIT_RANGE_MASK 0xC0
263#define DCDC_LIMIT_RANGE_SHIFT 6
264#define DCDC_LIMIT_MAX_SEL_MASK 0x3F
265#define DCDC_LIMIT_MAX_SEL_SHIFT 0
266
267/**
268 * struct tps65912_board
269 * Board platform dat may be used to initialize regulators.
270 */
271struct tps65912_board {
272 int is_dcdc1_avs;
273 int is_dcdc2_avs;
274 int is_dcdc3_avs;
275 int is_dcdc4_avs;
276 int irq;
277 int irq_base;
278 int gpio_base;
279 struct regulator_init_data *tps65912_pmic_init_data;
280};
281
282/**
283 * struct tps65912 - tps65912 sub-driver chip access routines
284 */
285
286struct tps65912 {
287 struct device *dev;
288 /* for read/write acces */
289 struct mutex io_mutex;
290
291 /* For device IO interfaces: I2C or SPI */
292 void *control_data;
293
294 int (*read)(struct tps65912 *tps65912, u8 reg, int size, void *dest);
295 int (*write)(struct tps65912 *tps65912, u8 reg, int size, void *src);
296
297 /* Client devices */
298 struct tps65912_pmic *pmic;
299
300 /* GPIO Handling */
301 struct gpio_chip gpio;
302
303 /* IRQ Handling */
304 struct mutex irq_lock;
305 int chip_irq;
306 int irq_base;
307 int irq_num;
308 u32 irq_mask;
309};
310
311struct tps65912_platform_data {
312 int irq;
313 int irq_base;
314};
315
316unsigned int tps_chip(void);
317
318int tps65912_set_bits(struct tps65912 *tps65912, u8 reg, u8 mask);
319int tps65912_clear_bits(struct tps65912 *tps65912, u8 reg, u8 mask);
320int tps65912_reg_read(struct tps65912 *tps65912, u8 reg);
321int tps65912_reg_write(struct tps65912 *tps65912, u8 reg, u8 val);
322int tps65912_device_init(struct tps65912 *tps65912);
323void tps65912_device_exit(struct tps65912 *tps65912);
324int tps65912_irq_init(struct tps65912 *tps65912, int irq,
325 struct tps65912_platform_data *pdata);
326
327#endif /* __LINUX_MFD_TPS65912_H */
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index 0d515ee1c247..8dda8ded5cda 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -17,6 +17,7 @@
17 17
18#include <linux/completion.h> 18#include <linux/completion.h>
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/list.h>
20 21
21/* 22/*
22 * Register values. 23 * Register values.
@@ -234,9 +235,111 @@
234#define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */ 235#define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */
235#define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */ 236#define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */
236 237
238/*
239 * R16528 (0x4090) - Clock Control 1
240 */
241#define WM831X_CLKOUT_ENA 0x8000 /* CLKOUT_ENA */
242#define WM831X_CLKOUT_ENA_MASK 0x8000 /* CLKOUT_ENA */
243#define WM831X_CLKOUT_ENA_SHIFT 15 /* CLKOUT_ENA */
244#define WM831X_CLKOUT_ENA_WIDTH 1 /* CLKOUT_ENA */
245#define WM831X_CLKOUT_OD 0x2000 /* CLKOUT_OD */
246#define WM831X_CLKOUT_OD_MASK 0x2000 /* CLKOUT_OD */
247#define WM831X_CLKOUT_OD_SHIFT 13 /* CLKOUT_OD */
248#define WM831X_CLKOUT_OD_WIDTH 1 /* CLKOUT_OD */
249#define WM831X_CLKOUT_SLOT_MASK 0x0700 /* CLKOUT_SLOT - [10:8] */
250#define WM831X_CLKOUT_SLOT_SHIFT 8 /* CLKOUT_SLOT - [10:8] */
251#define WM831X_CLKOUT_SLOT_WIDTH 3 /* CLKOUT_SLOT - [10:8] */
252#define WM831X_CLKOUT_SLPSLOT_MASK 0x0070 /* CLKOUT_SLPSLOT - [6:4] */
253#define WM831X_CLKOUT_SLPSLOT_SHIFT 4 /* CLKOUT_SLPSLOT - [6:4] */
254#define WM831X_CLKOUT_SLPSLOT_WIDTH 3 /* CLKOUT_SLPSLOT - [6:4] */
255#define WM831X_CLKOUT_SRC 0x0001 /* CLKOUT_SRC */
256#define WM831X_CLKOUT_SRC_MASK 0x0001 /* CLKOUT_SRC */
257#define WM831X_CLKOUT_SRC_SHIFT 0 /* CLKOUT_SRC */
258#define WM831X_CLKOUT_SRC_WIDTH 1 /* CLKOUT_SRC */
259
260/*
261 * R16529 (0x4091) - Clock Control 2
262 */
263#define WM831X_XTAL_INH 0x8000 /* XTAL_INH */
264#define WM831X_XTAL_INH_MASK 0x8000 /* XTAL_INH */
265#define WM831X_XTAL_INH_SHIFT 15 /* XTAL_INH */
266#define WM831X_XTAL_INH_WIDTH 1 /* XTAL_INH */
267#define WM831X_XTAL_ENA 0x2000 /* XTAL_ENA */
268#define WM831X_XTAL_ENA_MASK 0x2000 /* XTAL_ENA */
269#define WM831X_XTAL_ENA_SHIFT 13 /* XTAL_ENA */
270#define WM831X_XTAL_ENA_WIDTH 1 /* XTAL_ENA */
271#define WM831X_XTAL_BKUPENA 0x1000 /* XTAL_BKUPENA */
272#define WM831X_XTAL_BKUPENA_MASK 0x1000 /* XTAL_BKUPENA */
273#define WM831X_XTAL_BKUPENA_SHIFT 12 /* XTAL_BKUPENA */
274#define WM831X_XTAL_BKUPENA_WIDTH 1 /* XTAL_BKUPENA */
275#define WM831X_FLL_AUTO 0x0080 /* FLL_AUTO */
276#define WM831X_FLL_AUTO_MASK 0x0080 /* FLL_AUTO */
277#define WM831X_FLL_AUTO_SHIFT 7 /* FLL_AUTO */
278#define WM831X_FLL_AUTO_WIDTH 1 /* FLL_AUTO */
279#define WM831X_FLL_AUTO_FREQ_MASK 0x0007 /* FLL_AUTO_FREQ - [2:0] */
280#define WM831X_FLL_AUTO_FREQ_SHIFT 0 /* FLL_AUTO_FREQ - [2:0] */
281#define WM831X_FLL_AUTO_FREQ_WIDTH 3 /* FLL_AUTO_FREQ - [2:0] */
282
283/*
284 * R16530 (0x4092) - FLL Control 1
285 */
286#define WM831X_FLL_FRAC 0x0004 /* FLL_FRAC */
287#define WM831X_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */
288#define WM831X_FLL_FRAC_SHIFT 2 /* FLL_FRAC */
289#define WM831X_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
290#define WM831X_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */
291#define WM831X_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */
292#define WM831X_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */
293#define WM831X_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */
294#define WM831X_FLL_ENA 0x0001 /* FLL_ENA */
295#define WM831X_FLL_ENA_MASK 0x0001 /* FLL_ENA */
296#define WM831X_FLL_ENA_SHIFT 0 /* FLL_ENA */
297#define WM831X_FLL_ENA_WIDTH 1 /* FLL_ENA */
298
299/*
300 * R16531 (0x4093) - FLL Control 2
301 */
302#define WM831X_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */
303#define WM831X_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */
304#define WM831X_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */
305#define WM831X_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */
306#define WM831X_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */
307#define WM831X_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */
308#define WM831X_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
309#define WM831X_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
310#define WM831X_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
311
312/*
313 * R16532 (0x4094) - FLL Control 3
314 */
315#define WM831X_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
316#define WM831X_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
317#define WM831X_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
318
319/*
320 * R16533 (0x4095) - FLL Control 4
321 */
322#define WM831X_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
323#define WM831X_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
324#define WM831X_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
325#define WM831X_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */
326#define WM831X_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */
327#define WM831X_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */
328
329/*
330 * R16534 (0x4096) - FLL Control 5
331 */
332#define WM831X_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */
333#define WM831X_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */
334#define WM831X_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */
335#define WM831X_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */
336#define WM831X_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */
337#define WM831X_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */
338
237struct regulator_dev; 339struct regulator_dev;
238 340
239#define WM831X_NUM_IRQ_REGS 5 341#define WM831X_NUM_IRQ_REGS 5
342#define WM831X_NUM_GPIO_REGS 16
240 343
241enum wm831x_parent { 344enum wm831x_parent {
242 WM8310 = 0x8310, 345 WM8310 = 0x8310,
@@ -248,6 +351,12 @@ enum wm831x_parent {
248 WM8326 = 0x8326, 351 WM8326 = 0x8326,
249}; 352};
250 353
354struct wm831x;
355enum wm831x_auxadc;
356
357typedef int (*wm831x_auxadc_read_fn)(struct wm831x *wm831x,
358 enum wm831x_auxadc input);
359
251struct wm831x { 360struct wm831x {
252 struct mutex io_lock; 361 struct mutex io_lock;
253 362
@@ -261,7 +370,7 @@ struct wm831x {
261 370
262 int irq; /* Our chip IRQ */ 371 int irq; /* Our chip IRQ */
263 struct mutex irq_lock; 372 struct mutex irq_lock;
264 unsigned int irq_base; 373 int irq_base;
265 int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */ 374 int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */
266 int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */ 375 int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
267 376
@@ -272,8 +381,13 @@ struct wm831x {
272 381
273 int num_gpio; 382 int num_gpio;
274 383
384 /* Used by the interrupt controller code to post writes */
385 int gpio_update[WM831X_NUM_GPIO_REGS];
386
275 struct mutex auxadc_lock; 387 struct mutex auxadc_lock;
276 struct completion auxadc_done; 388 struct list_head auxadc_pending;
389 u16 auxadc_active;
390 wm831x_auxadc_read_fn auxadc_read;
277 391
278 /* The WM831x has a security key blocking access to certain 392 /* The WM831x has a security key blocking access to certain
279 * registers. The mutex is taken by the accessors for locking 393 * registers. The mutex is taken by the accessors for locking
@@ -300,5 +414,6 @@ void wm831x_device_exit(struct wm831x *wm831x);
300int wm831x_device_suspend(struct wm831x *wm831x); 414int wm831x_device_suspend(struct wm831x *wm831x);
301int wm831x_irq_init(struct wm831x *wm831x, int irq); 415int wm831x_irq_init(struct wm831x *wm831x, int irq);
302void wm831x_irq_exit(struct wm831x *wm831x); 416void wm831x_irq_exit(struct wm831x *wm831x);
417void wm831x_auxadc_init(struct wm831x *wm831x);
303 418
304#endif 419#endif
diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h
index ff42d700293f..0ba24599fe51 100644
--- a/include/linux/mfd/wm831x/pdata.h
+++ b/include/linux/mfd/wm831x/pdata.h
@@ -120,6 +120,9 @@ struct wm831x_pdata {
120 /** Put the /IRQ line into CMOS mode */ 120 /** Put the /IRQ line into CMOS mode */
121 bool irq_cmos; 121 bool irq_cmos;
122 122
123 /** Disable the touchscreen */
124 bool disable_touch;
125
123 int irq_base; 126 int irq_base;
124 int gpio_base; 127 int gpio_base;
125 int gpio_defaults[WM831X_GPIO_NUM]; 128 int gpio_defaults[WM831X_GPIO_NUM];
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-31 05:02:14 -0400