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| author | Alexander Graf <agraf@suse.de> | 2013-08-28 18:41:59 -0400 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-08-28 18:41:59 -0400 |
| commit | bf550fc93d9855872a95e69e4002256110d89858 (patch) | |
| tree | 10876bb4304bffe54c4160a132e7b8de6577ac4e /include/linux/mlx4 | |
| parent | 7e48c101e0c53e6095c5f4f5e63d14df50aae8fc (diff) | |
| parent | cc2df20c7c4ce594c3e17e9cc260c330646012c8 (diff) | |
Merge remote-tracking branch 'origin/next' into kvm-ppc-next
Conflicts:
mm/Kconfig
CMA DMA split and ZSWAP introduction were conflicting, fix up manually.
Diffstat (limited to 'include/linux/mlx4')
| -rw-r--r-- | include/linux/mlx4/cmd.h | 3 | ||||
| -rw-r--r-- | include/linux/mlx4/device.h | 3 | ||||
| -rw-r--r-- | include/linux/mlx4/qp.h | 36 |
3 files changed, 40 insertions, 2 deletions
diff --git a/include/linux/mlx4/cmd.h b/include/linux/mlx4/cmd.h index adf6e0648f20..bb1c8096a7eb 100644 --- a/include/linux/mlx4/cmd.h +++ b/include/linux/mlx4/cmd.h | |||
| @@ -111,6 +111,7 @@ enum { | |||
| 111 | MLX4_CMD_INIT2INIT_QP = 0x2d, | 111 | MLX4_CMD_INIT2INIT_QP = 0x2d, |
| 112 | MLX4_CMD_SUSPEND_QP = 0x32, | 112 | MLX4_CMD_SUSPEND_QP = 0x32, |
| 113 | MLX4_CMD_UNSUSPEND_QP = 0x33, | 113 | MLX4_CMD_UNSUSPEND_QP = 0x33, |
| 114 | MLX4_CMD_UPDATE_QP = 0x61, | ||
| 114 | /* special QP and management commands */ | 115 | /* special QP and management commands */ |
| 115 | MLX4_CMD_CONF_SPECIAL_QP = 0x23, | 116 | MLX4_CMD_CONF_SPECIAL_QP = 0x23, |
| 116 | MLX4_CMD_MAD_IFC = 0x24, | 117 | MLX4_CMD_MAD_IFC = 0x24, |
| @@ -237,7 +238,7 @@ int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac); | |||
| 237 | int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos); | 238 | int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos); |
| 238 | int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting); | 239 | int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting); |
| 239 | int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf); | 240 | int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf); |
| 240 | 241 | int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state); | |
| 241 | 242 | ||
| 242 | #define MLX4_COMM_GET_IF_REV(cmd_chan_ver) (u8)((cmd_chan_ver) >> 8) | 243 | #define MLX4_COMM_GET_IF_REV(cmd_chan_ver) (u8)((cmd_chan_ver) >> 8) |
| 243 | 244 | ||
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h index a51b0134ce18..52c23a892bab 100644 --- a/include/linux/mlx4/device.h +++ b/include/linux/mlx4/device.h | |||
| @@ -157,7 +157,8 @@ enum { | |||
| 157 | MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN = 1LL << 4, | 157 | MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN = 1LL << 4, |
| 158 | MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, | 158 | MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, |
| 159 | MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, | 159 | MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, |
| 160 | MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7 | 160 | MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, |
| 161 | MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8 | ||
| 161 | }; | 162 | }; |
| 162 | 163 | ||
| 163 | enum { | 164 | enum { |
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h index 352eec9df1b8..262deac02c9e 100644 --- a/include/linux/mlx4/qp.h +++ b/include/linux/mlx4/qp.h | |||
| @@ -152,6 +152,8 @@ enum { /* fl */ | |||
| 152 | }; | 152 | }; |
| 153 | enum { /* vlan_control */ | 153 | enum { /* vlan_control */ |
| 154 | MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6, | 154 | MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6, |
| 155 | MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED = 1 << 5, /* 802.1p priority tag */ | ||
| 156 | MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED = 1 << 4, | ||
| 155 | MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2, | 157 | MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2, |
| 156 | MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */ | 158 | MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */ |
| 157 | MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0 | 159 | MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0 |
| @@ -206,6 +208,40 @@ struct mlx4_qp_context { | |||
| 206 | u32 reserved5[10]; | 208 | u32 reserved5[10]; |
| 207 | }; | 209 | }; |
| 208 | 210 | ||
| 211 | struct mlx4_update_qp_context { | ||
| 212 | __be64 qp_mask; | ||
| 213 | __be64 primary_addr_path_mask; | ||
| 214 | __be64 secondary_addr_path_mask; | ||
| 215 | u64 reserved1; | ||
| 216 | struct mlx4_qp_context qp_context; | ||
| 217 | u64 reserved2[58]; | ||
| 218 | }; | ||
| 219 | |||
| 220 | enum { | ||
| 221 | MLX4_UPD_QP_MASK_PM_STATE = 32, | ||
| 222 | MLX4_UPD_QP_MASK_VSD = 33, | ||
| 223 | }; | ||
| 224 | |||
| 225 | enum { | ||
| 226 | MLX4_UPD_QP_PATH_MASK_PKEY_INDEX = 0 + 32, | ||
| 227 | MLX4_UPD_QP_PATH_MASK_FSM = 1 + 32, | ||
| 228 | MLX4_UPD_QP_PATH_MASK_MAC_INDEX = 2 + 32, | ||
| 229 | MLX4_UPD_QP_PATH_MASK_FVL = 3 + 32, | ||
| 230 | MLX4_UPD_QP_PATH_MASK_CV = 4 + 32, | ||
| 231 | MLX4_UPD_QP_PATH_MASK_VLAN_INDEX = 5 + 32, | ||
| 232 | MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN = 6 + 32, | ||
| 233 | MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32, | ||
| 234 | MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P = 8 + 32, | ||
| 235 | MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED = 9 + 32, | ||
| 236 | MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32, | ||
| 237 | MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P = 11 + 32, | ||
| 238 | MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED = 12 + 32, | ||
| 239 | MLX4_UPD_QP_PATH_MASK_FEUP = 13 + 32, | ||
| 240 | MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32, | ||
| 241 | MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32, | ||
| 242 | MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32, | ||
| 243 | }; | ||
| 244 | |||
| 209 | enum { /* param3 */ | 245 | enum { /* param3 */ |
| 210 | MLX4_STRIP_VLAN = 1 << 30 | 246 | MLX4_STRIP_VLAN = 1 << 30 |
| 211 | }; | 247 | }; |
