aboutsummaryrefslogtreecommitdiffstats
path: root/include/linux/mfd
diff options
context:
space:
mode:
authorDmitry Torokhov <dmitry.torokhov@gmail.com>2011-07-27 03:54:47 -0400
committerDmitry Torokhov <dmitry.torokhov@gmail.com>2011-07-27 03:54:47 -0400
commitaa7eb8e78d8ecd6cd0475d86ea8385ff9cb47ece (patch)
tree3f9e98fadd5124fb05e8f6f9b06aa23698d4f215 /include/linux/mfd
parentcca8edfd2ec2a34d9f50f593bc753bb11e1bc1f5 (diff)
parent3c6b50141ef9f0a8844bf1357b80c0cdf518bf05 (diff)
Merge branch 'next' into for-linus
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/88pm860x.h6
-rw-r--r--include/linux/mfd/abx500.h8
-rw-r--r--include/linux/mfd/asic3.h23
-rw-r--r--include/linux/mfd/core.h23
-rw-r--r--include/linux/mfd/db5500-prcmu.h45
-rw-r--r--include/linux/mfd/db8500-prcmu.h978
-rw-r--r--include/linux/mfd/max8997-private.h4
-rw-r--r--include/linux/mfd/pm8xxx/core.h81
-rw-r--r--include/linux/mfd/pm8xxx/irq.h59
-rw-r--r--include/linux/mfd/pm8xxx/pm8921.h31
-rw-r--r--include/linux/mfd/tmio.h17
-rw-r--r--include/linux/mfd/tps65910.h800
-rw-r--r--include/linux/mfd/twl4030-codec.h2
-rw-r--r--include/linux/mfd/wm831x/core.h26
-rw-r--r--include/linux/mfd/wm831x/pdata.h4
-rw-r--r--include/linux/mfd/wm8994/pdata.h49
16 files changed, 2102 insertions, 54 deletions
diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h
index 8fba7972ff5f..63b4fb8e3b6f 100644
--- a/include/linux/mfd/88pm860x.h
+++ b/include/linux/mfd/88pm860x.h
@@ -330,6 +330,11 @@ struct pm860x_led_pdata {
330 unsigned long flags; 330 unsigned long flags;
331}; 331};
332 332
333struct pm860x_rtc_pdata {
334 int (*sync)(unsigned int ticks);
335 int vrtc;
336};
337
333struct pm860x_touch_pdata { 338struct pm860x_touch_pdata {
334 int gpadc_prebias; 339 int gpadc_prebias;
335 int slot_cycle; 340 int slot_cycle;
@@ -349,6 +354,7 @@ struct pm860x_power_pdata {
349struct pm860x_platform_data { 354struct pm860x_platform_data {
350 struct pm860x_backlight_pdata *backlight; 355 struct pm860x_backlight_pdata *backlight;
351 struct pm860x_led_pdata *led; 356 struct pm860x_led_pdata *led;
357 struct pm860x_rtc_pdata *rtc;
352 struct pm860x_touch_pdata *touch; 358 struct pm860x_touch_pdata *touch;
353 struct pm860x_power_pdata *power; 359 struct pm860x_power_pdata *power;
354 struct regulator_init_data *regulator; 360 struct regulator_init_data *regulator;
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h
index 7d9b6ae1c203..896b5e47f16e 100644
--- a/include/linux/mfd/abx500.h
+++ b/include/linux/mfd/abx500.h
@@ -34,6 +34,13 @@
34#define AB5500_2_0 0x21 34#define AB5500_2_0 0x21
35#define AB5500_2_1 0x22 35#define AB5500_2_1 0x22
36 36
37/* AB8500 CIDs*/
38#define AB8500_CUTEARLY 0x00
39#define AB8500_CUT1P0 0x10
40#define AB8500_CUT1P1 0x11
41#define AB8500_CUT2P0 0x20
42#define AB8500_CUT3P0 0x30
43
37/* 44/*
38 * AB3100, EVENTA1, A2 and A3 event register flags 45 * AB3100, EVENTA1, A2 and A3 event register flags
39 * these are catenated into a single 32-bit flag in the code 46 * these are catenated into a single 32-bit flag in the code
@@ -186,6 +193,7 @@ struct abx500_init_settings {
186struct ab3550_platform_data { 193struct ab3550_platform_data {
187 struct {unsigned int base; unsigned int count; } irq; 194 struct {unsigned int base; unsigned int count; } irq;
188 void *dev_data[AB3550_NUM_DEVICES]; 195 void *dev_data[AB3550_NUM_DEVICES];
196 size_t dev_data_sz[AB3550_NUM_DEVICES];
189 struct abx500_init_settings *init_settings; 197 struct abx500_init_settings *init_settings;
190 unsigned int init_settings_sz; 198 unsigned int init_settings_sz;
191}; 199};
diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h
index de3c4ad19afb..ed793b77a1c5 100644
--- a/include/linux/mfd/asic3.h
+++ b/include/linux/mfd/asic3.h
@@ -16,6 +16,13 @@
16 16
17#include <linux/types.h> 17#include <linux/types.h>
18 18
19struct led_classdev;
20struct asic3_led {
21 const char *name;
22 const char *default_trigger;
23 struct led_classdev *cdev;
24};
25
19struct asic3_platform_data { 26struct asic3_platform_data {
20 u16 *gpio_config; 27 u16 *gpio_config;
21 unsigned int gpio_config_num; 28 unsigned int gpio_config_num;
@@ -23,6 +30,8 @@ struct asic3_platform_data {
23 unsigned int irq_base; 30 unsigned int irq_base;
24 31
25 unsigned int gpio_base; 32 unsigned int gpio_base;
33
34 struct asic3_led *leds;
26}; 35};
27 36
28#define ASIC3_NUM_GPIO_BANKS 4 37#define ASIC3_NUM_GPIO_BANKS 4
@@ -111,9 +120,9 @@ struct asic3_platform_data {
111#define ASIC3_GPIOA11_PWM0 ASIC3_CONFIG_GPIO(11, 1, 1, 0) 120#define ASIC3_GPIOA11_PWM0 ASIC3_CONFIG_GPIO(11, 1, 1, 0)
112#define ASIC3_GPIOA12_PWM1 ASIC3_CONFIG_GPIO(12, 1, 1, 0) 121#define ASIC3_GPIOA12_PWM1 ASIC3_CONFIG_GPIO(12, 1, 1, 0)
113#define ASIC3_GPIOA15_CONTROL_CX ASIC3_CONFIG_GPIO(15, 1, 1, 0) 122#define ASIC3_GPIOA15_CONTROL_CX ASIC3_CONFIG_GPIO(15, 1, 1, 0)
114#define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 1, 0) 123#define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 0, 0)
115#define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 1, 0) 124#define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 0, 0)
116#define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 1, 0) 125#define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 0, 0)
117#define ASIC3_GPIOC3_SPI_RXD ASIC3_CONFIG_GPIO(35, 1, 0, 0) 126#define ASIC3_GPIOC3_SPI_RXD ASIC3_CONFIG_GPIO(35, 1, 0, 0)
118#define ASIC3_GPIOC4_CF_nCD ASIC3_CONFIG_GPIO(36, 1, 0, 0) 127#define ASIC3_GPIOC4_CF_nCD ASIC3_CONFIG_GPIO(36, 1, 0, 0)
119#define ASIC3_GPIOC4_SPI_TXD ASIC3_CONFIG_GPIO(36, 1, 1, 0) 128#define ASIC3_GPIOC4_SPI_TXD ASIC3_CONFIG_GPIO(36, 1, 1, 0)
@@ -152,6 +161,7 @@ struct asic3_platform_data {
152#define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base */ 161#define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base */
153#define PWM_TIMEBASE_ENABLE (1 << 4) /* Enable clock */ 162#define PWM_TIMEBASE_ENABLE (1 << 4) /* Enable clock */
154 163
164#define ASIC3_NUM_LEDS 3
155#define ASIC3_LED_0_Base 0x0700 165#define ASIC3_LED_0_Base 0x0700
156#define ASIC3_LED_1_Base 0x0800 166#define ASIC3_LED_1_Base 0x0800
157#define ASIC3_LED_2_Base 0x0900 167#define ASIC3_LED_2_Base 0x0900
@@ -287,10 +297,17 @@ struct asic3_platform_data {
287 * 297 *
288 *****************************************************************************/ 298 *****************************************************************************/
289#define ASIC3_SD_CONFIG_BASE 0x0400 /* Assumes 32 bit addressing */ 299#define ASIC3_SD_CONFIG_BASE 0x0400 /* Assumes 32 bit addressing */
300#define ASIC3_SD_CONFIG_SIZE 0x0200 /* Assumes 32 bit addressing */
290#define ASIC3_SD_CTRL_BASE 0x1000 301#define ASIC3_SD_CTRL_BASE 0x1000
291#define ASIC3_SDIO_CTRL_BASE 0x1200 302#define ASIC3_SDIO_CTRL_BASE 0x1200
292 303
293#define ASIC3_MAP_SIZE_32BIT 0x2000 304#define ASIC3_MAP_SIZE_32BIT 0x2000
294#define ASIC3_MAP_SIZE_16BIT 0x1000 305#define ASIC3_MAP_SIZE_16BIT 0x1000
295 306
307/* Functions needed by leds-asic3 */
308
309struct asic3;
310extern void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 val);
311extern u32 asic3_read_register(struct asic3 *asic, unsigned int reg);
312
296#endif /* __ASIC3_H__ */ 313#endif /* __ASIC3_H__ */
diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h
index aef23309a742..4e76163dd862 100644
--- a/include/linux/mfd/core.h
+++ b/include/linux/mfd/core.h
@@ -33,8 +33,9 @@ struct mfd_cell {
33 int (*suspend)(struct platform_device *dev); 33 int (*suspend)(struct platform_device *dev);
34 int (*resume)(struct platform_device *dev); 34 int (*resume)(struct platform_device *dev);
35 35
36 /* mfd_data can be used to pass data to client drivers */ 36 /* platform data passed to the sub devices drivers */
37 void *mfd_data; 37 void *platform_data;
38 size_t pdata_size;
38 39
39 /* 40 /*
40 * These resources can be specified relative to the parent device. 41 * These resources can be specified relative to the parent device.
@@ -89,24 +90,6 @@ static inline const struct mfd_cell *mfd_get_cell(struct platform_device *pdev)
89 return pdev->mfd_cell; 90 return pdev->mfd_cell;
90} 91}
91 92
92/*
93 * Given a platform device that's been created by mfd_add_devices(), fetch
94 * the .mfd_data entry from the mfd_cell that created it.
95 * Otherwise just return the platform_data pointer.
96 * This maintains compatibility with platform drivers whose devices aren't
97 * created by the mfd layer, and expect platform_data to contain what would've
98 * otherwise been in mfd_data.
99 */
100static inline void *mfd_get_data(struct platform_device *pdev)
101{
102 const struct mfd_cell *cell = mfd_get_cell(pdev);
103
104 if (cell)
105 return cell->mfd_data;
106 else
107 return pdev->dev.platform_data;
108}
109
110extern int mfd_add_devices(struct device *parent, int id, 93extern int mfd_add_devices(struct device *parent, int id,
111 struct mfd_cell *cells, int n_devs, 94 struct mfd_cell *cells, int n_devs,
112 struct resource *mem_base, 95 struct resource *mem_base,
diff --git a/include/linux/mfd/db5500-prcmu.h b/include/linux/mfd/db5500-prcmu.h
new file mode 100644
index 000000000000..f0977986402c
--- /dev/null
+++ b/include/linux/mfd/db5500-prcmu.h
@@ -0,0 +1,45 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
6 * U5500 PRCMU API.
7 */
8#ifndef __MACH_PRCMU_U5500_H
9#define __MACH_PRCMU_U5500_H
10
11#ifdef CONFIG_UX500_SOC_DB5500
12
13void db5500_prcmu_early_init(void);
14
15int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
16int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
17
18#else /* !CONFIG_UX500_SOC_DB5500 */
19
20static inline void db5500_prcmu_early_init(void)
21{
22}
23
24static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
25{
26 return -ENOSYS;
27}
28
29static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
30{
31 return -ENOSYS;
32}
33
34#endif /* CONFIG_UX500_SOC_DB5500 */
35
36static inline int db5500_prcmu_config_abb_event_readout(u32 abb_events)
37{
38#ifdef CONFIG_MACH_U5500_SIMULATOR
39 return 0;
40#else
41 return -1;
42#endif
43}
44
45#endif /* __MACH_PRCMU_U5500_H */
diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
new file mode 100644
index 000000000000..917dbcab701c
--- /dev/null
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -0,0 +1,978 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * License Terms: GNU General Public License v2
6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 *
8 * PRCMU f/w APIs
9 */
10#ifndef __MFD_DB8500_PRCMU_H
11#define __MFD_DB8500_PRCMU_H
12
13#include <linux/interrupt.h>
14#include <linux/notifier.h>
15
16/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
17
18/**
19 * enum state - ON/OFF state definition
20 * @OFF: State is ON
21 * @ON: State is OFF
22 *
23 */
24enum state {
25 OFF = 0x0,
26 ON = 0x1,
27};
28
29/**
30 * enum ret_state - general purpose On/Off/Retention states
31 *
32 */
33enum ret_state {
34 OFFST = 0,
35 ONST = 1,
36 RETST = 2
37};
38
39/**
40 * enum clk_arm - ARM Cortex A9 clock schemes
41 * @A9_OFF:
42 * @A9_BOOT:
43 * @A9_OPPT1:
44 * @A9_OPPT2:
45 * @A9_EXTCLK:
46 */
47enum clk_arm {
48 A9_OFF,
49 A9_BOOT,
50 A9_OPPT1,
51 A9_OPPT2,
52 A9_EXTCLK
53};
54
55/**
56 * enum clk_gen - GEN#0/GEN#1 clock schemes
57 * @GEN_OFF:
58 * @GEN_BOOT:
59 * @GEN_OPPT1:
60 */
61enum clk_gen {
62 GEN_OFF,
63 GEN_BOOT,
64 GEN_OPPT1,
65};
66
67/* some information between arm and xp70 */
68
69/**
70 * enum romcode_write - Romcode message written by A9 AND read by XP70
71 * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
72 * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
73 * romcode. The xp70 will go into self-reset
74 */
75enum romcode_write {
76 RDY_2_DS = 0x09,
77 RDY_2_XP70_RST = 0x10
78};
79
80/**
81 * enum romcode_read - Romcode message written by XP70 and read by A9
82 * @INIT: Init value when romcode field is not used
83 * @FS_2_DS: Value set when power state is going from ApExecute to
84 * ApDeepSleep
85 * @END_DS: Value set when ApDeepSleep power state is reached coming from
86 * ApExecute state
87 * @DS_TO_FS: Value set when power state is going from ApDeepSleep to
88 * ApExecute
89 * @END_FS: Value set when ApExecute power state is reached coming from
90 * ApDeepSleep state
91 * @SWR: Value set when power state is going to ApReset
92 * @END_SWR: Value set when the xp70 finished executing ApReset actions and
93 * waits for romcode acknowledgment to go to self-reset
94 */
95enum romcode_read {
96 INIT = 0x00,
97 FS_2_DS = 0x0A,
98 END_DS = 0x0B,
99 DS_TO_FS = 0x0C,
100 END_FS = 0x0D,
101 SWR = 0x0E,
102 END_SWR = 0x0F
103};
104
105/**
106 * enum ap_pwrst - current power states defined in PRCMU firmware
107 * @NO_PWRST: Current power state init
108 * @AP_BOOT: Current power state is apBoot
109 * @AP_EXECUTE: Current power state is apExecute
110 * @AP_DEEP_SLEEP: Current power state is apDeepSleep
111 * @AP_SLEEP: Current power state is apSleep
112 * @AP_IDLE: Current power state is apIdle
113 * @AP_RESET: Current power state is apReset
114 */
115enum ap_pwrst {
116 NO_PWRST = 0x00,
117 AP_BOOT = 0x01,
118 AP_EXECUTE = 0x02,
119 AP_DEEP_SLEEP = 0x03,
120 AP_SLEEP = 0x04,
121 AP_IDLE = 0x05,
122 AP_RESET = 0x06
123};
124
125/**
126 * enum ap_pwrst_trans - Transition states defined in PRCMU firmware
127 * @NO_TRANSITION: No power state transition
128 * @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep
129 * @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep
130 * @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute
131 * @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to
132 * ApDeepSleep
133 * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
134 */
135enum ap_pwrst_trans {
136 NO_TRANSITION = 0x00,
137 APEXECUTE_TO_APSLEEP = 0x01,
138 APIDLE_TO_APSLEEP = 0x02, /* To be removed */
139 PRCMU_AP_SLEEP = 0x01,
140 APBOOT_TO_APEXECUTE = 0x03,
141 APEXECUTE_TO_APDEEPSLEEP = 0x04, /* To be removed */
142 PRCMU_AP_DEEP_SLEEP = 0x04,
143 APEXECUTE_TO_APIDLE = 0x05, /* To be removed */
144 PRCMU_AP_IDLE = 0x05,
145 PRCMU_AP_DEEP_IDLE = 0x07,
146};
147
148/**
149 * enum ddr_pwrst - DDR power states definition
150 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
151 * @DDR_PWR_STATE_ON:
152 * @DDR_PWR_STATE_OFFLOWLAT:
153 * @DDR_PWR_STATE_OFFHIGHLAT:
154 */
155enum ddr_pwrst {
156 DDR_PWR_STATE_UNCHANGED = 0x00,
157 DDR_PWR_STATE_ON = 0x01,
158 DDR_PWR_STATE_OFFLOWLAT = 0x02,
159 DDR_PWR_STATE_OFFHIGHLAT = 0x03
160};
161
162/**
163 * enum arm_opp - ARM OPP states definition
164 * @ARM_OPP_INIT:
165 * @ARM_NO_CHANGE: The ARM operating point is unchanged
166 * @ARM_100_OPP: The new ARM operating point is arm100opp
167 * @ARM_50_OPP: The new ARM operating point is arm50opp
168 * @ARM_MAX_OPP: Operating point is "max" (more than 100)
169 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
170 * @ARM_EXTCLK: The new ARM operating point is armExtClk
171 */
172enum arm_opp {
173 ARM_OPP_INIT = 0x00,
174 ARM_NO_CHANGE = 0x01,
175 ARM_100_OPP = 0x02,
176 ARM_50_OPP = 0x03,
177 ARM_MAX_OPP = 0x04,
178 ARM_MAX_FREQ100OPP = 0x05,
179 ARM_EXTCLK = 0x07
180};
181
182/**
183 * enum ape_opp - APE OPP states definition
184 * @APE_OPP_INIT:
185 * @APE_NO_CHANGE: The APE operating point is unchanged
186 * @APE_100_OPP: The new APE operating point is ape100opp
187 * @APE_50_OPP: 50%
188 */
189enum ape_opp {
190 APE_OPP_INIT = 0x00,
191 APE_NO_CHANGE = 0x01,
192 APE_100_OPP = 0x02,
193 APE_50_OPP = 0x03
194};
195
196/**
197 * enum hw_acc_state - State definition for hardware accelerator
198 * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
199 * @HW_OFF: The hardware accelerator must be switched off
200 * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its
201 * internal RAM in retention
202 * @HW_ON: The hwa hardware accelerator hwa must be switched on
203 *
204 * NOTE! Deprecated, to be removed when all users switched over to use the
205 * regulator API.
206 */
207enum hw_acc_state {
208 HW_NO_CHANGE = 0x00,
209 HW_OFF = 0x01,
210 HW_OFF_RAMRET = 0x02,
211 HW_ON = 0x04
212};
213
214/**
215 * enum mbox_2_arm_stat - Status messages definition for mbox_arm
216 * @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been
217 * completed
218 * @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been
219 * completed
220 * @SLEEPOK: The apExecute to apSleep state transition has been completed
221 * @IDLEOK: The apExecute to apIdle state transition has been completed
222 * @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed
223 * @SOFTRESETGO : The A9 watchdog/SoftReset state is on going
224 * @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going
225 * @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on
226 * going
227 * @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on
228 * going
229 * @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has
230 * been completed
231 * @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going
232 * @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going
233 * @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been
234 * completed
235 * @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going
236 * @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going
237 * @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been
238 * completed
239 * @INIT_STATUS: Status init
240 */
241enum ap_pwrsttr_status {
242 BOOT_TO_EXECUTEOK = 0xFF,
243 DEEPSLEEPOK = 0xFE,
244 SLEEPOK = 0xFD,
245 IDLEOK = 0xFC,
246 SOFTRESETOK = 0xFB,
247 SOFTRESETGO = 0xFA,
248 BOOT_TO_EXECUTE = 0xF9,
249 EXECUTE_TO_DEEPSLEEP = 0xF8,
250 DEEPSLEEP_TO_EXECUTE = 0xF7,
251 DEEPSLEEP_TO_EXECUTEOK = 0xF6,
252 EXECUTE_TO_SLEEP = 0xF5,
253 SLEEP_TO_EXECUTE = 0xF4,
254 SLEEP_TO_EXECUTEOK = 0xF3,
255 EXECUTE_TO_IDLE = 0xF2,
256 IDLE_TO_EXECUTE = 0xF1,
257 IDLE_TO_EXECUTEOK = 0xF0,
258 RDYTODS_RETURNTOEXE = 0xEF,
259 NORDYTODS_RETURNTOEXE = 0xEE,
260 EXETOSLEEP_RETURNTOEXE = 0xED,
261 EXETOIDLE_RETURNTOEXE = 0xEC,
262 INIT_STATUS = 0xEB,
263
264 /*error messages */
265 INITERROR = 0x00,
266 PLLARMLOCKP_ER = 0x01,
267 PLLDDRLOCKP_ER = 0x02,
268 PLLSOCLOCKP_ER = 0x03,
269 PLLSOCK1LOCKP_ER = 0x04,
270 ARMWFI_ER = 0x05,
271 SYSCLKOK_ER = 0x06,
272 I2C_NACK_DATA_ER = 0x07,
273 BOOT_ER = 0x08,
274 I2C_STATUS_ALWAYS_1 = 0x0A,
275 I2C_NACK_REG_ADDR_ER = 0x0B,
276 I2C_NACK_DATA0123_ER = 0x1B,
277 I2C_NACK_ADDR_ER = 0x1F,
278 CURAPPWRSTISNOT_BOOT = 0x20,
279 CURAPPWRSTISNOT_EXECUTE = 0x21,
280 CURAPPWRSTISNOT_SLEEPMODE = 0x22,
281 CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23,
282 FIFO4500WUISNOT_WUPEVENT = 0x24,
283 PLL32KLOCKP_ER = 0x29,
284 DDRDEEPSLEEPOK_ER = 0x2A,
285 ROMCODEREADY_ER = 0x50,
286 WUPBEFOREDS = 0x51,
287 DDRCONFIG_ER = 0x52,
288 WUPBEFORESLEEP = 0x53,
289 WUPBEFOREIDLE = 0x54
290}; /* earlier called as mbox_2_arm_stat */
291
292/**
293 * enum dvfs_stat - DVFS status messages definition
294 * @DVFS_GO: A state transition DVFS is on going
295 * @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP
296 * @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP
297 * @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK
298 * @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for
299 * NOCHGCLK
300 * @DVFS_INITSTATUS: Value init
301 */
302enum dvfs_stat {
303 DVFS_GO = 0xFF,
304 DVFS_ARM100OPPOK = 0xFE,
305 DVFS_ARM50OPPOK = 0xFD,
306 DVFS_ARMEXTCLKOK = 0xFC,
307 DVFS_NOCHGTCLKOK = 0xFB,
308 DVFS_INITSTATUS = 0x00
309};
310
311/**
312 * enum sva_mmdsp_stat - SVA MMDSP status messages
313 * @SVA_MMDSP_GO: SVAMMDSP interrupt has happened
314 * @SVA_MMDSP_INIT: Status init
315 */
316enum sva_mmdsp_stat {
317 SVA_MMDSP_GO = 0xFF,
318 SVA_MMDSP_INIT = 0x00
319};
320
321/**
322 * enum sia_mmdsp_stat - SIA MMDSP status messages
323 * @SIA_MMDSP_GO: SIAMMDSP interrupt has happened
324 * @SIA_MMDSP_INIT: Status init
325 */
326enum sia_mmdsp_stat {
327 SIA_MMDSP_GO = 0xFF,
328 SIA_MMDSP_INIT = 0x00
329};
330
331/**
332 * enum mbox_to_arm_err - Error messages definition
333 * @INIT_ERR: Init value
334 * @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time
335 * @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time
336 * @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time
337 * @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time
338 * @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time
339 * @SYSCLKOK_ERR: The SYSCLK is not available in the given time
340 * @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time
341 * @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context
342 * @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered
343 * through I2C has not been correctly executed in the given time
344 * @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered
345 * through I2C has not been correctly executed in the given time
346 * @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through
347 * I2C has not been correctly executed in the given time
348 * @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered
349 * through I2C has not been correctly executed in the given time
350 * @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through
351 * I2C has not been correctly executed in the given time
352 * @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered
353 * through I2C has not been correctly executed in the given time
354 * @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through
355 * I2C has not been correctly executed in the given time
356 * @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C
357 * has not been correctly executed in the given time
358 * @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has
359 * not been correctly executed in the given time
360 * @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has
361 * not been correctly executed in the given time
362 * @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through
363 * I2C has not been correctly executed in the given time
364 * @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through
365 * I2C has not been correctly executed in the given time
366 * @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered
367 * through I2C has not been correctly executed in the given time
368 * @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition
369 * ApBoot to ApExecute but the power current state is not Apboot
370 * @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state
371 * transition from ApExecute to others power state but the
372 * power current state is not ApExecute
373 * @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted
374 * but the power current state is not ApDeepSleep/ApSleep/ApIdle
375 * @CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted
376 * but the power current state is not correct
377 * @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not
378 * been correctly executed in the given time
379 * @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not
380 * been correctly executed in the given time
381 * @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not
382 * been correctly executed in the given time
383 * @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not
384 * been correctly executed in the given time
385 * @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not
386 * been correctly executed in the given time
387 */
388enum mbox_to_arm_err {
389 INIT_ERR = 0x00,
390 PLLARMLOCKP_ERR = 0x01,
391 PLLDDRLOCKP_ERR = 0x02,
392 PLLSOC0LOCKP_ERR = 0x03,
393 PLLSOC1LOCKP_ERR = 0x04,
394 ARMWFI_ERR = 0x05,
395 SYSCLKOK_ERR = 0x06,
396 BOOT_ERR = 0x07,
397 ROMCODESAVECONTEXT = 0x08,
398 VARMHIGHSPEEDVALTO_ERR = 0x10,
399 VARMHIGHSPEEDACCESS_ERR = 0x11,
400 VARMLOWSPEEDVALTO_ERR = 0x12,
401 VARMLOWSPEEDACCESS_ERR = 0x13,
402 VARMRETENTIONVALTO_ERR = 0x14,
403 VARMRETENTIONACCESS_ERR = 0x15,
404 VAPEHIGHSPEEDVALTO_ERR = 0x16,
405 VSAFEHPVALTO_ERR = 0x17,
406 VMODSEL1VALTO_ERR = 0x18,
407 VMODSEL2VALTO_ERR = 0x19,
408 VARMOFFACCESS_ERR = 0x1A,
409 VAPEOFFACCESS_ERR = 0x1B,
410 VARMRETACCES_ERR = 0x1C,
411 CURAPPWRSTISNOTBOOT = 0x20,
412 CURAPPWRSTISNOTEXECUTE = 0x21,
413 CURAPPWRSTISNOTSLEEPMODE = 0x22,
414 CURAPPWRSTISNOTCORRECTDBG = 0x23,
415 ARMREGU1VALTO_ERR = 0x24,
416 ARMREGU2VALTO_ERR = 0x25,
417 VAPEREGUVALTO_ERR = 0x26,
418 VSMPS3REGUVALTO_ERR = 0x27,
419 VMODREGUVALTO_ERR = 0x28
420};
421
422enum hw_acc {
423 SVAMMDSP = 0,
424 SVAPIPE = 1,
425 SIAMMDSP = 2,
426 SIAPIPE = 3,
427 SGA = 4,
428 B2R2MCDE = 5,
429 ESRAM12 = 6,
430 ESRAM34 = 7,
431};
432
433enum cs_pwrmgt {
434 PWRDNCS0 = 0,
435 WKUPCS0 = 1,
436 PWRDNCS1 = 2,
437 WKUPCS1 = 3
438};
439
440/* Defs related to autonomous power management */
441
442/**
443 * enum sia_sva_pwr_policy - Power policy
444 * @NO_CHGT: No change
445 * @DSPOFF_HWPOFF:
446 * @DSPOFFRAMRET_HWPOFF:
447 * @DSPCLKOFF_HWPOFF:
448 * @DSPCLKOFF_HWPCLKOFF:
449 *
450 */
451enum sia_sva_pwr_policy {
452 NO_CHGT = 0x0,
453 DSPOFF_HWPOFF = 0x1,
454 DSPOFFRAMRET_HWPOFF = 0x2,
455 DSPCLKOFF_HWPOFF = 0x3,
456 DSPCLKOFF_HWPCLKOFF = 0x4,
457};
458
459/**
460 * enum auto_enable - Auto Power enable
461 * @AUTO_OFF:
462 * @AUTO_ON:
463 *
464 */
465enum auto_enable {
466 AUTO_OFF = 0x0,
467 AUTO_ON = 0x1,
468};
469
470/* End of file previously known as prcmu-fw-defs_v1.h */
471
472/* PRCMU Wakeup defines */
473enum prcmu_wakeup_index {
474 PRCMU_WAKEUP_INDEX_RTC,
475 PRCMU_WAKEUP_INDEX_RTT0,
476 PRCMU_WAKEUP_INDEX_RTT1,
477 PRCMU_WAKEUP_INDEX_HSI0,
478 PRCMU_WAKEUP_INDEX_HSI1,
479 PRCMU_WAKEUP_INDEX_USB,
480 PRCMU_WAKEUP_INDEX_ABB,
481 PRCMU_WAKEUP_INDEX_ABB_FIFO,
482 PRCMU_WAKEUP_INDEX_ARM,
483 NUM_PRCMU_WAKEUP_INDICES
484};
485#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
486
487/* PRCMU QoS APE OPP class */
488#define PRCMU_QOS_APE_OPP 1
489#define PRCMU_QOS_DDR_OPP 2
490#define PRCMU_QOS_DEFAULT_VALUE -1
491
492/**
493 * enum hw_acc_dev - enum for hw accelerators
494 * @HW_ACC_SVAMMDSP: for SVAMMDSP
495 * @HW_ACC_SVAPIPE: for SVAPIPE
496 * @HW_ACC_SIAMMDSP: for SIAMMDSP
497 * @HW_ACC_SIAPIPE: for SIAPIPE
498 * @HW_ACC_SGA: for SGA
499 * @HW_ACC_B2R2: for B2R2
500 * @HW_ACC_MCDE: for MCDE
501 * @HW_ACC_ESRAM1: for ESRAM1
502 * @HW_ACC_ESRAM2: for ESRAM2
503 * @HW_ACC_ESRAM3: for ESRAM3
504 * @HW_ACC_ESRAM4: for ESRAM4
505 * @NUM_HW_ACC: number of hardware accelerators
506 *
507 * Different hw accelerators which can be turned ON/
508 * OFF or put into retention (MMDSPs and ESRAMs).
509 * Used with EPOD API.
510 *
511 * NOTE! Deprecated, to be removed when all users switched over to use the
512 * regulator API.
513 */
514enum hw_acc_dev {
515 HW_ACC_SVAMMDSP,
516 HW_ACC_SVAPIPE,
517 HW_ACC_SIAMMDSP,
518 HW_ACC_SIAPIPE,
519 HW_ACC_SGA,
520 HW_ACC_B2R2,
521 HW_ACC_MCDE,
522 HW_ACC_ESRAM1,
523 HW_ACC_ESRAM2,
524 HW_ACC_ESRAM3,
525 HW_ACC_ESRAM4,
526 NUM_HW_ACC
527};
528
529/*
530 * Ids for all EPODs (power domains)
531 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
532 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
533 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
534 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
535 * - EPOD_ID_SGA: power domain for SGA
536 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
537 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
538 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
539 * - NUM_EPOD_ID: number of power domains
540 */
541#define EPOD_ID_SVAMMDSP 0
542#define EPOD_ID_SVAPIPE 1
543#define EPOD_ID_SIAMMDSP 2
544#define EPOD_ID_SIAPIPE 3
545#define EPOD_ID_SGA 4
546#define EPOD_ID_B2R2_MCDE 5
547#define EPOD_ID_ESRAM12 6
548#define EPOD_ID_ESRAM34 7
549#define NUM_EPOD_ID 8
550
551/*
552 * state definition for EPOD (power domain)
553 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
554 * - EPOD_STATE_OFF: The EPOD is switched off
555 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
556 * retention
557 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
558 * - EPOD_STATE_ON: Same as above, but with clock enabled
559 */
560#define EPOD_STATE_NO_CHANGE 0x00
561#define EPOD_STATE_OFF 0x01
562#define EPOD_STATE_RAMRET 0x02
563#define EPOD_STATE_ON_CLK_OFF 0x03
564#define EPOD_STATE_ON 0x04
565
566/*
567 * CLKOUT sources
568 */
569#define PRCMU_CLKSRC_CLK38M 0x00
570#define PRCMU_CLKSRC_ACLK 0x01
571#define PRCMU_CLKSRC_SYSCLK 0x02
572#define PRCMU_CLKSRC_LCDCLK 0x03
573#define PRCMU_CLKSRC_SDMMCCLK 0x04
574#define PRCMU_CLKSRC_TVCLK 0x05
575#define PRCMU_CLKSRC_TIMCLK 0x06
576#define PRCMU_CLKSRC_CLK009 0x07
577/* These are only valid for CLKOUT1: */
578#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
579#define PRCMU_CLKSRC_I2CCLK 0x41
580#define PRCMU_CLKSRC_MSP02CLK 0x42
581#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
582#define PRCMU_CLKSRC_HSIRXCLK 0x44
583#define PRCMU_CLKSRC_HSITXCLK 0x45
584#define PRCMU_CLKSRC_ARMCLKFIX 0x46
585#define PRCMU_CLKSRC_HDMICLK 0x47
586
587/*
588 * Definitions for autonomous power management configuration.
589 */
590
591#define PRCMU_AUTO_PM_OFF 0
592#define PRCMU_AUTO_PM_ON 1
593
594#define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
595#define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
596
597enum prcmu_auto_pm_policy {
598 PRCMU_AUTO_PM_POLICY_NO_CHANGE,
599 PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
600 PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
601 PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
602 PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
603};
604
605/**
606 * struct prcmu_auto_pm_config - Autonomous power management configuration.
607 * @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
608 * @sia_power_on: SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
609 * @sia_policy: SIA power policy. (enum prcmu_auto_pm_policy)
610 * @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
611 * @sva_power_on: SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
612 * @sva_policy: SVA power policy. (enum prcmu_auto_pm_policy)
613 */
614struct prcmu_auto_pm_config {
615 u8 sia_auto_pm_enable;
616 u8 sia_power_on;
617 u8 sia_policy;
618 u8 sva_auto_pm_enable;
619 u8 sva_power_on;
620 u8 sva_policy;
621};
622
623/**
624 * enum ddr_opp - DDR OPP states definition
625 * @DDR_100_OPP: The new DDR operating point is ddr100opp
626 * @DDR_50_OPP: The new DDR operating point is ddr50opp
627 * @DDR_25_OPP: The new DDR operating point is ddr25opp
628 */
629enum ddr_opp {
630 DDR_100_OPP = 0x00,
631 DDR_50_OPP = 0x01,
632 DDR_25_OPP = 0x02,
633};
634
635/*
636 * Clock identifiers.
637 */
638enum prcmu_clock {
639 PRCMU_SGACLK,
640 PRCMU_UARTCLK,
641 PRCMU_MSP02CLK,
642 PRCMU_MSP1CLK,
643 PRCMU_I2CCLK,
644 PRCMU_SDMMCCLK,
645 PRCMU_SLIMCLK,
646 PRCMU_PER1CLK,
647 PRCMU_PER2CLK,
648 PRCMU_PER3CLK,
649 PRCMU_PER5CLK,
650 PRCMU_PER6CLK,
651 PRCMU_PER7CLK,
652 PRCMU_LCDCLK,
653 PRCMU_BMLCLK,
654 PRCMU_HSITXCLK,
655 PRCMU_HSIRXCLK,
656 PRCMU_HDMICLK,
657 PRCMU_APEATCLK,
658 PRCMU_APETRACECLK,
659 PRCMU_MCDECLK,
660 PRCMU_IPI2CCLK,
661 PRCMU_DSIALTCLK,
662 PRCMU_DMACLK,
663 PRCMU_B2R2CLK,
664 PRCMU_TVCLK,
665 PRCMU_SSPCLK,
666 PRCMU_RNGCLK,
667 PRCMU_UICCCLK,
668 PRCMU_NUM_REG_CLOCKS,
669 PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
670 PRCMU_TIMCLK,
671};
672
673/*
674 * Definitions for controlling ESRAM0 in deep sleep.
675 */
676#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
677#define ESRAM0_DEEP_SLEEP_STATE_RET 2
678
679#ifdef CONFIG_MFD_DB8500_PRCMU
680void __init prcmu_early_init(void);
681int prcmu_set_display_clocks(void);
682int prcmu_disable_dsipll(void);
683int prcmu_enable_dsipll(void);
684#else
685static inline void __init prcmu_early_init(void) {}
686#endif
687
688#ifdef CONFIG_MFD_DB8500_PRCMU
689
690int prcmu_set_rc_a2p(enum romcode_write);
691enum romcode_read prcmu_get_rc_p2a(void);
692enum ap_pwrst prcmu_get_xp70_current_state(void);
693int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
694
695void prcmu_enable_wakeups(u32 wakeups);
696static inline void prcmu_disable_wakeups(void)
697{
698 prcmu_enable_wakeups(0);
699}
700
701void prcmu_config_abb_event_readout(u32 abb_events);
702void prcmu_get_abb_event_buffer(void __iomem **buf);
703int prcmu_set_arm_opp(u8 opp);
704int prcmu_get_arm_opp(void);
705bool prcmu_has_arm_maxopp(void);
706bool prcmu_is_u8400(void);
707int prcmu_set_ape_opp(u8 opp);
708int prcmu_get_ape_opp(void);
709int prcmu_request_ape_opp_100_voltage(bool enable);
710int prcmu_release_usb_wakeup_state(void);
711int prcmu_set_ddr_opp(u8 opp);
712int prcmu_get_ddr_opp(void);
713unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
714void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
715/* NOTE! Use regulator framework instead */
716int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
717int prcmu_set_epod(u16 epod_id, u8 epod_state);
718void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
719 struct prcmu_auto_pm_config *idle);
720bool prcmu_is_auto_pm_enabled(void);
721
722int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
723int prcmu_request_clock(u8 clock, bool enable);
724int prcmu_set_clock_divider(u8 clock, u8 divider);
725int prcmu_config_esram0_deep_sleep(u8 state);
726int prcmu_config_hotdog(u8 threshold);
727int prcmu_config_hotmon(u8 low, u8 high);
728int prcmu_start_temp_sense(u16 cycles32k);
729int prcmu_stop_temp_sense(void);
730int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
731int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
732
733void prcmu_ac_wake_req(void);
734void prcmu_ac_sleep_req(void);
735void prcmu_system_reset(u16 reset_code);
736void prcmu_modem_reset(void);
737bool prcmu_is_ac_wake_requested(void);
738void prcmu_enable_spi2(void);
739void prcmu_disable_spi2(void);
740
741#else /* !CONFIG_MFD_DB8500_PRCMU */
742
743static inline int prcmu_set_rc_a2p(enum romcode_write code)
744{
745 return 0;
746}
747
748static inline enum romcode_read prcmu_get_rc_p2a(void)
749{
750 return INIT;
751}
752
753static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
754{
755 return AP_EXECUTE;
756}
757
758static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
759 bool keep_ap_pll)
760{
761 return 0;
762}
763
764static inline void prcmu_enable_wakeups(u32 wakeups) {}
765
766static inline void prcmu_disable_wakeups(void) {}
767
768static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
769
770static inline int prcmu_set_arm_opp(u8 opp)
771{
772 return 0;
773}
774
775static inline int prcmu_get_arm_opp(void)
776{
777 return ARM_100_OPP;
778}
779
780static bool prcmu_has_arm_maxopp(void)
781{
782 return false;
783}
784
785static bool prcmu_is_u8400(void)
786{
787 return false;
788}
789
790static inline int prcmu_set_ape_opp(u8 opp)
791{
792 return 0;
793}
794
795static inline int prcmu_get_ape_opp(void)
796{
797 return APE_100_OPP;
798}
799
800static inline int prcmu_request_ape_opp_100_voltage(bool enable)
801{
802 return 0;
803}
804
805static inline int prcmu_release_usb_wakeup_state(void)
806{
807 return 0;
808}
809
810static inline int prcmu_set_ddr_opp(u8 opp)
811{
812 return 0;
813}
814
815static inline int prcmu_get_ddr_opp(void)
816{
817 return DDR_100_OPP;
818}
819
820static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
821{
822 return 0;
823}
824
825static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
826
827static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
828{
829 return 0;
830}
831
832static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
833 struct prcmu_auto_pm_config *idle)
834{
835}
836
837static inline bool prcmu_is_auto_pm_enabled(void)
838{
839 return false;
840}
841
842static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
843{
844 return 0;
845}
846
847static inline int prcmu_request_clock(u8 clock, bool enable)
848{
849 return 0;
850}
851
852static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
853{
854 return 0;
855}
856
857int prcmu_config_esram0_deep_sleep(u8 state)
858{
859 return 0;
860}
861
862static inline int prcmu_config_hotdog(u8 threshold)
863{
864 return 0;
865}
866
867static inline int prcmu_config_hotmon(u8 low, u8 high)
868{
869 return 0;
870}
871
872static inline int prcmu_start_temp_sense(u16 cycles32k)
873{
874 return 0;
875}
876
877static inline int prcmu_stop_temp_sense(void)
878{
879 return 0;
880}
881
882static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
883{
884 return -ENOSYS;
885}
886
887static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
888{
889 return -ENOSYS;
890}
891
892static inline void prcmu_ac_wake_req(void) {}
893
894static inline void prcmu_ac_sleep_req(void) {}
895
896static inline void prcmu_system_reset(u16 reset_code) {}
897
898static inline void prcmu_modem_reset(void) {}
899
900static inline bool prcmu_is_ac_wake_requested(void)
901{
902 return false;
903}
904
905#ifndef CONFIG_UX500_SOC_DB5500
906static inline int prcmu_set_display_clocks(void)
907{
908 return 0;
909}
910
911static inline int prcmu_disable_dsipll(void)
912{
913 return 0;
914}
915
916static inline int prcmu_enable_dsipll(void)
917{
918 return 0;
919}
920#endif
921
922static inline int prcmu_enable_spi2(void)
923{
924 return 0;
925}
926
927static inline int prcmu_disable_spi2(void)
928{
929 return 0;
930}
931
932#endif /* !CONFIG_MFD_DB8500_PRCMU */
933
934#ifdef CONFIG_UX500_PRCMU_QOS_POWER
935int prcmu_qos_requirement(int pm_qos_class);
936int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
937int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
938void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
939int prcmu_qos_add_notifier(int prcmu_qos_class,
940 struct notifier_block *notifier);
941int prcmu_qos_remove_notifier(int prcmu_qos_class,
942 struct notifier_block *notifier);
943#else
944static inline int prcmu_qos_requirement(int prcmu_qos_class)
945{
946 return 0;
947}
948
949static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
950 char *name, s32 value)
951{
952 return 0;
953}
954
955static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
956 char *name, s32 new_value)
957{
958 return 0;
959}
960
961static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
962{
963}
964
965static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
966 struct notifier_block *notifier)
967{
968 return 0;
969}
970static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
971 struct notifier_block *notifier)
972{
973 return 0;
974}
975
976#endif
977
978#endif /* __MFD_DB8500_PRCMU_H */
diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h
index 69d1010e2e51..5ff2400ad46c 100644
--- a/include/linux/mfd/max8997-private.h
+++ b/include/linux/mfd/max8997-private.h
@@ -311,10 +311,6 @@ enum max8997_irq {
311 MAX8997_IRQ_NR, 311 MAX8997_IRQ_NR,
312}; 312};
313 313
314#define MAX8997_REG_BUCK1DVS(x) (MAX8997_REG_BUCK1DVS1 + (x) - 1)
315#define MAX8997_REG_BUCK2DVS(x) (MAX8997_REG_BUCK2DVS1 + (x) - 1)
316#define MAX8997_REG_BUCK5DVS(x) (MAX8997_REG_BUCK5DVS1 + (x) - 1)
317
318#define MAX8997_NUM_GPIO 12 314#define MAX8997_NUM_GPIO 12
319struct max8997_dev { 315struct max8997_dev {
320 struct device *dev; 316 struct device *dev;
diff --git a/include/linux/mfd/pm8xxx/core.h b/include/linux/mfd/pm8xxx/core.h
new file mode 100644
index 000000000000..bd2f4f64e931
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/core.h
@@ -0,0 +1,81 @@
1/*
2 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/*
14 * Qualcomm PMIC 8xxx driver header file
15 *
16 */
17
18#ifndef __MFD_PM8XXX_CORE_H
19#define __MFD_PM8XXX_CORE_H
20
21#include <linux/mfd/core.h>
22
23struct pm8xxx_drvdata {
24 int (*pmic_readb) (const struct device *dev, u16 addr, u8 *val);
25 int (*pmic_writeb) (const struct device *dev, u16 addr, u8 val);
26 int (*pmic_read_buf) (const struct device *dev, u16 addr, u8 *buf,
27 int n);
28 int (*pmic_write_buf) (const struct device *dev, u16 addr, u8 *buf,
29 int n);
30 int (*pmic_read_irq_stat) (const struct device *dev, int irq);
31 void *pm_chip_data;
32};
33
34static inline int pm8xxx_readb(const struct device *dev, u16 addr, u8 *val)
35{
36 struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
37
38 if (!dd)
39 return -EINVAL;
40 return dd->pmic_readb(dev, addr, val);
41}
42
43static inline int pm8xxx_writeb(const struct device *dev, u16 addr, u8 val)
44{
45 struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
46
47 if (!dd)
48 return -EINVAL;
49 return dd->pmic_writeb(dev, addr, val);
50}
51
52static inline int pm8xxx_read_buf(const struct device *dev, u16 addr, u8 *buf,
53 int n)
54{
55 struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
56
57 if (!dd)
58 return -EINVAL;
59 return dd->pmic_read_buf(dev, addr, buf, n);
60}
61
62static inline int pm8xxx_write_buf(const struct device *dev, u16 addr, u8 *buf,
63 int n)
64{
65 struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
66
67 if (!dd)
68 return -EINVAL;
69 return dd->pmic_write_buf(dev, addr, buf, n);
70}
71
72static inline int pm8xxx_read_irq_stat(const struct device *dev, int irq)
73{
74 struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
75
76 if (!dd)
77 return -EINVAL;
78 return dd->pmic_read_irq_stat(dev, irq);
79}
80
81#endif
diff --git a/include/linux/mfd/pm8xxx/irq.h b/include/linux/mfd/pm8xxx/irq.h
new file mode 100644
index 000000000000..4b21769f4483
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/irq.h
@@ -0,0 +1,59 @@
1/*
2 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/*
14 * Qualcomm PMIC irq 8xxx driver header file
15 *
16 */
17
18#ifndef __MFD_PM8XXX_IRQ_H
19#define __MFD_PM8XXX_IRQ_H
20
21#include <linux/errno.h>
22#include <linux/err.h>
23
24struct pm8xxx_irq_core_data {
25 u32 rev;
26 int nirqs;
27};
28
29struct pm8xxx_irq_platform_data {
30 int irq_base;
31 struct pm8xxx_irq_core_data irq_cdata;
32 int devirq;
33 int irq_trigger_flag;
34};
35
36struct pm_irq_chip;
37
38#ifdef CONFIG_MFD_PM8XXX_IRQ
39int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq);
40struct pm_irq_chip * __devinit pm8xxx_irq_init(struct device *dev,
41 const struct pm8xxx_irq_platform_data *pdata);
42int __devexit pm8xxx_irq_exit(struct pm_irq_chip *chip);
43#else
44static inline int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq)
45{
46 return -ENXIO;
47}
48static inline struct pm_irq_chip * __devinit pm8xxx_irq_init(
49 const struct device *dev,
50 const struct pm8xxx_irq_platform_data *pdata)
51{
52 return ERR_PTR(-ENXIO);
53}
54static inline int __devexit pm8xxx_irq_exit(struct pm_irq_chip *chip)
55{
56 return -ENXIO;
57}
58#endif /* CONFIG_MFD_PM8XXX_IRQ */
59#endif /* __MFD_PM8XXX_IRQ_H */
diff --git a/include/linux/mfd/pm8xxx/pm8921.h b/include/linux/mfd/pm8xxx/pm8921.h
new file mode 100644
index 000000000000..d5517fd32d1b
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/pm8921.h
@@ -0,0 +1,31 @@
1/*
2 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/*
14 * Qualcomm PMIC 8921 driver header file
15 *
16 */
17
18#ifndef __MFD_PM8921_H
19#define __MFD_PM8921_H
20
21#include <linux/device.h>
22#include <linux/mfd/pm8xxx/irq.h>
23
24#define PM8921_NR_IRQS 256
25
26struct pm8921_platform_data {
27 int irq_base;
28 struct pm8xxx_irq_platform_data *irq_pdata;
29};
30
31#endif
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index 8e70310ee945..5a90266c3a5a 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -4,6 +4,7 @@
4#include <linux/fb.h> 4#include <linux/fb.h>
5#include <linux/io.h> 5#include <linux/io.h>
6#include <linux/platform_device.h> 6#include <linux/platform_device.h>
7#include <linux/pm_runtime.h>
7 8
8#define tmio_ioread8(addr) readb(addr) 9#define tmio_ioread8(addr) readb(addr)
9#define tmio_ioread16(addr) readw(addr) 10#define tmio_ioread16(addr) readw(addr)
@@ -61,6 +62,12 @@
61 * Some controllers can support SDIO IRQ signalling. 62 * Some controllers can support SDIO IRQ signalling.
62 */ 63 */
63#define TMIO_MMC_SDIO_IRQ (1 << 2) 64#define TMIO_MMC_SDIO_IRQ (1 << 2)
65/*
66 * Some platforms can detect card insertion events with controller powered
67 * down, in which case they have to call tmio_mmc_cd_wakeup() to power up the
68 * controller and report the event to the driver.
69 */
70#define TMIO_MMC_HAS_COLD_CD (1 << 3)
64 71
65int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); 72int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
66int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); 73int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
@@ -82,11 +89,21 @@ struct tmio_mmc_data {
82 unsigned long flags; 89 unsigned long flags;
83 u32 ocr_mask; /* available voltages */ 90 u32 ocr_mask; /* available voltages */
84 struct tmio_mmc_dma *dma; 91 struct tmio_mmc_dma *dma;
92 struct device *dev;
93 bool power;
85 void (*set_pwr)(struct platform_device *host, int state); 94 void (*set_pwr)(struct platform_device *host, int state);
86 void (*set_clk_div)(struct platform_device *host, int state); 95 void (*set_clk_div)(struct platform_device *host, int state);
87 int (*get_cd)(struct platform_device *host); 96 int (*get_cd)(struct platform_device *host);
88}; 97};
89 98
99static inline void tmio_mmc_cd_wakeup(struct tmio_mmc_data *pdata)
100{
101 if (pdata && !pdata->power) {
102 pdata->power = true;
103 pm_runtime_get(pdata->dev);
104 }
105}
106
90/* 107/*
91 * data for the NAND controller 108 * data for the NAND controller
92 */ 109 */
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
new file mode 100644
index 000000000000..8bb85b930c07
--- /dev/null
+++ b/include/linux/mfd/tps65910.h
@@ -0,0 +1,800 @@
1/*
2 * tps65910.h -- TI TPS6591x
3 *
4 * Copyright 2010-2011 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8 * Author: Arnaud Deconinck <a-deconinck@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#ifndef __LINUX_MFD_TPS65910_H
18#define __LINUX_MFD_TPS65910_H
19
20/* TPS chip id list */
21#define TPS65910 0
22#define TPS65911 1
23
24/* TPS regulator type list */
25#define REGULATOR_LDO 0
26#define REGULATOR_DCDC 1
27
28/*
29 * List of registers for component TPS65910
30 *
31 */
32
33#define TPS65910_SECONDS 0x0
34#define TPS65910_MINUTES 0x1
35#define TPS65910_HOURS 0x2
36#define TPS65910_DAYS 0x3
37#define TPS65910_MONTHS 0x4
38#define TPS65910_YEARS 0x5
39#define TPS65910_WEEKS 0x6
40#define TPS65910_ALARM_SECONDS 0x8
41#define TPS65910_ALARM_MINUTES 0x9
42#define TPS65910_ALARM_HOURS 0xA
43#define TPS65910_ALARM_DAYS 0xB
44#define TPS65910_ALARM_MONTHS 0xC
45#define TPS65910_ALARM_YEARS 0xD
46#define TPS65910_RTC_CTRL 0x10
47#define TPS65910_RTC_STATUS 0x11
48#define TPS65910_RTC_INTERRUPTS 0x12
49#define TPS65910_RTC_COMP_LSB 0x13
50#define TPS65910_RTC_COMP_MSB 0x14
51#define TPS65910_RTC_RES_PROG 0x15
52#define TPS65910_RTC_RESET_STATUS 0x16
53#define TPS65910_BCK1 0x17
54#define TPS65910_BCK2 0x18
55#define TPS65910_BCK3 0x19
56#define TPS65910_BCK4 0x1A
57#define TPS65910_BCK5 0x1B
58#define TPS65910_PUADEN 0x1C
59#define TPS65910_REF 0x1D
60#define TPS65910_VRTC 0x1E
61#define TPS65910_VIO 0x20
62#define TPS65910_VDD1 0x21
63#define TPS65910_VDD1_OP 0x22
64#define TPS65910_VDD1_SR 0x23
65#define TPS65910_VDD2 0x24
66#define TPS65910_VDD2_OP 0x25
67#define TPS65910_VDD2_SR 0x26
68#define TPS65910_VDD3 0x27
69#define TPS65910_VDIG1 0x30
70#define TPS65910_VDIG2 0x31
71#define TPS65910_VAUX1 0x32
72#define TPS65910_VAUX2 0x33
73#define TPS65910_VAUX33 0x34
74#define TPS65910_VMMC 0x35
75#define TPS65910_VPLL 0x36
76#define TPS65910_VDAC 0x37
77#define TPS65910_THERM 0x38
78#define TPS65910_BBCH 0x39
79#define TPS65910_DCDCCTRL 0x3E
80#define TPS65910_DEVCTRL 0x3F
81#define TPS65910_DEVCTRL2 0x40
82#define TPS65910_SLEEP_KEEP_LDO_ON 0x41
83#define TPS65910_SLEEP_KEEP_RES_ON 0x42
84#define TPS65910_SLEEP_SET_LDO_OFF 0x43
85#define TPS65910_SLEEP_SET_RES_OFF 0x44
86#define TPS65910_EN1_LDO_ASS 0x45
87#define TPS65910_EN1_SMPS_ASS 0x46
88#define TPS65910_EN2_LDO_ASS 0x47
89#define TPS65910_EN2_SMPS_ASS 0x48
90#define TPS65910_EN3_LDO_ASS 0x49
91#define TPS65910_SPARE 0x4A
92#define TPS65910_INT_STS 0x50
93#define TPS65910_INT_MSK 0x51
94#define TPS65910_INT_STS2 0x52
95#define TPS65910_INT_MSK2 0x53
96#define TPS65910_INT_STS3 0x54
97#define TPS65910_INT_MSK3 0x55
98#define TPS65910_GPIO0 0x60
99#define TPS65910_GPIO1 0x61
100#define TPS65910_GPIO2 0x62
101#define TPS65910_GPIO3 0x63
102#define TPS65910_GPIO4 0x64
103#define TPS65910_GPIO5 0x65
104#define TPS65910_GPIO6 0x66
105#define TPS65910_GPIO7 0x67
106#define TPS65910_GPIO8 0x68
107#define TPS65910_JTAGVERNUM 0x80
108#define TPS65910_MAX_REGISTER 0x80
109
110/*
111 * List of registers specific to TPS65911
112 */
113#define TPS65911_VDDCTRL 0x27
114#define TPS65911_VDDCTRL_OP 0x28
115#define TPS65911_VDDCTRL_SR 0x29
116#define TPS65911_LDO1 0x30
117#define TPS65911_LDO2 0x31
118#define TPS65911_LDO5 0x32
119#define TPS65911_LDO8 0x33
120#define TPS65911_LDO7 0x34
121#define TPS65911_LDO6 0x35
122#define TPS65911_LDO4 0x36
123#define TPS65911_LDO3 0x37
124#define TPS65911_VMBCH 0x6A
125#define TPS65911_VMBCH2 0x6B
126
127/*
128 * List of register bitfields for component TPS65910
129 *
130 */
131
132
133/*Register BCK1 (0x80) register.RegisterDescription */
134#define BCK1_BCKUP_MASK 0xFF
135#define BCK1_BCKUP_SHIFT 0
136
137
138/*Register BCK2 (0x80) register.RegisterDescription */
139#define BCK2_BCKUP_MASK 0xFF
140#define BCK2_BCKUP_SHIFT 0
141
142
143/*Register BCK3 (0x80) register.RegisterDescription */
144#define BCK3_BCKUP_MASK 0xFF
145#define BCK3_BCKUP_SHIFT 0
146
147
148/*Register BCK4 (0x80) register.RegisterDescription */
149#define BCK4_BCKUP_MASK 0xFF
150#define BCK4_BCKUP_SHIFT 0
151
152
153/*Register BCK5 (0x80) register.RegisterDescription */
154#define BCK5_BCKUP_MASK 0xFF
155#define BCK5_BCKUP_SHIFT 0
156
157
158/*Register PUADEN (0x80) register.RegisterDescription */
159#define PUADEN_EN3P_MASK 0x80
160#define PUADEN_EN3P_SHIFT 7
161#define PUADEN_I2CCTLP_MASK 0x40
162#define PUADEN_I2CCTLP_SHIFT 6
163#define PUADEN_I2CSRP_MASK 0x20
164#define PUADEN_I2CSRP_SHIFT 5
165#define PUADEN_PWRONP_MASK 0x10
166#define PUADEN_PWRONP_SHIFT 4
167#define PUADEN_SLEEPP_MASK 0x08
168#define PUADEN_SLEEPP_SHIFT 3
169#define PUADEN_PWRHOLDP_MASK 0x04
170#define PUADEN_PWRHOLDP_SHIFT 2
171#define PUADEN_BOOT1P_MASK 0x02
172#define PUADEN_BOOT1P_SHIFT 1
173#define PUADEN_BOOT0P_MASK 0x01
174#define PUADEN_BOOT0P_SHIFT 0
175
176
177/*Register REF (0x80) register.RegisterDescription */
178#define REF_VMBCH_SEL_MASK 0x0C
179#define REF_VMBCH_SEL_SHIFT 2
180#define REF_ST_MASK 0x03
181#define REF_ST_SHIFT 0
182
183
184/*Register VRTC (0x80) register.RegisterDescription */
185#define VRTC_VRTC_OFFMASK_MASK 0x08
186#define VRTC_VRTC_OFFMASK_SHIFT 3
187#define VRTC_ST_MASK 0x03
188#define VRTC_ST_SHIFT 0
189
190
191/*Register VIO (0x80) register.RegisterDescription */
192#define VIO_ILMAX_MASK 0xC0
193#define VIO_ILMAX_SHIFT 6
194#define VIO_SEL_MASK 0x0C
195#define VIO_SEL_SHIFT 2
196#define VIO_ST_MASK 0x03
197#define VIO_ST_SHIFT 0
198
199
200/*Register VDD1 (0x80) register.RegisterDescription */
201#define VDD1_VGAIN_SEL_MASK 0xC0
202#define VDD1_VGAIN_SEL_SHIFT 6
203#define VDD1_ILMAX_MASK 0x20
204#define VDD1_ILMAX_SHIFT 5
205#define VDD1_TSTEP_MASK 0x1C
206#define VDD1_TSTEP_SHIFT 2
207#define VDD1_ST_MASK 0x03
208#define VDD1_ST_SHIFT 0
209
210
211/*Register VDD1_OP (0x80) register.RegisterDescription */
212#define VDD1_OP_CMD_MASK 0x80
213#define VDD1_OP_CMD_SHIFT 7
214#define VDD1_OP_SEL_MASK 0x7F
215#define VDD1_OP_SEL_SHIFT 0
216
217
218/*Register VDD1_SR (0x80) register.RegisterDescription */
219#define VDD1_SR_SEL_MASK 0x7F
220#define VDD1_SR_SEL_SHIFT 0
221
222
223/*Register VDD2 (0x80) register.RegisterDescription */
224#define VDD2_VGAIN_SEL_MASK 0xC0
225#define VDD2_VGAIN_SEL_SHIFT 6
226#define VDD2_ILMAX_MASK 0x20
227#define VDD2_ILMAX_SHIFT 5
228#define VDD2_TSTEP_MASK 0x1C
229#define VDD2_TSTEP_SHIFT 2
230#define VDD2_ST_MASK 0x03
231#define VDD2_ST_SHIFT 0
232
233
234/*Register VDD2_OP (0x80) register.RegisterDescription */
235#define VDD2_OP_CMD_MASK 0x80
236#define VDD2_OP_CMD_SHIFT 7
237#define VDD2_OP_SEL_MASK 0x7F
238#define VDD2_OP_SEL_SHIFT 0
239
240/*Register VDD2_SR (0x80) register.RegisterDescription */
241#define VDD2_SR_SEL_MASK 0x7F
242#define VDD2_SR_SEL_SHIFT 0
243
244
245/*Registers VDD1, VDD2 voltage values definitions */
246#define VDD1_2_NUM_VOLTS 73
247#define VDD1_2_MIN_VOLT 6000
248#define VDD1_2_OFFSET 125
249
250
251/*Register VDD3 (0x80) register.RegisterDescription */
252#define VDD3_CKINEN_MASK 0x04
253#define VDD3_CKINEN_SHIFT 2
254#define VDD3_ST_MASK 0x03
255#define VDD3_ST_SHIFT 0
256#define VDDCTRL_MIN_VOLT 6000
257#define VDDCTRL_OFFSET 125
258
259/*Registers VDIG (0x80) to VDAC register.RegisterDescription */
260#define LDO_SEL_MASK 0x0C
261#define LDO_SEL_SHIFT 2
262#define LDO_ST_MASK 0x03
263#define LDO_ST_SHIFT 0
264#define LDO_ST_ON_BIT 0x01
265#define LDO_ST_MODE_BIT 0x02
266
267
268/* Registers LDO1 to LDO8 in tps65910 */
269#define LDO1_SEL_MASK 0xFC
270#define LDO3_SEL_MASK 0x7C
271#define LDO_MIN_VOLT 1000
272#define LDO_MAX_VOLT 3300;
273
274
275/*Register VDIG1 (0x80) register.RegisterDescription */
276#define VDIG1_SEL_MASK 0x0C
277#define VDIG1_SEL_SHIFT 2
278#define VDIG1_ST_MASK 0x03
279#define VDIG1_ST_SHIFT 0
280
281
282/*Register VDIG2 (0x80) register.RegisterDescription */
283#define VDIG2_SEL_MASK 0x0C
284#define VDIG2_SEL_SHIFT 2
285#define VDIG2_ST_MASK 0x03
286#define VDIG2_ST_SHIFT 0
287
288
289/*Register VAUX1 (0x80) register.RegisterDescription */
290#define VAUX1_SEL_MASK 0x0C
291#define VAUX1_SEL_SHIFT 2
292#define VAUX1_ST_MASK 0x03
293#define VAUX1_ST_SHIFT 0
294
295
296/*Register VAUX2 (0x80) register.RegisterDescription */
297#define VAUX2_SEL_MASK 0x0C
298#define VAUX2_SEL_SHIFT 2
299#define VAUX2_ST_MASK 0x03
300#define VAUX2_ST_SHIFT 0
301
302
303/*Register VAUX33 (0x80) register.RegisterDescription */
304#define VAUX33_SEL_MASK 0x0C
305#define VAUX33_SEL_SHIFT 2
306#define VAUX33_ST_MASK 0x03
307#define VAUX33_ST_SHIFT 0
308
309
310/*Register VMMC (0x80) register.RegisterDescription */
311#define VMMC_SEL_MASK 0x0C
312#define VMMC_SEL_SHIFT 2
313#define VMMC_ST_MASK 0x03
314#define VMMC_ST_SHIFT 0
315
316
317/*Register VPLL (0x80) register.RegisterDescription */
318#define VPLL_SEL_MASK 0x0C
319#define VPLL_SEL_SHIFT 2
320#define VPLL_ST_MASK 0x03
321#define VPLL_ST_SHIFT 0
322
323
324/*Register VDAC (0x80) register.RegisterDescription */
325#define VDAC_SEL_MASK 0x0C
326#define VDAC_SEL_SHIFT 2
327#define VDAC_ST_MASK 0x03
328#define VDAC_ST_SHIFT 0
329
330
331/*Register THERM (0x80) register.RegisterDescription */
332#define THERM_THERM_HD_MASK 0x20
333#define THERM_THERM_HD_SHIFT 5
334#define THERM_THERM_TS_MASK 0x10
335#define THERM_THERM_TS_SHIFT 4
336#define THERM_THERM_HDSEL_MASK 0x0C
337#define THERM_THERM_HDSEL_SHIFT 2
338#define THERM_RSVD1_MASK 0x02
339#define THERM_RSVD1_SHIFT 1
340#define THERM_THERM_STATE_MASK 0x01
341#define THERM_THERM_STATE_SHIFT 0
342
343
344/*Register BBCH (0x80) register.RegisterDescription */
345#define BBCH_BBSEL_MASK 0x06
346#define BBCH_BBSEL_SHIFT 1
347#define BBCH_BBCHEN_MASK 0x01
348#define BBCH_BBCHEN_SHIFT 0
349
350
351/*Register DCDCCTRL (0x80) register.RegisterDescription */
352#define DCDCCTRL_VDD2_PSKIP_MASK 0x20
353#define DCDCCTRL_VDD2_PSKIP_SHIFT 5
354#define DCDCCTRL_VDD1_PSKIP_MASK 0x10
355#define DCDCCTRL_VDD1_PSKIP_SHIFT 4
356#define DCDCCTRL_VIO_PSKIP_MASK 0x08
357#define DCDCCTRL_VIO_PSKIP_SHIFT 3
358#define DCDCCTRL_DCDCCKEXT_MASK 0x04
359#define DCDCCTRL_DCDCCKEXT_SHIFT 2
360#define DCDCCTRL_DCDCCKSYNC_MASK 0x03
361#define DCDCCTRL_DCDCCKSYNC_SHIFT 0
362
363
364/*Register DEVCTRL (0x80) register.RegisterDescription */
365#define DEVCTRL_RTC_PWDN_MASK 0x40
366#define DEVCTRL_RTC_PWDN_SHIFT 6
367#define DEVCTRL_CK32K_CTRL_MASK 0x20
368#define DEVCTRL_CK32K_CTRL_SHIFT 5
369#define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10
370#define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4
371#define DEVCTRL_DEV_OFF_RST_MASK 0x08
372#define DEVCTRL_DEV_OFF_RST_SHIFT 3
373#define DEVCTRL_DEV_ON_MASK 0x04
374#define DEVCTRL_DEV_ON_SHIFT 2
375#define DEVCTRL_DEV_SLP_MASK 0x02
376#define DEVCTRL_DEV_SLP_SHIFT 1
377#define DEVCTRL_DEV_OFF_MASK 0x01
378#define DEVCTRL_DEV_OFF_SHIFT 0
379
380
381/*Register DEVCTRL2 (0x80) register.RegisterDescription */
382#define DEVCTRL2_TSLOT_LENGTH_MASK 0x30
383#define DEVCTRL2_TSLOT_LENGTH_SHIFT 4
384#define DEVCTRL2_SLEEPSIG_POL_MASK 0x08
385#define DEVCTRL2_SLEEPSIG_POL_SHIFT 3
386#define DEVCTRL2_PWON_LP_OFF_MASK 0x04
387#define DEVCTRL2_PWON_LP_OFF_SHIFT 2
388#define DEVCTRL2_PWON_LP_RST_MASK 0x02
389#define DEVCTRL2_PWON_LP_RST_SHIFT 1
390#define DEVCTRL2_IT_POL_MASK 0x01
391#define DEVCTRL2_IT_POL_SHIFT 0
392
393
394/*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */
395#define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80
396#define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7
397#define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40
398#define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6
399#define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20
400#define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5
401#define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10
402#define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4
403#define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08
404#define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3
405#define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04
406#define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2
407#define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02
408#define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1
409#define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01
410#define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0
411
412
413/*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */
414#define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80
415#define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7
416#define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40
417#define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6
418#define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20
419#define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5
420#define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10
421#define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4
422#define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08
423#define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3
424#define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04
425#define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2
426#define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02
427#define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1
428#define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01
429#define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0
430
431
432/*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */
433#define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80
434#define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7
435#define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40
436#define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6
437#define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20
438#define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5
439#define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10
440#define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4
441#define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08
442#define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3
443#define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04
444#define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2
445#define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02
446#define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1
447#define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01
448#define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0
449
450
451/*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */
452#define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80
453#define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7
454#define SLEEP_SET_RES_OFF_RSVD_MASK 0x60
455#define SLEEP_SET_RES_OFF_RSVD_SHIFT 5
456#define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10
457#define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4
458#define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08
459#define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3
460#define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04
461#define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2
462#define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02
463#define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1
464#define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01
465#define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0
466
467
468/*Register EN1_LDO_ASS (0x80) register.RegisterDescription */
469#define EN1_LDO_ASS_VDAC_EN1_MASK 0x80
470#define EN1_LDO_ASS_VDAC_EN1_SHIFT 7
471#define EN1_LDO_ASS_VPLL_EN1_MASK 0x40
472#define EN1_LDO_ASS_VPLL_EN1_SHIFT 6
473#define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20
474#define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5
475#define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10
476#define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4
477#define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08
478#define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3
479#define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04
480#define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2
481#define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02
482#define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1
483#define EN1_LDO_ASS_VMMC_EN1_MASK 0x01
484#define EN1_LDO_ASS_VMMC_EN1_SHIFT 0
485
486
487/*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */
488#define EN1_SMPS_ASS_RSVD_MASK 0xE0
489#define EN1_SMPS_ASS_RSVD_SHIFT 5
490#define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10
491#define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4
492#define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08
493#define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3
494#define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04
495#define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2
496#define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02
497#define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1
498#define EN1_SMPS_ASS_VIO_EN1_MASK 0x01
499#define EN1_SMPS_ASS_VIO_EN1_SHIFT 0
500
501
502/*Register EN2_LDO_ASS (0x80) register.RegisterDescription */
503#define EN2_LDO_ASS_VDAC_EN2_MASK 0x80
504#define EN2_LDO_ASS_VDAC_EN2_SHIFT 7
505#define EN2_LDO_ASS_VPLL_EN2_MASK 0x40
506#define EN2_LDO_ASS_VPLL_EN2_SHIFT 6
507#define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20
508#define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5
509#define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10
510#define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4
511#define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08
512#define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3
513#define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04
514#define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2
515#define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02
516#define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1
517#define EN2_LDO_ASS_VMMC_EN2_MASK 0x01
518#define EN2_LDO_ASS_VMMC_EN2_SHIFT 0
519
520
521/*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */
522#define EN2_SMPS_ASS_RSVD_MASK 0xE0
523#define EN2_SMPS_ASS_RSVD_SHIFT 5
524#define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10
525#define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4
526#define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08
527#define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3
528#define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04
529#define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2
530#define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02
531#define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1
532#define EN2_SMPS_ASS_VIO_EN2_MASK 0x01
533#define EN2_SMPS_ASS_VIO_EN2_SHIFT 0
534
535
536/*Register EN3_LDO_ASS (0x80) register.RegisterDescription */
537#define EN3_LDO_ASS_VDAC_EN3_MASK 0x80
538#define EN3_LDO_ASS_VDAC_EN3_SHIFT 7
539#define EN3_LDO_ASS_VPLL_EN3_MASK 0x40
540#define EN3_LDO_ASS_VPLL_EN3_SHIFT 6
541#define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20
542#define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5
543#define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10
544#define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4
545#define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08
546#define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3
547#define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04
548#define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2
549#define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02
550#define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1
551#define EN3_LDO_ASS_VMMC_EN3_MASK 0x01
552#define EN3_LDO_ASS_VMMC_EN3_SHIFT 0
553
554
555/*Register SPARE (0x80) register.RegisterDescription */
556#define SPARE_SPARE_MASK 0xFF
557#define SPARE_SPARE_SHIFT 0
558
559
560/*Register INT_STS (0x80) register.RegisterDescription */
561#define INT_STS_RTC_PERIOD_IT_MASK 0x80
562#define INT_STS_RTC_PERIOD_IT_SHIFT 7
563#define INT_STS_RTC_ALARM_IT_MASK 0x40
564#define INT_STS_RTC_ALARM_IT_SHIFT 6
565#define INT_STS_HOTDIE_IT_MASK 0x20
566#define INT_STS_HOTDIE_IT_SHIFT 5
567#define INT_STS_PWRHOLD_IT_MASK 0x10
568#define INT_STS_PWRHOLD_IT_SHIFT 4
569#define INT_STS_PWRON_LP_IT_MASK 0x08
570#define INT_STS_PWRON_LP_IT_SHIFT 3
571#define INT_STS_PWRON_IT_MASK 0x04
572#define INT_STS_PWRON_IT_SHIFT 2
573#define INT_STS_VMBHI_IT_MASK 0x02
574#define INT_STS_VMBHI_IT_SHIFT 1
575#define INT_STS_VMBDCH_IT_MASK 0x01
576#define INT_STS_VMBDCH_IT_SHIFT 0
577
578
579/*Register INT_MSK (0x80) register.RegisterDescription */
580#define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80
581#define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7
582#define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40
583#define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6
584#define INT_MSK_HOTDIE_IT_MSK_MASK 0x20
585#define INT_MSK_HOTDIE_IT_MSK_SHIFT 5
586#define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10
587#define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4
588#define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
589#define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3
590#define INT_MSK_PWRON_IT_MSK_MASK 0x04
591#define INT_MSK_PWRON_IT_MSK_SHIFT 2
592#define INT_MSK_VMBHI_IT_MSK_MASK 0x02
593#define INT_MSK_VMBHI_IT_MSK_SHIFT 1
594#define INT_MSK_VMBDCH_IT_MSK_MASK 0x01
595#define INT_MSK_VMBDCH_IT_MSK_SHIFT 0
596
597
598/*Register INT_STS2 (0x80) register.RegisterDescription */
599#define INT_STS2_GPIO3_F_IT_MASK 0x80
600#define INT_STS2_GPIO3_F_IT_SHIFT 7
601#define INT_STS2_GPIO3_R_IT_MASK 0x40
602#define INT_STS2_GPIO3_R_IT_SHIFT 6
603#define INT_STS2_GPIO2_F_IT_MASK 0x20
604#define INT_STS2_GPIO2_F_IT_SHIFT 5
605#define INT_STS2_GPIO2_R_IT_MASK 0x10
606#define INT_STS2_GPIO2_R_IT_SHIFT 4
607#define INT_STS2_GPIO1_F_IT_MASK 0x08
608#define INT_STS2_GPIO1_F_IT_SHIFT 3
609#define INT_STS2_GPIO1_R_IT_MASK 0x04
610#define INT_STS2_GPIO1_R_IT_SHIFT 2
611#define INT_STS2_GPIO0_F_IT_MASK 0x02
612#define INT_STS2_GPIO0_F_IT_SHIFT 1
613#define INT_STS2_GPIO0_R_IT_MASK 0x01
614#define INT_STS2_GPIO0_R_IT_SHIFT 0
615
616
617/*Register INT_MSK2 (0x80) register.RegisterDescription */
618#define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80
619#define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7
620#define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40
621#define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6
622#define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20
623#define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5
624#define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10
625#define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4
626#define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08
627#define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3
628#define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04
629#define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2
630#define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02
631#define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1
632#define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01
633#define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0
634
635
636/*Register INT_STS3 (0x80) register.RegisterDescription */
637#define INT_STS3_GPIO5_F_IT_MASK 0x08
638#define INT_STS3_GPIO5_F_IT_SHIFT 3
639#define INT_STS3_GPIO5_R_IT_MASK 0x04
640#define INT_STS3_GPIO5_R_IT_SHIFT 2
641#define INT_STS3_GPIO4_F_IT_MASK 0x02
642#define INT_STS3_GPIO4_F_IT_SHIFT 1
643#define INT_STS3_GPIO4_R_IT_MASK 0x01
644#define INT_STS3_GPIO4_R_IT_SHIFT 0
645
646
647/*Register INT_MSK3 (0x80) register.RegisterDescription */
648#define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08
649#define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3
650#define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04
651#define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2
652#define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02
653#define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1
654#define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01
655#define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0
656
657
658/*Register GPIO (0x80) register.RegisterDescription */
659#define GPIO_DEB_MASK 0x10
660#define GPIO_DEB_SHIFT 4
661#define GPIO_PUEN_MASK 0x08
662#define GPIO_PUEN_SHIFT 3
663#define GPIO_CFG_MASK 0x04
664#define GPIO_CFG_SHIFT 2
665#define GPIO_STS_MASK 0x02
666#define GPIO_STS_SHIFT 1
667#define GPIO_SET_MASK 0x01
668#define GPIO_SET_SHIFT 0
669
670
671/*Register JTAGVERNUM (0x80) register.RegisterDescription */
672#define JTAGVERNUM_VERNUM_MASK 0x0F
673#define JTAGVERNUM_VERNUM_SHIFT 0
674
675
676/* Register VDDCTRL (0x27) bit definitions */
677#define VDDCTRL_ST_MASK 0x03
678#define VDDCTRL_ST_SHIFT 0
679
680
681/*Register VDDCTRL_OP (0x28) bit definitios */
682#define VDDCTRL_OP_CMD_MASK 0x80
683#define VDDCTRL_OP_CMD_SHIFT 7
684#define VDDCTRL_OP_SEL_MASK 0x7F
685#define VDDCTRL_OP_SEL_SHIFT 0
686
687
688/*Register VDDCTRL_SR (0x29) bit definitions */
689#define VDDCTRL_SR_SEL_MASK 0x7F
690#define VDDCTRL_SR_SEL_SHIFT 0
691
692
693/* IRQ Definitions */
694#define TPS65910_IRQ_VBAT_VMBDCH 0
695#define TPS65910_IRQ_VBAT_VMHI 1
696#define TPS65910_IRQ_PWRON 2
697#define TPS65910_IRQ_PWRON_LP 3
698#define TPS65910_IRQ_PWRHOLD 4
699#define TPS65910_IRQ_HOTDIE 5
700#define TPS65910_IRQ_RTC_ALARM 6
701#define TPS65910_IRQ_RTC_PERIOD 7
702#define TPS65910_IRQ_GPIO_R 8
703#define TPS65910_IRQ_GPIO_F 9
704#define TPS65910_NUM_IRQ 10
705
706#define TPS65911_IRQ_VBAT_VMBDCH 0
707#define TPS65911_IRQ_VBAT_VMBDCH2L 1
708#define TPS65911_IRQ_VBAT_VMBDCH2H 2
709#define TPS65911_IRQ_VBAT_VMHI 3
710#define TPS65911_IRQ_PWRON 4
711#define TPS65911_IRQ_PWRON_LP 5
712#define TPS65911_IRQ_PWRHOLD_F 6
713#define TPS65911_IRQ_PWRHOLD_R 7
714#define TPS65911_IRQ_HOTDIE 8
715#define TPS65911_IRQ_RTC_ALARM 9
716#define TPS65911_IRQ_RTC_PERIOD 10
717#define TPS65911_IRQ_GPIO0_R 11
718#define TPS65911_IRQ_GPIO0_F 12
719#define TPS65911_IRQ_GPIO1_R 13
720#define TPS65911_IRQ_GPIO1_F 14
721#define TPS65911_IRQ_GPIO2_R 15
722#define TPS65911_IRQ_GPIO2_F 16
723#define TPS65911_IRQ_GPIO3_R 17
724#define TPS65911_IRQ_GPIO3_F 18
725#define TPS65911_IRQ_GPIO4_R 19
726#define TPS65911_IRQ_GPIO4_F 20
727#define TPS65911_IRQ_GPIO5_R 21
728#define TPS65911_IRQ_GPIO5_F 22
729#define TPS65911_IRQ_WTCHDG 23
730#define TPS65911_IRQ_PWRDN 24
731
732#define TPS65911_NUM_IRQ 25
733
734
735/* GPIO Register Definitions */
736#define TPS65910_GPIO_DEB BIT(2)
737#define TPS65910_GPIO_PUEN BIT(3)
738#define TPS65910_GPIO_CFG BIT(2)
739#define TPS65910_GPIO_STS BIT(1)
740#define TPS65910_GPIO_SET BIT(0)
741
742/**
743 * struct tps65910_board
744 * Board platform data may be used to initialize regulators.
745 */
746
747struct tps65910_board {
748 int gpio_base;
749 int irq;
750 int irq_base;
751 int vmbch_threshold;
752 int vmbch2_threshold;
753 struct regulator_init_data *tps65910_pmic_init_data;
754};
755
756/**
757 * struct tps65910 - tps65910 sub-driver chip access routines
758 */
759
760struct tps65910 {
761 struct device *dev;
762 struct i2c_client *i2c_client;
763 struct mutex io_mutex;
764 unsigned int id;
765 int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
766 int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src);
767
768 /* Client devices */
769 struct tps65910_pmic *pmic;
770 struct tps65910_rtc *rtc;
771 struct tps65910_power *power;
772
773 /* GPIO Handling */
774 struct gpio_chip gpio;
775
776 /* IRQ Handling */
777 struct mutex irq_lock;
778 int chip_irq;
779 int irq_base;
780 int irq_num;
781 u32 irq_mask;
782};
783
784struct tps65910_platform_data {
785 int irq;
786 int irq_base;
787};
788
789int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
790int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
791void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
792int tps65910_irq_init(struct tps65910 *tps65910, int irq,
793 struct tps65910_platform_data *pdata);
794
795static inline int tps65910_chip_id(struct tps65910 *tps65910)
796{
797 return tps65910->id;
798}
799
800#endif /* __LINUX_MFD_TPS65910_H */
diff --git a/include/linux/mfd/twl4030-codec.h b/include/linux/mfd/twl4030-codec.h
index 2ec317c68e59..5cc16bbd1da1 100644
--- a/include/linux/mfd/twl4030-codec.h
+++ b/include/linux/mfd/twl4030-codec.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * MFD driver for twl4030 codec submodule 2 * MFD driver for twl4030 codec submodule
3 * 3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com> 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
5 * 5 *
6 * Copyright: (C) 2009 Nokia Corporation 6 * Copyright: (C) 2009 Nokia Corporation
7 * 7 *
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index 903280d21866..0d515ee1c247 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -301,30 +301,4 @@ int wm831x_device_suspend(struct wm831x *wm831x);
301int wm831x_irq_init(struct wm831x *wm831x, int irq); 301int wm831x_irq_init(struct wm831x *wm831x, int irq);
302void wm831x_irq_exit(struct wm831x *wm831x); 302void wm831x_irq_exit(struct wm831x *wm831x);
303 303
304static inline int __must_check wm831x_request_irq(struct wm831x *wm831x,
305 unsigned int irq,
306 irq_handler_t handler,
307 unsigned long flags,
308 const char *name,
309 void *dev)
310{
311 return request_threaded_irq(irq, NULL, handler, flags, name, dev);
312}
313
314static inline void wm831x_free_irq(struct wm831x *wm831x,
315 unsigned int irq, void *dev)
316{
317 free_irq(irq, dev);
318}
319
320static inline void wm831x_disable_irq(struct wm831x *wm831x, int irq)
321{
322 disable_irq(irq);
323}
324
325static inline void wm831x_enable_irq(struct wm831x *wm831x, int irq)
326{
327 enable_irq(irq);
328}
329
330#endif 304#endif
diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h
index 632d1567a1b6..ff42d700293f 100644
--- a/include/linux/mfd/wm831x/pdata.h
+++ b/include/linux/mfd/wm831x/pdata.h
@@ -105,6 +105,9 @@ struct wm831x_watchdog_pdata {
105#define WM831X_MAX_LDO 11 105#define WM831X_MAX_LDO 11
106#define WM831X_MAX_ISINK 2 106#define WM831X_MAX_ISINK 2
107 107
108#define WM831X_GPIO_CONFIGURE 0x10000
109#define WM831X_GPIO_NUM 16
110
108struct wm831x_pdata { 111struct wm831x_pdata {
109 /** Used to distinguish multiple WM831x chips */ 112 /** Used to distinguish multiple WM831x chips */
110 int wm831x_num; 113 int wm831x_num;
@@ -119,6 +122,7 @@ struct wm831x_pdata {
119 122
120 int irq_base; 123 int irq_base;
121 int gpio_base; 124 int gpio_base;
125 int gpio_defaults[WM831X_GPIO_NUM];
122 struct wm831x_backlight_pdata *backlight; 126 struct wm831x_backlight_pdata *backlight;
123 struct wm831x_backup_pdata *backup; 127 struct wm831x_backup_pdata *backup;
124 struct wm831x_battery_pdata *battery; 128 struct wm831x_battery_pdata *battery;
diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h
index 466b1c777aff..d12f8d635a81 100644
--- a/include/linux/mfd/wm8994/pdata.h
+++ b/include/linux/mfd/wm8994/pdata.h
@@ -32,6 +32,10 @@ struct wm8994_ldo_pdata {
32#define WM8994_EQ_REGS 20 32#define WM8994_EQ_REGS 20
33#define WM8958_MBC_CUTOFF_REGS 20 33#define WM8958_MBC_CUTOFF_REGS 20
34#define WM8958_MBC_COEFF_REGS 48 34#define WM8958_MBC_COEFF_REGS 48
35#define WM8958_MBC_COMBINED_REGS 56
36#define WM8958_VSS_HPF_REGS 2
37#define WM8958_VSS_REGS 148
38#define WM8958_ENH_EQ_REGS 32
35 39
36/** 40/**
37 * DRC configurations are specified with a label and a set of register 41 * DRC configurations are specified with a label and a set of register
@@ -71,6 +75,42 @@ struct wm8958_mbc_cfg {
71 const char *name; 75 const char *name;
72 u16 cutoff_regs[WM8958_MBC_CUTOFF_REGS]; 76 u16 cutoff_regs[WM8958_MBC_CUTOFF_REGS];
73 u16 coeff_regs[WM8958_MBC_COEFF_REGS]; 77 u16 coeff_regs[WM8958_MBC_COEFF_REGS];
78
79 /* Coefficient layout when using MBC+VSS firmware */
80 u16 combined_regs[WM8958_MBC_COMBINED_REGS];
81};
82
83/**
84 * VSS HPF configurations are specified with a label and two values to
85 * write. Configurations are expected to be generated using the
86 * multiband compressor configuration panel in WISCE - see
87 * http://www.wolfsonmicro.com/wisce/
88 */
89struct wm8958_vss_hpf_cfg {
90 const char *name;
91 u16 regs[WM8958_VSS_HPF_REGS];
92};
93
94/**
95 * VSS configurations are specified with a label and array of values
96 * to write. Configurations are expected to be generated using the
97 * multiband compressor configuration panel in WISCE - see
98 * http://www.wolfsonmicro.com/wisce/
99 */
100struct wm8958_vss_cfg {
101 const char *name;
102 u16 regs[WM8958_VSS_REGS];
103};
104
105/**
106 * Enhanced EQ configurations are specified with a label and array of
107 * values to write. Configurations are expected to be generated using
108 * the multiband compressor configuration panel in WISCE - see
109 * http://www.wolfsonmicro.com/wisce/
110 */
111struct wm8958_enh_eq_cfg {
112 const char *name;
113 u16 regs[WM8958_ENH_EQ_REGS];
74}; 114};
75 115
76struct wm8994_pdata { 116struct wm8994_pdata {
@@ -95,6 +135,15 @@ struct wm8994_pdata {
95 int num_mbc_cfgs; 135 int num_mbc_cfgs;
96 struct wm8958_mbc_cfg *mbc_cfgs; 136 struct wm8958_mbc_cfg *mbc_cfgs;
97 137
138 int num_vss_cfgs;
139 struct wm8958_vss_cfg *vss_cfgs;
140
141 int num_vss_hpf_cfgs;
142 struct wm8958_vss_hpf_cfg *vss_hpf_cfgs;
143
144 int num_enh_eq_cfgs;
145 struct wm8958_enh_eq_cfg *enh_eq_cfgs;
146
98 /* LINEOUT can be differential or single ended */ 147 /* LINEOUT can be differential or single ended */
99 unsigned int lineout1_diff:1; 148 unsigned int lineout1_diff:1;
100 unsigned int lineout2_diff:1; 149 unsigned int lineout2_diff:1;
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-11 10:16:47 -0400